Abstract: The present inventions, in one aspect, are directed to micromachined resonator comprising: a first resonant structure extending along a first axis, wherein the first axis is different from a crystal axis of silicon, a second resonant structure extending along a second axis, wherein the second axis is different from the first axis and the crystal axis of silicon and wherein the first resonant structure is coupled to the second resonant structure, and wherein the first and second resonant structures are comprised of silicon (for example, substantially monocrystalline) and include an impurity dopant (for example, phosphorus) having a concentrations which is greater than 1019 cm-3, and preferably between 1019 cm-3 and 1021 cm-3.

Abstract: The present invention relates to a circuit failure detector comprising: an input terminal for receiving a detection signal having a first frequency from an interlock circuit; a correction circuit for correcting the voltage of the received detection signal; a first comparator comparing the corrected detection signal with a first reference voltage and outputting a high voltage signal or a low voltage signal; a second comparator inverting the corrected detection signal, comparing the inverted detection signal with a second reference voltage, and outputting the high voltage signal or the low voltage signal; a counting signal generator for generating a counting signal having a second frequency; a first coupler for coupling an output signal of the first comparator with the counting signal; a second coupler for coupling the output signal of the second comparator with the counting signal; and a controller for detecting a circuit failure on the basis of the output signal of the first coupler and the output signal of t

Abstract: A clock oscillator includes with a pullable BAW oscillator to generate an output signal with a target frequency. The BAW oscillator is based on a BAW resonator and voltage-controlled variable load capacitance, responsive to a capacitance control signal to provide a selectable load capacitance. An oscillator driver (such as a differential negative gm transconductance amplifier), is coupled to the BAW oscillator to provide an oscillation drive signal. The BAW oscillator is responsive to the oscillation drive signal to generate the output signal with a frequency based on the selectable load capacitance. The oscillator driver can include a bandpass filter network with a resonance frequency substantially at the target frequency.

Abstract: The apparatus comprises a first coupler configured to receive two output signals, having 180° phase difference, outputted from a first differential generator as two input signals, and output a first voltage signal generated by adding the two input signals and a second voltage signal corresponding to subtraction of the two input signals, a second coupler configured to receive two output signals, having 180° phase difference, outputted from a second differential generator as two input signals, and output a third voltage signal generated by adding the two input signals and a fourth voltage signal corresponding to subtraction of the two input signals, a coupling network connected to the first differential generator and the second differential generator and a third coupler configured to output a signal generated by adding the voltage signal outputted from the first coupler and corresponding voltage signal outputted from the second coupler.

Abstract: Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.

Abstract: A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.

Abstract: Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver.

Abstract: Phase and frequency recovery techniques comprising; a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality, and receiver synchronization techniques (RST) enabling by one order more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of receivers oscillator.

Abstract: An integrated power combiner is disclosed. The power combiner includes a first circular geometry primary winding having one or more inductive elements, such as an active winding with one or more driver stages. A circular geometry secondary winding is disposed adjacent to the first primary winding, such as an active winding with one or more driver stages. A second circular geometry primary winding is disposed adjacent to the secondary winding and has one or more inductive elements. One or more connections are provided between one or more of the inductive elements of the first circular geometry primary winding and one or more of the inductive elements of the second circular geometry primary winding.

Abstract: An integrated circuit distributed radio frequency oscillator comprises a semiconductor chip which includes a differential input transmission line, a differential output transmission line and, coupled in parallel between these transmission lines at spaced apart portions, a number of differential amplifier cells with adjustable delay. The output end of the output transmission line is coupled back to the input end of the input transmission line by a feedback link with a pair of on-chip capacitors. The delay introduced by the amplifier cells is variable in response to a tuning voltage applied to a differential tuning input, making the oscillator suitable for use as a distributed VCO in, e.g. a phase-locked loop circuit. The layout of the oscillator on a semiconductor chip includes the series-connected arrangement of the differential transmission lines in a rectilinear spiral path.

Abstract: A capacitive sensor includes a sensing electrode, control unit, first and second comparator wherein the sensing electrode includes a first and a second conductors. A positive input terminal of the first comparator and a negative input terminal of the second comparator are coupled to the first conductor. A positive input terminal of the second comparator and a negative input terminal of the first comparator are coupled to the second conductor. The first and second comparators respectively output first and second comparing signals according to voltages of the positive and the negative terminals thereof. The control unit charges the first conductor and discharges the second conductor when the first and second comparing signals correspondingly are in first and second logic states. The control unit is operable on the contrary when the first and second comparing signals are in opposition to the abovementioned description.

Abstract: A PLL is provided with an optimum operating point in order to have appropriately a frequency margin and a locking time. There is provided a phase looked loop which includes: a frequency divider for dividing an output signal by a dividing integer corresponding to an input code; an encoding unit for encoding the input code to generate an encoded code; and a loop filtering unit configured to adjust elements in response to the encoded code.

Abstract: Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.

Abstract: A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.

Abstract: An antenna selector selects one of the plurality of antennas according to an antenna selection signal. The antenna selector includes a voltage converter and an analog switch circuit. The voltage converter converts a power-supply voltage to a predetermined output voltage higher than the power-supply voltage. The analog switch circuit operates with the predetermined output voltage from the voltage converter or the power-supply voltage being applied thereto. A voltage converter controller controls the voltage converter to operate/halt according to a power level of the transmission signal generated by the transmitter. The predetermined output voltage is applied to the analog switch circuit when the voltage converter is operating and the power-supply voltage is applied to the analog switch circuit when the voltage converter is halted.

Abstract: An oscillator comprising a three-terminal device and circuitry coupled across a first terminal and a second terminal of the device. The circuitry is preferably operable to bias the device and feedback a select amount of noise generated by the device into the device so as to reduce a proportional amount of phase noise present at a third terminal of the device.

Abstract: A method and apparatus for calibrating a voltage-controlled device in a control loop is disclosed. The method and apparatus of the present invention maintains a control voltage of a voltage-controlled device within a high tuning sensitivity range, and thus improves the performance of the voltage-controlled device. The present inventive method and apparatus features a voltage windowing method wherein a high tuning sensitivity window is a subset of the low tuning sensitivity window. In one embodiment, the present invention maintains a control voltage within a predetermined tuning sensitivity window or range. In another embodiment, the present inventive method and apparatus calibrates a PLL that includes multiple VCOs. In yet another embodiment, the present invention calibrates control voltages to account for changes in operating temperature.

Abstract: A system and method for a novel microwave coaxial resonator oscillator using a ⅝ths wavelength resonator is described. The novel system and method provides a coaxial resonator for operation at high frequencies comprising a conductive resonator and a coaxial conductive outer shell electrically connected by an conductive end member, wherein the conductive resonator and outer shell are of a length approximately equal to (⅛+n/2) of the wavelength of the desired frequency, where n is a positive integer. The novel system and method provides a low noise oscillator for operation at high frequencies and reduces oscillator phase noise in high Q implementations.

Abstract: An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

Abstract: A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.

Abstract: A method and a lock detector circuit for phase-locked loop for detecting lock between reference signal and a feedback signal in two phases: lock detection phase and lock assertion phase. The detector circuit comprises delay circuits coupled to a first, a second D flip flops, an OR logic gate, and an AND gate. In the lock detection, the lock detector circuit compares the phases of the reference input clock with the feedback clock. If the phases of these clocks are different or not within a window of tolerance, the sample clock outputs of the first and second D flip flops are different. This condition causes the logic gate to issue a reset signal to the divide-by-64 counters. As such, the lock detection signal is low, indicating the PLL is not in lock condition. In the lock assertion phase, if the two phases are the same or within the window of tolerance, the sample clock outputs of the first and second D flip flops are the same or both low at the same time.

Abstract: An intermittent oscillation circuit is disclosed, and more particularly, relates to an intermittent oscillation circuit utilized in a RF transmitting/receiving system. The intermittent oscillation circuit of the present invention comprises an inversion circuit, a power control circuit and a power supply circuit. By utilizing the power control circuit to controlling the operation voltage level outputted from the power supply circuit, the duty cycle of oscillatory signal outputted from the inversion circuit can be adjusted. Therefore, data collision is decreased while transmitting/receiving various data in the RF transmitting/receiving system, and the power consumption is decreased at the transmitting/receiving terminal as well.

Abstract: A frequency synthesizer, a multi-channel carrier generator, and a transceiver, as well as a method for generating a sub-carrier frequency are described.

Abstract: A voltage controlled oscillator, comprising a pair of transistors connected to a tank circuit, said tank circuit including a plurality of tuning diodes connected in parallel with an inductor, said tuning diodes having cathodes connected to a common connection.

Abstract: A VCO having an automatic amplitude control circuit in the form of a sensing amplifier provided in the feedback loop to sense the oscillator amplitude and draw current away only when the positive peak voltage is above a certain value. In general, any amplifier may be used in the feedback loop that outputs current proportional to a peak positive input (in a non-linear and asymmetric fashion with respect to the changing voltage). In one example, the amplifier in the feedback loop comprises first and second transistors that are set nominally in cut off and behave as class C amplifiers. The advantage of this amplifier transistor configuration is that the amplifier they form has a low load on the LC tank circuit and a high input impedance.

Abstract: To attenuate the effects of phase noise and input jitter introduced in the reference frequency of the PLL, the zeros of the forward path transfer function are removed. As a result, the forward path does not amplify any phase noise or input jitter appearing in the reference frequency. However, overall loop stability is maintained by placing the zeros in the feedback path of the PLL. A discriminator may be placed in the feedback path to introduce the zero in the loop gain transfer function and provide stability.

Abstract: VCO (voltage controlled oscillator) circuits typically exhibit a frequency dependent variation in their output signal with respect to a tuning voltage applied to a tuning port on the VCO circuit. For a fixed tuning voltage the VCO circuit forms a stable oscillator. However, the stable oscillator formed is susceptible to both internal and external noise sources. Forming a VCO circuit from components such as varactors facilitates frequency stability and decreased noise susceptibility of the VCO circuit. A VCO formed from such components advantageously uses a summed capacitance of two or more varactors to provide decreased phase noise. Using a summed capacitance of the varactors reduces changes in output signal frequency with respect to changes in tuning voltage and thereby reduces the effects of noise by reducing a slope of this dependence.

Abstract: For a phase-locked loop, disclosed is a method (and corresponding apparatus) for reducing electromagnetic interference caused by a clock signal produced by a voltage controlled oscillator, the method comprising: generating a control signal having a first type, e.g., sinusoidal, of slight variation in magnitude relative to a nominal magnitude value thereof; and providing the slightly varying control signal to a voltage-controlled oscillator (“VCO”) to obtain a clock signal exhibiting a second type, e.g., sinusoidal, of slight variation in frequency relative to a nominal frequency value thereof. The slight variation is non-negligible.

Abstract: Systems and methods are provided for adjusting the frequency of an oscillator to compensate for oscillator frequency variations resulting from changes in oscillator parameters. Measurement systems monitor one or more oscillator parameters. The capacitance of the oscillator is selectively adjusted based on the measurement of the one or more oscillator parameters. The change in capacitance compensates for changes in environmental and operating conditions that affect the oscillator parameters, such as temperature and applied voltage, and produces a relatively stable output frequency over a specified operating range.

Abstract: A voltage controlled oscillator (600) includes a voltage to current portion (400) that is inversely proportional to the semiconductor processing in order to compensate for variations both in the low-frequency and high-frequency portions of the VCO gain response. To compensate for low-frequency variations, a portion of the control current (ICTL), non-compensated control current ICTLNC (436), is subtracted from a reference current IREF (408) and the result, a low-frequency compensating control current, ICTLLF (438), is added to the non-compensated control current ICTLNC (436). To compensate for high frequency variations, a number of differential transistor pairs (410-416) are provided that have tail currents that are inversely proportional to the processing. One input (426) to all the differential pairs is connected to the VCO's control voltage while the other inputs (418-424) are connected to successively increasing voltages in the control voltage range.

Abstract: A cross-coupled voltage controlled oscillator having reduced phase noise. A pair of bipolar transistors having common emitter connections are coupled to reduce that oscillation frequency which is determined from a tuning circuit connected across the collectors of transistors. First and second varactor diodes provide analog tuning of the circuit, and a digitally controlled capacitor provides for a selection of a band of frequencies to be tuned by the varactor diodes. A current source provides the current to the emitter connections of the bipolar transistors. Second harmonic signals generated at the emitter of the transistors are significantly suppressed by a tuned filtered trap connected to the common emitter connections. By reducing the second harmonic signals, the phase noise or the voltage controlled oscillator can be significantly improved.

Abstract: A high frequency signal source and method of generating a high frequency signal is disclosed. An output signal is generated from a dielectric resonator oscillator and mixed with an output signal from a voltage controlled oscillator having a predetermined tuning range and part of a phase locked loop circuit to sum the frequencies for creating a final output frequency. A portion of the final output frequency is coupled into the phase locked loop circuit that is phase locked to a reference signal from a crystal reference oscillator. The voltage controlled oscillator has a tuning range that is used to compensate for the dielectric resonator oscillator initial frequency error and drift over temperature and aging while the balance of the bandwidth is used to provide the tuning range on the local oscillator output.

Abstract: An intermittent oscillation circuit is disclosed, and more particularly, relates to an intermittent oscillation circuit utilized in a RF transmitting/receiving system. The intermittent oscillation circuit of the present invention comprises an inversion circuit, a power control circuit and a power supply circuit. By utilizing the power control circuit to controlling the operation voltage level outputted from the power supply circuit, the duty cycle of oscillatory signal outputted from the inversion circuit can be adjusted. Therefore, data collision is decreased while transmitting/receiving various data in the RF transmitting/receiving system, and the power consumption is decreased at the transmitting/receiving terminal as well.

Abstract: A voltage-controlled capacitor circuit and related circuitry. The voltage-controlled capacitor circuit includes a metal-oxide semiconductor (MOS) varactor, a diode varactor, and/or a capacitor with fixed capacitance. The MOS varactor, the diode varactor and the capacitor are electrically connected in parallel or in series to form a capacitor with a preferred characteristic of voltage-controlled capacitance.

Abstract: An improved automatic frequency compensation (AFC) technique and apparatus is provided for piconet applications, e.g., BLUETOOTH™ applications. In particular, the present invention provides an offset normalizer which normalizes frequency offset against maximum deviations. By normalizing the frequency offset, before determination of an adjustment of a local oscillator, the local oscillator adjustment becomes uncorrelated with respect to gain along the receiving path (including in a demodulator). Thus, extremely precise adjustments can be made to the local oscillator in a piconet device to provide extremely precise automatic frequency compensation.

Abstract: A numerically controlled oscillator (NCO) system for generating rational frequencies with normalized phase is disclosed. In one embodiment, the system comprises a rational NCO and a simple NCO. The rational NCO generates an overflow or correction value, based on a desired rational frequency of the system, and the simple NCO uses the overflow or correction value to generate the desired rational frequency.

Abstract: A voltage controlled oscillator (VCO) has an LC tank for generating a sinusoidal wave. The VCO uses a positive feedback circuit electrically connected to the LC tank for amplifying the sinusoidal wave. In addition, the VCO includes a noise reducing circuit having a T-shaped resistor configuration connected to the positive feedback circuit. The use of the T-shaped resistor configuration allows the VCO to reduce phase noise generated by the LC tank, and provide a high SNR.

Abstract: A phase locked loop circuit is used to provide timing clocks for data bit recovery from a serial data flow. The system locks to a SYNC signal, preferably a lower frequency fifty percent duty cycle square wave with a period equal to the time of a fully framed serial data word. When a start signal transition is detected the system is prevented from trying to lock onto the data signal edge transitions. But, the system provides a signal suitable for clocking in the individual data bits.

Abstract: A programmable capacitive network for use in a tunable resonant circuit is set forth that may be used in a number of different applications, but is particularly useful in the tuning of a voltage controlled oscillator formed on a substrate, such as a semiconductor substrate or the like. The programmable capacitive network includes a plurality of capacitive elements. An interconnected network of voltage gate elements and fuse elements are interconnected with the capacitive elements to selectively connect one or more of the plurality of capacitive elements in the resonant circuit in response to at least one program control signal. In accordance with one embodiment, the voltage gate elements are diodes.

Abstract: An LC oscillator includes inductors, a variable capacitor section, an adjusting section for varying the capacitance of the variable capacitor section in response to a control voltage supplied in accordance with a digital control signal, and an additional variable capacitor section for varying its capacitance in response to an additional control voltage. The variable capacitor section includes first to Kth capacitors, where K is an integer greater than one. The adjusting section includes buffer section, each of which selectively generates one of a first voltage and a second voltage lower than the first voltage in response to a kth bit of the digital control signal, where k is an integer varying from one to K, thereby generating first to Kth control voltages to be supplied to the first to Kth capacitors.

Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Abstract: A non-linear time digitizer delay chain and a respective lookup table for converting the phase error into a digital code together prevent a phase error pulse from saturating the delay chain, even when the input frequency varies by orders of magnitude. By using a non-linear T2D delay chain along with a corresponding lookup table, the phase error pulse associated with a digital phase lock loop (PLL) can be measured and represented in more meaningful and accurate ways that that achievable when using a conventional T2d circuit to convert the phase error into a digital code. The lookup table implementation allows an additional degree of freedom for designers to apply a transfer function to the digital code measured by the T2D.

Abstract: A low-phase noise oscillator with a microstrip resonator for generating a target signal with a predetermined frequency is provided. The resonator includes a first microstrip line and a second microstrip line. The first microstrip line is parallel with the second microstrip line without having any contact. A length of the first microstrip line equals a length of the second microstrip line, and the length equals a quarter wavelength of the target signal. When a plurality of oscillating signals is transmitted to the first microstrip line, one of the oscillating signals having the predetermined frequency will be output from the resonator by an electromagnetic coupling generated between the first microstrip line and the second microstrip line.

Abstract: A digital phase-quadrature oscillator generates a series of sine values representative of a sine wave, and a series of cosine values representative of a cosine wave. In each iteration of the oscillator, a sum of the squares of past sine and cosine values is used as a negative feedback term in synthesizing next sine and cosine values, in order to stabilize the amplitudes of the sine and cosine values.

Abstract: An atomic frequency standard system includes two atomic standard devices, a comparison circuit and a correction circuit. The first device operates continuously, while the second device is operated only periodically. As the second device is only periodically operated, it experiences little frequency drift due to aging effects. When operated, the second device is stabilized, and then frequency compared to the first device by means of the comparison circuit. The correction circuit is then used to recalibrate frequency of the first device with the stabilized frequency of the second device.

Abstract: A clock signal generating device is described, having an oscillator and a PLL connected downstream thereof. The clock signal generating device is distinguished by the fact that a phase shifting device is provided between the oscillator and the PLL. This phase shifting device can temporally shift the edges of the signal output by the oscillator to a variable extent, and feeds the resultant signal to the PLL as an input signal. Such a clock signal generating device makes it possible to realize a spread spectrum oscillator which is constructed in a simple manner and can be made small.

Abstract: There is disclosed a voltage controlled oscillator (VCO) that receives +V(IN) and −V(IN) control voltages and outputs a VCO output signal having an oscillation frequency determined by the +V(IN) and −V(IN) control voltages. The VCO comprises: 1) a storage capacitor charged linearly by a constant charge current and too discharged linearly by a constant discharge current; 2) a comparator for comparing the storage capacitor voltage to an upper threshold voltage and a lower threshold voltage. The comparator output drops to a negative saturation voltage (−V(SAT)) when the storage capacitor voltage rises above the upper threshold voltage and rises to a positive saturation voltage (+V(SAT)) when the storage capacitor voltage drops below the lower threshold voltage.

Abstract: A fractional-N frequency synthesizer is disclosed wherein the multi-modulus frequency divider in the feedback path of the phase locked loop is controlled by a delta-sigma modulator to achieve the desired division ratio. The fractional input control signal to the delta sigma modulator is dithered to break any periodicity in the modulator output signal to avoid the generation of fractional spurious frequencies.

Abstract: A high-speed digitally voltage controlled oscillator with 1/N phase resolution, having a load counter, 1/N phase difference generator, a multiplexor, a clock selector, and a load controller. The high-speed digitally voltage controlled oscillator only needs a load counter with an input frequency D+1 (D is far smaller than N) times an output frequency thereof. The phases of first and (M/2+1)th phases of M clock signals with 1/N phase difference (M is far smaller than N) generated by the 1/N phase difference generator are fixed at 0° and 180° with respect to a reference clock. Therefore, only (M/2−1) clock signals are affected by variation of process parameters. Consequently, the high-speed digitally voltage controlled oscillator can tolerate variation error of process parameter and is applicable for high resolution and high frequency operation.

Abstract: Circuitry for controlling the oscillation frequency of an oscillator by using a digitally tunable on-chip capacitor bank. The capacitor bank includes a plurality of on-chip capacitors, each of which is independently selectable by a control signal for providing a selectable amount of capacitance to the oscillator to control the oscillator's oscillation frequency.