Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: a voltage tunable inductive-capacitive (LC) oscillator, a charge pump, and a phase detector. The oscillator, detector, and charge pump are coupled together to form a PLL.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a more general terms, a frequency synthesizer is disclosed having a first variable and a second capacitance circuits and frequency control circuitry to coarsely tune the output frequency by adjusting the first control signal and to finely tune the output frequency by adjusting the second control signal.

Abstract: A stabilised voltage controlled oscillator circuit comprises a closed loop circuit containing a voltage controlled oscillator (34), a local oscillator (40) and a harmonic mixer (38) that mixes a stabilised local oscillator (LO) frequency signal and a radio frequency (RF) signal from the voltage controlled oscillator (34) to obtain an intermediate frequency (IF) signal. An IF amplifier (42) is connected to a linear frequency discriminator (44) that provides an output signal to a summing amplifier (46), which is connected to the voltage controlled oscillator (34). The closed loop circuit uses the linear frequency discriminator (44) to provide a feedback signal that stabilises the voltage controlled oscillator (34).

Abstract: A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

Abstract: An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a support layer, a fixed layer positioned on a support layer, remaining portions of a sacrificial layer positioned only on portions of the fixed layer, and an oscillating layer positioned on the remaining portions of the sacrificial layer, overlying the fixed layer in spaced relation therefrom, and extending lengthwise generally transverse to a predetermined direction for defining a released beam for oscillating at a predetermined frequency. The spaced relation is preferably formed by removal of unwanted portions of the sacrificial layer.

Abstract: A thermal RC network is fabricated in silicon as a lateral array of forward-biased PN junctions, which may take the form of the base-emitter junctions of bipolar transistors. Application of a clock signal from a voltage controlled oscillator to the silicon produces a heat pulse which propagates across the arrayed transistors of the thermal RC network. The resulting change in temperature produces a change in the V.sub.be of the arrayed transistors. The phase shift between the original clock signal and the changed V.sub.be is determined solely by the time constant .tau. of the particular thermal RC network. This time constant is a function only of the intrinsic thermal resistance and thermal capacitance of the silicon and the spacing of the laterally-arrayed transistors. The time constant is independent of the amplitude, frequency, and duty cycle of the original clock signal. The original clock signal and the time-delayed output of the RC network can be compared, and the phase shift determined.

Abstract: An integrated circuit (IC) comprising an oscillator (OSC) has a first amplifier (AMP.sub.1) and a second amplifier (AMP.sub.2). The first and the second amplifier (AMP.sub.1, AMP.sub.2) each have a non-inverting input, an inverting input, and an output. The output of the first amplifier (AMP.sub.1) is connected to the non-inverting input of the first amplifier (AMP.sub.1) and also to the non-inverting input of the second amplifier (AMP.sub.2). The output of the second amplifier (AMP.sub.2) is connected to the inverting input of the first amplifier (AMP.sub.1) and also to the inverting input of the second amplifier (AMP.sub.2). The first amplifier (AMP.sub.1) is loaded with a capacitor (C) connected between the output of the first amplifier (AMP.sub.1) and an external power supply terminal (1). The second amplifier (AMP.sub.2) is loaded with a further capacitor (C.sub.F) connected between the output of the second amplifier (AMP.sub.2) and the external power supply terminal (1).

Abstract: A fully integratable voltage controlled oscillator (VCO) circuit includes a tuned circuit having a spiral inductance connected in parallel with a varactor controlled by a control voltage. Damping of the tuned circuit is counteracted by a cross-coupled NIC (Negative Impedance Converter). The cross-coupling of the NIC, which transforms a negative resistance into the tuned circuit, is provided by AC coupling of two outputs. Bipolar transistors are provided only for current source transistors, while in contrast CMOS transistors are provided in a current switch. The VCO can be used, for example, in DECT units.

Abstract: An improved oscillator test structure is disclosed. A structure according to one embodiment includes an odd plurality of first transistor pairs formed on a predetermined area of a semiconductor substrate. The transistor pairs are electrically connected in a serial ring. The structure also includes at least one second transistor pair, also formed within the predetermined area on the substrate, but electrically isolated from the odd plurality of first transistor pairs.

Abstract: A phase-locked loop fabricated on an integrated circuit includes a phase/frequency detector, a charge pump, a filter node and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second frequency control inputs and a VCO output, wherein the first frequency control input is coupled to the filter node and the VCO output is coupled to the phase/frequency detector. The VCO has a first voltage-to-frequency gain from the first frequency control input to the VCO output and a second voltage-to-frequency gain from the second frequency control input to the VCO output. An off-chip filter input is coupled to the filter node for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first frequency control input and the second frequency control input and has a variable time constant. A time constant control circuit is coupled to the on-chip loop filter for controlling the variable time constant.

Abstract: An integrated circuit complementary metal-oxide silicon (CMOS) voltage controlled oscillator (VCO) includes a plurality of variable delay elements, connected in a ring configuration, each variable delay element including a pair of parallel connected differential CMOS sections. The parallel-connected differential CMOS sections of each variable delay element are controlled by a differential control voltage whose magnitude sets relative levels of operation of the two differential sections of each variable delay element. These relative levels of operation determine the delay through the variable delay element. A current mirror circuit provides the differential control voltage.

Abstract: A small and economically fabricated CMOS voltage controlled crystal oscillator is provided by coupling three inverter amplifiers in series with a regenerative crystal controlled feedback loop. The first and second CMOS inverters have output nodes whose impedances are modified by a CMOS impedance modulating circuit. Also coupled to each of these two output nodes is a CMOS transistor shunt capacitor. The impedance of the output node is modified according to the magnitude of a voltage control signal applied to the CMOS modulating circuits. The self-bias of the modulating circuits is maintained substantially constant by adjusting the gate drive in each of the modulating circuits according to gate drives derived from a dummy modulating circuit.

Abstract: A voltage controlled oscillator includes a varactor (201) and a transistor (202) and a ground via (203), of epitaxially grown silicon that is etched to provide respective pedestals embodying the varactor (201) and the transistor (202) and the ground via (203), an L-C resonator circuit, the varactor (201) and an inductor providing a tank circuit that changes the frequency of the L-C resonator circuit, and that shifts the average frequency of the oscillator to that of an input voltage to the collector of the transistor (202).

Abstract: A clock generator or oscillator circuit for use in an integrated circuit for generating a clock signal includes a 555 timer circuit. The time constant circuit of the 555 timer includes a heater element for generating heat and a transducer for converting heat generated by the heater element into electrical energy. The clock signal is generated in response to the heating and cooling of the heater element.

Abstract: An integrated circuit having at least the following: a substrate; a composite inductor formed within the substrate having at least a first coil with an associated first coil inductance and first coil resistance and a second coil with an associated second coil inductance and second coil resistance, with the first coil formed proximate the second coil for magnetic flux linkage such that when a current in the first coil is matched with a current in the second coil, a new inductance associated with the first coil is produced that is in excess of the first coil inductance. An oscillator can be formed in the integrated circuit by connecting the first coil to at least one capacitor formed in the substrate.

Abstract: In a high current, high frequency integrated circuit chip characteristic of producing an excess of internal on-chip circuit induced noise with respect to a low current, low frequency circuit implemented on the high current, high frequency integrated circuit chip, a method is disclosed for reducing noise in the low current, low frequency circuit. The method includes placing noise sensitive components of the low current, low frequency circuit external to the integrated circuit chip, corresponding to an off-chip placement. An exclusive power supply reference line V.sub.(REF) tapped off of a power supply bus internal to the integrated circuit chip is provided. The exclusive power supply reference line V.sub.(REF) is tapped off the internal power supply bus on-chip at a physical location proximate the low current, low frequency circuit and routed off-chip. The noise sensitive components are connected between the low current, low frequency circuit and the power supply reference line V.sub.

Abstract: A VCO includes a transistor having a plurality of negative differential resistance devices coupled in series to the source terminal of the transistor, with each of the devices having a negative differential resistance operating region. Biasing circuits are coupled to the drain and gate terminals along with operating voltages which set the oscillator to operating in a negative differential resistance region of at least one of the negative differential resistance devices so that oscillations of a selected frequency are produced at an output terminal. The transistor, the plurality of N devices, the DC biasing circuits, and the operating voltages are connected so that the oscillator negative differential resistance operating region is greater than N times as wide as each of the device negative differential operating regions individually.

Abstract: The invention relates to an oscillator OSC intended to provide an output signal having a frequency which is variable as a function of a tuning voltage Vtun. The oscillator OSC includes a passive part having two series-arranged variable capacitances Cs, biased by the tuning voltage Vtun, and connected to a power supply VCC via two inductances Lext, and an active part having a first transistor T1 and a second transistor T2 whose collectors are connected to the output terminals C1 and C2 of the passive part, the base of one transistor being connected to the collector of the other transistor via a coupling capacitor Cfb. According to the invention, the passive part includes two high-pass filters, each being inserted between one of the output terminals S1 or S2 and one of the variable capacitances Cs, which allows a reduction of the active part's sensitivity to low-frequency noise.

Abstract: A method and system in an integrated circuit for frequency tuning oscillator circuits. An oscillator circuit within an integrated circuit is formed on a substrate such that the oscillator circuit is coupled to an inductor component. The inductor component includes a first inductor positioned parallel to a second inductor such that a total effective inductance is associated with the first and second inductors. The first inductor is formed from a first spiral coil layer which is coupled to a second spiral coil layer on the substrate. The second inductor is formed of a single spiral coil layer on the substrate, wherein the single spiral coil layer provides an inductive feedback signal to the oscillator circuit when electrical current flows through the single spiral coil layer in response to current flowing through the first spiral coil layer and the second spiral coil layer.

Abstract: The present invention provides a novel circuitry comprising a series connection of a plurality of invertor gates, each of which has field effect transistors, wherein at least one of the field effect transistors has a back bias control terminal; and a various bias voltage generator being capable of generating at least one bias voltage and also capable of varying the at least one bias voltage individually, the various bias voltage generator being also electrically connected to the back bias control terminal of the at least one of the field effect transistors for applying the at least one bias voltage to the back bias control terminal so that the various bias voltage generator is operated to individually vary the at least one bias voltage thereby to individually vary a threshold voltage of the at least one of the field effect transistors.

Abstract: An oscillator circuit, having an inverter with input and output terminals interconnected through a feedback resistance, operates in two modes. In a first mode, the input and output terminals are coupled to an external crystal resonator. In a second mode, an external clock signal is supplied to the input terminal. In the second mode, the input terminal is disconnected from the output terminal, and in addition, the output-drive capacity of the inverter is reduced, or the output terminal of the inverter is held at a fixed potential.

Abstract: In accordance with novel features of the present invention, a method and apparatus are provided for generating a oscillatory output signal having an oscillatory rate that is proportional to the magnitude of charge delivered through the input to the first charge well. The apparatus includes an input disposed to receive an input signal and an output disposed to output an oscillatory signal. A plurality of adjacently-disposed CCD charge wells are disposed between the input and the output. The plurality of CCD charge wells include a first charge well that is disposed in communication with the input and a last charge well is disposed in communication with the output. A charge sensor is disposed in proximity to the first charge well and operates to sense the magnitude of charge stored in the first charge well, and a driver is responsive to the sensor to drive an electrode disposed in proximity to a second charge well, which is disposed adjacent to the first charge well.

Abstract: In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit.

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: An electronic device (1) has a substrate (2) of monocrystalline silicon on which is an integrated circuit (3). The integrated circuit is an oscillator containing a resonator, a maintenance circuit to cause the vibration of the resonator, and a frequency division chain. The maintenance circuit as well as the division chain are manufactured as CMOS circuits. The resonator is an integrated resonator (4) formed of a body cut out in a delimited surface part of reduced thickness (14) of the substrate (2), of a thin layer of piezoelectric material (10) deposited on at least a part (6) of the body, and of a thin metallic layer (11) deposited on the piezoelectric layer (10) so as to form an electrode.

Abstract: An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

Abstract: An integrated oscillation circuit used for frequency conversion circuit in which UHF frequency conversion and VHF frequency conversion are selectively energized to use a common IF amplifier. The integrated oscillation circuit is used for a local oscillation circuit. The integrated oscillation circuit including a connection terminal connected to an external resonance circuit and an input line of a mode switching signal which is set at a different level in response to an operation mode, an oscillation element, a bias terminal of which is connected to the connection terminal, a detection circuit detecting the level of the mode switching signal applied to the bias terminal of the oscillation element, and a switching circuit turning on and off a power source for driving the oscillation element in response to the level detected at the detection circuit.

Abstract: An optically controlled oscillator utilizes a HEMT or a PIN diode as a photodetector and either a HEMT or HBT as an active inductor. The optically controlled HEMT active inductor provides a means for tuning the frequency of the oscillator. The optical receiver includes an optically tunable active inductor using a photodetector which includes a resonant tank circuit of an electronic oscillator to allow both optical/digital quench and unquench of an oscillator or digital AM detection with an improved signal to noise ratio, or optical FM modulation and analog AM detection by tuning/shifting the frequency of the oscillation through the detection of the optical light intensity.

Abstract: An improved ring oscillator in which frequency drift is controlled to provide reasonable accuracy is disclosed. The improved ring oscillator eliminates the frequency drift due processing variances. The ring oscillator provided by the invention incurs substantially less frequency drift than a conventional ring oscillator, but the frequency of the ring oscillator is still dependent on temperature and voltage changes. The improved ring oscillator according to the invention is particularly suited for operating as a localized oscillator that is used to facilitate periodic refreshing of DRAM within a computer.

Abstract: A ring oscillator circuit of one aspect includes a plurality of logic gates connected in cascade in a ring form and a plurality of signal lines each disposed between adjacent ones of the plurality of logic gates, and one of the signal lines is disposed in a spiral form in a pair together with another signal line. A ring oscillator circuit of another aspect includes a plurality of logic gates connected in cascade in a ring form and a plurality of signal lines whose wiring layout is made using wiring layers of a multi-layer structure and which are disposed between adjacent ones of the plurality of logic gates, and one of the signal lines is disposed spirally in such a manner as to be close to itself at portions thereof in at least two of the wiring layers of a multi-layer structure. When such a layout of the signal lines is employed, the difference between the frequency of the pulses actually output and the frequency of the output pulses based on simulation can be reduced to minimum.

Abstract: A voltage controlled ring oscillator (10) integrated with a phase locked loop (101) using CMOS technology. The ring oscillator (10) provides a frequency multiplied harmonic output frequency (42) at a frequency of 2.5 GHz or more while operating at only one-third of that frequency. The ring oscillator (10) uses an odd number of inverter stages (12, 14, 16) and provides high frequency CMOS operation by utilizing the phase shifted signals of the ring frequency at each ring inverter output (20, 24, 28). The ring oscillator (10) draws minimal current and is incorporated in a frequency synthesizer (100) used in a radio communication device (200).

Abstract: A digital temperature compensated crystal oscillator (10) with pin multiplex control which includes: four analog I/O pins, a signal multiplex method which allows switchable digital communication via at least two of the analog I/O pins (20,28), and an external mode selector (12) which operates through the power leads. Changes in the power voltage level selects the TCXO (10) to operate in a normal or communication operating mode. In the normal operating mode the TCXO operates in a normal analog manner. In the communication mode, the analog functions of the I/O pins (20,28) are switched out and digital functions are allowed on the same I/O pins (20,28). The use of the same I/O pins (20,28) for switchable analog and digital signals saves size and cost, and prevents the inadvertent access to the digital functions of the TCXO (10) by customers in the field.

Abstract: A resonance inductor of a resonant circuit is formed of a chip inductor and an inductance fine adjustment pattern. A resonance capacitor is formed of a plurality of chip layered capacitors connected in parallel to each other via connection patterns formed on a substrate. The connection patterns are sequentially disconnected to adjust the capacitance of the resonance capacitor. Then, the inductance fine adjustment pattern is partially removed to adjust the inductance of the resonance inductor.

Abstract: An astable multivibrator comprising a capacitor connected between a first output signal and a third output signal, an amplification circuit connected between the first and third output signals, a delay for delaying a signal logic-converted from the first output signal and for outputting a second output signal, and a variable resistor connected between the first output signal and an output node of the delay. High frequency oscillation performance is enhanced and a larger voltage operating range is obtained by excluding the effect of feedback current.

Abstract: A dual voltage controlled oscillator including a transistor with a negative differential resistance diode coupled to a first terminal and an inductance coupled to a second terminal. Operating voltages are applied to the gate and drain of the transistor to set the oscillator to operating in a negative differential resistance region of the diode. The diode, the inductance and the operating voltages are connected so that varying either of the operating voltages varies the frequency of the oscillations at the output.

Abstract: An electromagnetic wave generator for influencing different corporal states in a biological organism includes an oscillator circuit coupled to a microcontroller and an antenna coupled to the microcontroller through which waves at a given frequency are transmitted to a biological organism.

Abstract: A semiconductor IC used for synthesizer having a phase locked loop PLL, a voltage controlled oscillator (VCO) and a mixer (MIX) for intermediate frequency is formed on a one chip silicon wafer. A semiconductor IC used for synthesizer having a VCO portion and an internal circuit such as PLL on a silicon wafer chip includes a differential buffer circuit which separates the VCO portion from the internal circuit. A capacitor (C1) is connected to an output of the VCO portion. A constant voltage source (V1) may be connected to respective input of the differential transistors (Q4, Q5). Transistors (Q6,Q7) provide emitter follower output circuits in the differential buffer. Respective emitters of the transistors (Q6,Q7) are connected to corresponding constant current sources (I1,I2).

Abstract: A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock generator allows for electrical configuration of various information including PLL parameters, input thresholds, output drive levels and output frequencies. The various parameters can be configured after the clock generator is fabricated. The parameters can be configured either during wafer sort or after packaging. The clock generator can be erased prior to packaging so programming can be verified.

Abstract: A millimeter or microwave oscillator device for a receiver or a transmitter is described. The oscillator device including a high frequency oscillating circuit including an active device 41; said active device 41 having a first and a second contact 56, 52, a signal line 49 of said oscillator device 41 being connected to said first contact 56 for connection to a load circuit 43; a biasing circuit 47 for said active device; and a low frequency oscillation suppression circuit; wherein said low frequency oscillation suppression circuit includes a decoupling capacitor 45 and one electrode of said decoupling capacitor 45 is connected to said second contact 52. A manufacturing method for the oscillator device is also disclosed.

Abstract: Micro-scale and nano-scale devices which achieve high frequency signals ug materials having increased electron saturation velocity. These devices have frequencies in the terahertz range with high temperature and radiation hard characteristics. The transit time device includes a substrate, a buffer layer and an epitaxial layer made of a material in the 43 m and 6 mm crystallographic point groups and associated alloys, and at least two contacts on the device. In operation, one contact is forward biased and the other is reversed biased. Applications for this devices include transit-time-based oscillators for use in military and civilian radar receivers, logic devices, burglar alarm and proximity alarm systems.

Abstract: A monolithically integrated oscillator is implemented as ring oscillator with a line driver and a double line formed on one and the same chip. A running time of the double line is selected optimally long and a delay time of the line driver is selected optimally short. The double line can be loaded with controllable capacitors.

Abstract: In a semiconductor device having a CR oscillation circuit and a reset circuit, the semiconductor device includes a common terminal for constituting the CR oscillation circuit and the reset circuit. A voltage level at which the device falls into a reset state is lower than a low level voltage of an oscillation waveform and the device does not falls into the reset state during oscillation. As a result, the number of terminals of the device can be decreased to permit a larger number of functions to be included in a package having an equal number of pins, and the number of components externally equipped can be decreased to reduce expense of the components and management therefor.

Abstract: An automatic gain control circuit and method ensure feedback for oscillator circuitry fabricated on a single semiconductor chip to adapt to the Q value established by a resonator circuit connected to the oscillator circuitry, and to ensure that gain is maximized and linearity of operation preserved within the voltage rails of the power supply.

Abstract: A one pin on-chip crystal oscillator circuit and a method of operating that oscillator are provided. The oscillator makes use of the gate-source capacitance of a MOS transistor to provide capacitance which would otherwise need to be provided by one of two oscillator capacitors. The MOS transistor is provided with a floating well by coupling its body to its source, so that the gate-source capacitance does not change substantially when the transistor is turned off. In another aspect of the invention, the MOS transistor is provided with a floating well using a parallel combination of MOS transistor elements, so as to minimize the coupling resistance of the MOS transistor to other elements of the circuit.

Abstract: An on-chip voltage controlled oscillator for use in an analog phase locked loop receives power from a voltage regulator which greatly reduces the noise seen by the voltage controlled oscillator. The voltage controlled oscillator has a DC bias section which supplies a relatively constant current to the multivibrator to assure a minimum operating frequency. A control signal is used to provide additional current which increases the speed of oscillation. The bias current reduces the transfer characteristics (MHz/volt) of the voltage controlled oscillator making it more immune to noise in the control signal.

Abstract: A communication system providing read and write access to analog and digitally controlled calibration and configuration information contained within prepackaged crystal oscillators having a crystal oscillator electrical interface with power (VCC), ground (GND), output enable (OE), and oscillator output (XO) interface pins. An output enable (OE) signal is used to control the activity state of the crystal oscillator output, with a pullup MOSFET connected to the XO pin to detect a logic low level at the XO pin during times when the OE signal is logically inactive. A state machine controls access to a serial shift register having multiple calibration and configuration bits. The calibration and configuration bits are used in performing an oscillator specific calibration and configuration function. The state machine also controls the reads and writes of the calibration and configuration shift register.

Abstract: An oscillation circuit in which the driving performance of a CMOS transistor therein for enabling/disabling an oscillating function is enhanced without unstabilizing the oscillation operation, by applying a higher potential to the back gate of the CMOS transistor when a signal other than an oscillation signal is inputted/outputted, and a lower potential when generating the oscillation signal.

Abstract: An integrated oscillation circuit used for frequency conversion circuit in which UHF frequency conversion and VHF frequency conversion are selectively energized to use a common IF amplifier. The integrated oscillation circuit is used for a local oscillation circuit. The integrated oscillation circuit including a connection terminal connected to an external resonance circuit and an input line of a mode switching signal which is set at a different level in response to an operation mode, an oscillation element, a bias terminal of which is connected to the connection terminal, a detection circuit detecting the level of the mode switching signal applied to the bias terminal of the oscillation element, and a switching circuit turning on and off a power source for driving the oscillation element in response to the level detected at the detection circuit.

Abstract: An oscillator circuit (150) is designed with a reference circuit (102), responsive to a first voltage, for producing a second voltage. An oscillator (108), responsive to the second voltage, produces a first output signal having a magnitude less than a magnitude of the first voltage. A level translator (114), responsive to the first output signal, produces a second output signal having a magnitude greater than the magnitude of the first output signal. Since the oscillator produces the first output signal with a magnitude less than the magnitude of the first voltage, power consumption is reduced with respect to an oscillator operating at the first voltage. The magnitude of the first output signal is increased by the level translator to a desired magnitude of the second output signal.

Abstract: An oscillator circuit having an amplifier and feedback loop multiplies a generated signal by appropriate selection of capacitance ratios in the feedback loop. In order to isolate this multiplied, high voltage signal, a voltage divider is used to isolate the high voltage portion from the input and output (I/O) of an integrated circuit oscillator core. The multiplied voltage creates a high voltage signal suitable for stylus signal transmission. The divided, and relatively low, voltage is used in the feedback path to stabilize the oscillator core's operation.