With Crystal Substitution Patents (Class 331/161)
  • Patent number: 10750452
    Abstract: A system includes a frequency-locked loop (FLL) circuit, a sensor-hub circuit and a processor. The FLL circuit is used to generate a low-frequency clock. The sensor-hub circuit is coupled to a number of sensors and is configured to periodically poll the sensors during polling periods and to detect sensor activities. The processor is coupled to the sensor-hub circuit and can process sensor signals from one or more active sensors. The processor is off during polling periods and is turned on when a sensor activity is detected. The polling periods are based on the low-frequency clock generated by the FLL circuit.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 18, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Avinash Agarwal, Mohit Sharma
  • Patent number: 10256801
    Abstract: An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 9, 2019
    Assignee: M31 Technology Corporation
    Inventors: Chih-Cheng Hsu, Yuan-Hsun Chang, Chang-Huan Liang
  • Patent number: 9509324
    Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 29, 2016
    Assignee: Silego Technology, Inc.
    Inventors: John Othniel McDonald, Crist Y. Lu, Ilbok Lee
  • Patent number: 9291600
    Abstract: A sensor for detecting analytes, a method of making the sensor, and a method of using the sensor. In one embodiment, the present invention comprises at least one array comprising a plurality of resonators. The resonators can be arranged in a plurality of rows and a plurality of columns, and can be connected in a combined series-parallel configuration. The resonators can be adapted to vibrate independently at about the same resonance frequency and about the same phase. The sensor can also comprise an actuator and a signal detector electrically coupled to the array. The sensor can also further comprise an analyte delivery system and can be functionalized for detection of at least one analyte.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 22, 2016
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Igor Bargatin, John Sequoyah Aldridge, Edward Myers, Michael L. Roukes
  • Patent number: 8653901
    Abstract: An oscillator and a control circuit thereof are provided. The control circuit is configured to control an oscillator to adjust the amplitude and the level of an oscillation signal. The control circuit includes a peak amplitude detector, an average voltage detector, and an oscillation controller. The peak amplitude detector is configured to detect the amplitude of the oscillation signal, so as to generate an amplitude value. The average voltage detector is configured to detect the direct current (DC) level of the oscillation signal, so as to generate an average value. The oscillation controller is configured to generate two power signals according to the amplitude value and the average value. The two power signals are provided to the oscillator, so that the oscillator adjusts the amplitude and DC level of the oscillation signal.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 18, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jia-Shian Tsai, Kuo-Tai Chang
  • Patent number: 8564378
    Abstract: A voltage-controlled oscillating circuit includes a differential amplifying circuit connected to a resonant element such as a quartz crystal element. The differential amplifying circuit includes first and second input terminals connected to the resonant element and also connected respectively to first and second voltage-controlled capacitors. The differential output terminals of the differential amplifying circuit are connected respectively to first and second emitter follower circuits. The output signal of the first emitter follower circuit is fed back to the second input terminal through a third capacitor and a third voltage-controlled capacitor, and the output signal of the second emitter follower circuit is fed back to the second input terminal through a fourth capacitor and a fourth voltage-controlled capacitor. A control voltage is applied to each of the voltage-controlled capacitors.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: October 22, 2013
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Yutaka Takahashi
  • Patent number: 8532590
    Abstract: A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: September 10, 2013
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thomas Mayer, Nick Shute
  • Patent number: 8049569
    Abstract: A clock generation circuit is provided for improving the accuracy of a low power oscillator circuit contained therein. The clock generation circuit includes a crystal-less oscillator having at least two distinct frequency modes, including a low frequency mode and a high frequency mode. In some cases, the crystal-less oscillator may be adapted to generate a first clock frequency with relatively high accuracy and a second clock frequency with relatively low accuracy. A calibration and control circuit is included within the clock generation circuit for increasing the accuracy of the second clock frequency. In particular, the calibration and control circuit increases accuracy by using the first clock frequency to calibrate the second clock frequency generated by the same crystal-less oscillator. A system comprising the clock generation circuit and methods for operating a crystal-less oscillator having at least two distinct frequency modes are also provided herein.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: November 1, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: David G. Wright, Timothy J. Williams
  • Patent number: 8045937
    Abstract: A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Infineon Technologies AG
    Inventors: Thomas Mayer, Nick Shute
  • Patent number: 7215208
    Abstract: Embodiments of the present invention include a frequency generator comprising a feedback loop with a transmission line integrated on a single integrated circuit. In one embodiment, a frequency generator comprises a phase detector and a voltage controlled oscillator coupled in series, and a transmission line having an input coupled to an output of the voltage controlled oscillator, the transmission line providing a time delay between the transmission line input and output, wherein the phase detector includes an input coupled to the transmission line output and another input coupled to the transmission line input. The phase detector, voltage controlled oscillator and transmission line are advantageously integrated on a single integrated circuit.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: May 8, 2007
    Inventor: Paul William Ronald Self
  • Patent number: 6946923
    Abstract: A structure and associated method to allow an oscillator circuit to operate with a plurality of different crystals. The oscillator circuit comprises a semiconductor device and a crystal. The semiconductor device comprises a primary inverting amplifier and a crystal substitution damping resistor. The crystal is electrically coupled to the primary inverting amplifier. A resistance value of the crystal substitution resistor is adapted to vary in order to control an amount of current flow from the primary inverting amplifier to the crystal. The amount of the current flow to the crystal is dependent upon an electrical property of the crystal.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: September 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jerry P. Knickerbocker, Jr., Vishwanath A. Patil, Stephen D. Wyatt
  • Patent number: 6759980
    Abstract: This invention provides a phased array antenna comprising an input, a feed network electronically coupled to the input, a plurality of radiating elements, a plurality of continuously voltage tunable phase shifters for receiving signals from the feed network and providing phase shifts for the signals prior to transmitting the signals to the radiating elements, and a controller for controlling the phase shift provided by the phase shifters. The phased array antennas can be configured to produce beams that can be scanned in one dimension (one-dimensional) or two dimensions (two-dimensional) by using continuously adjustable phase shifters that are based on low cost, low loss voltage-tunable dielectric materials.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: July 6, 2004
    Assignee: Paratek Microwave, Inc.
    Inventors: Shuguang Chen, Daniel F. DiFonzo, Ernest P. Ekelman
  • Patent number: 6480073
    Abstract: A method of evaluating quality of a crystal unit, capable of performing quantitative measurement of an actual operation of a crystal unit which is to be oscillated in an actual oscillator to ensure an accurate quality evaluation, is provided. The method includes increasing a DC input voltage of a crystal oscillator, the crystal oscillator having at least one AGC amplifier whose amplification rate varies depending on the DC input voltage and having a crystal unit connected thereto, measuring a maximum value of the DC input voltage at a start of oscillation of the crystal oscillator, and evaluating quality of the crystal unit by the measured maximum value.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: November 12, 2002
    Assignee: Suwadenshi Co., Ltd.
    Inventor: Hajime Ushiyama
  • Patent number: 5959505
    Abstract: A crystal oscillator for measuring crystal impedance (CI) easily and accurately of various crystal units having an oscillating frequency in a wide band and various CI-values in a broad rage. A DC input voltage is measured, representing CI of a crystal unit, in a crystal oscillator, wherein an integrating circuit is provided in an output section providing a frequency oscillated from the crystal unit as an output, and one or more AGC amplifiers having an amplification rate proportional to a DC input voltage is provided between the crystal unit and the integrating circuit.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: September 28, 1999
    Assignee: Suwadenshi Co., Ltd.
    Inventor: Hajime Ushiyama
  • Patent number: 5696469
    Abstract: A clock oscillator having a pair of pins adapted for coupling to an external crystal, a first one of such pair of pins being adapted for coupling to an external clock. A switch, formed on the chip, is provided for electrically decoupling the crystal excitation circuit from one of the pair of pins in response to a control signal. In accordance with one embodiment of the invention, the switch is disposed between the output of a crystal excitation circuit and the second one of the pair of output pins and, in another embodiment, the switch is placed in circuit between the input to the crystal excitation circuit and the first one of the pair of pins. In each of these embodiments, when the switch is in a first condition, clock pulses are prevented from being coupled to the second one of the output pins, either: by preventing the external clock from feeding the input to the crystal excitation circuit; or, by preventing the output of the crystal excitation circuit from feeding the second one of the pair of pins.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: December 9, 1997
    Assignee: Analog Devices, Inc.
    Inventors: Thomas J. Meany, Patrick R. Hickey
  • Patent number: 5646580
    Abstract: A multi-crystal controlled oscillator (10) and method includes a first crystal resonator (11), second crystal resonator (14), oscillator circuit (23), and a switch (29). The switch (29) is coupled between the first crystal resonator (11) and the oscillator circuit (23) and between the second crystal resonator (14) and the oscillator circuit (23), and electrically couples either the first (11) or the second crystal resonator (14) to the oscillator circuit (23) in response to a crystal select input (XTAL SELECT).
    Type: Grant
    Filed: March 4, 1996
    Date of Patent: July 8, 1997
    Assignee: Motorola, Inc.
    Inventor: Geoffrey W. Perkins
  • Patent number: 5142251
    Abstract: A CMOS oscillator integrated circuit in a Pierce crystal oscillator circuit configuration operates at oscillating frequencies over a wide band frequency range. A single inverter stage (I1) is coupled between the oscillator input (OSC IN) and the oscillator output (OSC OUT). An oscillator feedback circuit coupled between the oscillator output and oscillator input incorporates an oscillator crystal (XTAL). A pullup gain network (PNET) provides a plurality of different parallel pullup gain paths between the pullup transistor (P1) of the inverter stage (I1) and the high potential power rail (V.sub.CC). The pullup gain paths have different pullup gain resistances (RP2, RP3, . . . RPN) in the respective pullup gain paths for implementing different amplifying gains (A.sub.N) by the inverter stage (I1). Digitally addressable pullup gain switches (P2, P3, . . . PN) are coupled in respective pullup gain paths for selecting different gain paths and different amplifying gains (A.sub.N).
    Type: Grant
    Filed: October 3, 1991
    Date of Patent: August 25, 1992
    Assignee: National Semiconductor Corporation
    Inventor: James B. Boomer
  • Patent number: 4574255
    Abstract: Between insulative layers (31-37, 41-44), a multilayer substrate comprises at least one dielectric layer (26-29). It is possible to form capacitors (58), resistors (46), and wiring conductors (61, 62) in the substrate. The at least one dielectric layer should be of at least one dielectric composition which has a perovskite structure. Preferably, each insulative layer is of an insulating material which consists essentially of aluminum oxide and lead borosilicate glass. The substrate is convenient in manufacturing a crystal oscillator by mounting a crystal vibrator (71) and a transistor (72) on the principal surface(s). Examples of the dielectric composition are:Pb[(Fe.sub.2/3.W.sub.1/3).sub.0.33 (Fe.sub.1/2.Nb.sub.1/2).sub.0.67 ]O.sub.3,Pb[(Mn.sub.1/3.Nb.sub.2/3).sub.0.01 (Mg.sub.1/2.W.sub.1/2).sub.0.30 (Ni.sub.1/3.Nb.sub.2/3).sub.0.49 Ti.sub.0.20 ]O.sub.3,andPb[(Mg.sub.1/2.W.sub.1/2).sub.0.66 Ti.sub.0.34 ]O.sub.3.
    Type: Grant
    Filed: December 15, 1983
    Date of Patent: March 4, 1986
    Assignee: NEC Corporation
    Inventors: Shuzo Fujii, Yuzo Shimada, Kazuaki Utsumi, Yutaka Saito
  • Patent number: 4547748
    Abstract: A frequency synthesizer is provided that is capable of supplying a plurality of accurate frequencies. The frequency synthesizer comprises a resonator matrix including a plurality of resonators embedded in a single monolithic piece of piezoelectric crystal. The resonators are arranged in rectangular row and column configuration including m rows and n columns. Each of the resonators is separated from its neighboring resonators by distances such that the resonant energies do not overlap. Each of the rows of resonators bears a metallic electrode stripe for that row and each of the columns of resonators bears a metallic electrode stripe for that column, the electrodes row stripes being positioned on the top surface of the crystal and the electrode column stripes being positioned on the bottom surface of the crystal. The areas of overlap of the row and column stripes are registered with the central portions of the embedded resonators.
    Type: Grant
    Filed: August 13, 1984
    Date of Patent: October 15, 1985
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Arthur Ballato
  • Patent number: 4510464
    Abstract: A self-oscillating vibrator exciting circuit utilizing a drive transistor that operates in a switching mode. The ON-period of the transistor is determined by base/emitter inductance and capacitance and base/collector capacitance, while the OFF-period of the transistor is determined by collector/emitter inductance and capacitance. The vibrator is connected between transistor collector and emitter, and the ON-period frequency of the transistor is set in the neighborhood of the resonance frequency of the vibrator so that the vibrator exciting circuit oscillates generally at the resonance frequency of the vibrator.
    Type: Grant
    Filed: September 29, 1982
    Date of Patent: April 9, 1985
    Assignee: TDK Corporation
    Inventor: Minoru Takahashi
  • Patent number: 4442415
    Abstract: A single Colpitts-type oscillator has a plurality (here, three) of optional inputs, each having a separate oscillating circuit individually associated therewith. By suitably applying a potential to a selected one of the oscillating circuits, the oscillator may be made to produce one of a plurality of predetermined carrier wave frequencies. The inventive circuit configuration eliminates large volume components such as coupling capacitors and enables hybrid IC construction, which miniaturizes the circuit. The circuit is particularly useful in walkie-talkie FM transceivers.
    Type: Grant
    Filed: July 14, 1980
    Date of Patent: April 10, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Shigeaki Ashida