Particular Error Voltage Control (e.g., Intergrating Network) Patents (Class 331/17)
  • Patent number: 9748932
    Abstract: A phase locked loop includes a signal receiver configured to generate a mixed signal based on the received signal and an oscillator signal, and a frequency control circuit configured to compare the mixed signal to a reference signal, and adjust the oscillator signal based on a result of the comparing.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 29, 2017
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Jaesup Lee, Sang-Gug Lee, Jae-Seung Lee, Seok-Kyun Han
  • Patent number: 9735790
    Abstract: A radio communication device has an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal including the reception signal, an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, and a setting code adjuster to adjust the frequency setting code signal, wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: August 15, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihide Sai, Hidenori Okuni, Masanori Furuta
  • Patent number: 9735788
    Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ja Yol Lee, Minjae Lee, Cheon Soo Kim, Jaehyun Kang, Junsoo Ko
  • Patent number: 9722616
    Abstract: A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takayuki Shibasaki
  • Patent number: 9712317
    Abstract: In some aspects, the disclosure is directed to methods and systems for carrier synchronization in active load modulation for near field communications. A broadcast carrier is received from a remote device and mixed with a locally-generated carrier and modulated data. A carrier synchronization circuit synchronizes the locally-generated carrier with the broadcast carrier based on an identified phase error from a double Cartesian-to-polar mapping of the mixed locally-generated carrier and broadcast carrier. In some implementations, the system also includes a modulation suppression circuit for providing unmodulated carrier signals to the carrier synchronization circuit or suppressing modulation distortion to maintain frequency and phase tracking despite the presence of data.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 18, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Manolis Frantzeskakis, Dong-U Lee, Divyanshu Jain, Jianhua Gan, Shengyang Xu
  • Patent number: 9679885
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 13, 2017
    Assignee: Volterra Semiconductor Corporation
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9680479
    Abstract: An electronic apparatus includes a voltage-controlled oscillator and a biasing circuit. The voltage-controlled oscillator includes varactors. The voltage-controlled oscillator is configured to output an oscillating frequency at a first temperature. The biasing circuit electrically coupled with the varactors is configured to provide a first biasing voltage to the varactors at the first temperature, and provide a second biasing voltage to the varactors at a second temperature, in which the varactors have a first temperature coefficient, and the biasing circuit generates the first biasing voltage and the second biasing voltage according to values of the first temperature coefficient and a second temperature coefficient.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 13, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Che-Wei Chang
  • Patent number: 9628262
    Abstract: An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Marius Moe
  • Patent number: 9606645
    Abstract: A display apparatus is provided. The display device includes pixels, a data line, a first current compensation unit, a second current compensation unit, and a control unit. The first current compensation unit is configured for providing a first current to pixels through the data line. The first current is configured for compensating a leakage current that flows out of the data line. The second current compensation unit is configured for sinking a second current from pixels through the data line. The second current is configured for compensating the leakage current that flows into the data line. The control unit is configured for controlling the first current compensation unit to provide the first current or controlling the second current compensation unit to sink the second current according to a voltage of the data line.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: March 28, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chun-Chieh Lin, Hua-Gang Chang, Chih-Cheng Chen
  • Patent number: 9590643
    Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John W. Stanton, Pradeep Thiagarajan
  • Patent number: 9565042
    Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 7, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Kuang-Wei Cheng, Wen-Hao Ho, Sheng-Kai Chang
  • Patent number: 9509289
    Abstract: An oscillation circuit includes a ring oscillator and a current generating circuit. The ring oscillator includes a control terminal. The current generating circuit generates a current according to a voltage of the control terminal in the ring oscillator, and supplies the current to the control terminal. The ring oscillator includes a plurality of delay stages connected to each other in a ring shape. Each of the delay stages includes an inverter and a capacitance element. The inverter includes a power source side node, an input node, and an output node. The power source side node is connected to the control terminal. The capacitance element is connected as a load for the inverter. The capacitance value of the capacitance element is larger than a parasitic capacitance at the output node.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: November 29, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Kobayashi
  • Patent number: 9503107
    Abstract: The disclosure is directed to compensating for frequency drift in a voltage-controlled oscillator (VCO). Example methods and systems are described which may detect a signal edge associated with a transceiver, and determine whether one or more lock quality signals indicate that the VCO frequency is outside of an specified range, indicating an unacceptable amount of frequency drift. A frequency tuning setting of the VCO may be adjusted based on the one or more lock quality signals, and a determination may be made whether or not the one or more lock quality signals indicate that the VCO frequency has returned to the specified range. The adjustment of the frequency tuning setting of the VCO may be repeated until the VCO frequency returns to the specified range.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: November 22, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Young Gon Kim, Burcin Baytekin, Yido Koo, Emilia Vailun Lei, Jeongsik Yang, Yongwang Ding
  • Patent number: 9484939
    Abstract: Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: November 1, 2016
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kexin Luo, Kai Zhou, Shengguo Cao, Lingfen Yue, Fangquing Chu, Yu Shen, Zhi Wu
  • Patent number: 9470726
    Abstract: Systems and methods of a temperature compensated real-time clock are disclosed. The systems and methods can include measuring a temperature with a temperature sensor, detecting a temperature dependent frequency from an oscillator, inputting the temperature and determining a temperature estimate for the oscillator with an infinite impulse response filter, and determining a compensation factor, for the oscillator.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 18, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Nathan Theodore Hackett
  • Patent number: 9473153
    Abstract: An oscillation circuit, an oscillator, an electronic device and a moving object, having at least a serial interface and an output enabling function, which are capable of implementing the control of output enabling without performing exclusive switching control using a switch, are provided. The oscillation circuit generates an oscillation signal by oscillating an oscillation element, and includes a first terminal to which characteristic control data for controlling characteristics of the oscillation signal including at least a frequency is input and to which control data of a first output control signal for controlling an output of the oscillation signal is input.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 18, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Yuichi Toriumi
  • Patent number: 9466353
    Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 9413365
    Abstract: Apparatuses are disclosed which comprise a coarse tuning circuitry, a fine tuning circuitry and at least one switchable capacitance.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: August 9, 2016
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Thomas Mayer, Andreas Roithmeier
  • Patent number: 9407424
    Abstract: A clock and data recovery module (CDR) is configured to perform fast locking using only two samples per each unit interval (UI). Two clock phase signals are selected from a plurality of clock phase signals. A sequence of data bits is sampled at a rate of two times per UI responsive to the two clock phase signals in which a first sample of each UI is designated as an edge sample a second sample is designated as a data sample. Each edge sample is voted as early/late as compared to an associated data transition of the sequence of data bits by comparing each edge sample to a next data sample. The sample clocks are locked such that edge samples occur in proximity to data transitions by iteratively adjusting a phase of the two selected clock phase signals by a variable step size in response to the early/late vote.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: August 2, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bharathi Rahuldev Holla, Jagdish Chand Goyal, Biman Chattopadhyay, Sujoy Chakravarty, Sumantra Seth
  • Patent number: 9395745
    Abstract: Aspects of this disclosure relate to reference switchover. In one embodiment, an apparatus includes a phase error detector, a phase alignment detector, and a selection circuit. The phase error detector is configured to generate an indication of a relative phase difference between a first reference clock signal and a second reference clock signal. The phase alignment detector is configured to receive the indication of the relative phase difference and determine when the relative phase difference satisfies a preset threshold. The selection circuit is configured to transition from providing the first reference clock signal as a clock system reference signal to providing the second reference clock signal as the clock system reference signal responsive to the phase alignment detector detecting that the relative phase difference satisfies the preset threshold.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Analog Devices, Inc.
    Inventors: Dan Zhu, Reuben Pascal Nelson, Yi Wang
  • Patent number: 9344271
    Abstract: A hybrid analog-digital, dual path, delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) that includes an integral path and a proportional path is provided. The integral path is implemented in the digital domain. The proportional path may be implemented in either the digital or analog domain. A feed-forward error correction signal generator is used to generate a feed-forward signal for attenuating in-band spurs generated by the quantization error of the integral path phase detector.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: May 17, 2016
    Assignee: MICROSEMI STORAGE SOLUTIONS (U.S.), INC.
    Inventor: Tomas A. Dusatko
  • Patent number: 9325331
    Abstract: Methods and systems for phase correction include determining a phase error direction and generating a prediction for the phase error based on a sigma-delta error. It is determined whether the prediction agrees with the determined phase error direction. If the prediction does not agree, a phase correction is adjusted in accordance with the predicted phase error.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: April 26, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Herschel A. Ainspan, Mark Ferriss, Daniel J. Friedman, Alexander V. Rylyakov, Bodhisatwa Sadhu, Alberto Valdes Garcia
  • Patent number: 9287886
    Abstract: Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 15, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Steven C. Ciccarelli, Frederic Bossu, Vladimir Aparin, Kevin H. Wang
  • Patent number: 9257998
    Abstract: A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: February 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Tsung-Hsien Tsai
  • Patent number: 9252788
    Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: February 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: John W. Stanton, Pradeep Thiagarajan
  • Patent number: 9197226
    Abstract: According to one example, a digital phase detector is disclosed for use with a phase lock loop. The digital phase detector is configured to operate in a low-frequency environment and to filter noise and transients in a signal, while also being tolerant of dropped phase pulses. In some embodiments, the digital phase detector is configured to measure up to two REFCLK edges with respect to a FBCLK signal, and if an edge occurs in the first half of REFCLK, classify the edge as lagging, and if an edge occurs in the second half of REFCLK, classify the edge as leading. If both edges are leading or both are lagging, the smaller of the two is used as the phase. If one is leading and one is lagging, the difference is used as the phase.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Lewis F. Lahr
  • Patent number: 9163954
    Abstract: Circuitry is described for compensating leakage currents in capacitive sensing circuits. A single active leakage compensation circuit may sense a representative leakage current and drive a plurality of output transistors, each of which provides a compensating current to a respective capacitive sensing circuit. The leakage compensation circuit may sense current flow through a device substantially equivalent to a device exhibiting leakage current in a capacitive sensing circuit, and in response, provide a signal to drive one or more output transistors to supply approximately equivalent currents to a plurality of circuit nodes. For embodiments having multiple similar capacitive sensors and capacitive sensing circuits, only one transistor need be added to each capacitive sensing circuit to compensate for leakage current.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: October 20, 2015
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventors: Chee Weng Cheong, Yannick Guedon
  • Patent number: 9130623
    Abstract: User equipment includes a convertor that converts transmission target frequency domain signal into time domain signal; a quadrature modulator that applies quadrature modulation to the time domain signal; a cancellation signal generator that generates image leakage cancellation signal by converting image signal into time domain signal, and applying the quadrature modulation, wherein the image signal has a frequency component that is symmetrical to the transmission target signal with respect to center of transmission frequency range; an adjuster that monitors the frequency component of the image signal in output signal from the quadrature modulator, and that adjusts amplitude and a phase of image leakage cancellation signal so as to cancel the frequency component; and a combiner that combines output signal from the quadrature modulator with image leakage cancellation signal, and that provides a power amplifier with combined signal.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 8, 2015
    Assignee: NTT DOCOMO, INC.
    Inventors: Hidetoshi Suzuki, Hiromasa Umeda, Takashi Okada
  • Patent number: 9106128
    Abstract: Provided is a charge pump circuit having a current mirror structure, including a first voltage controller including a plurality of first resistors and a plurality of first switches, and in response to a switching control signal corresponding to a bias current, driving the plurality of first switches to allow a current path passing through the plurality of first resistors to bypass, thereby controlling a voltage level of an output end, a second voltage controller including a plurality of second resistors and a plurality of second switches, and in response to the switching control signal, driving the plurality of second switches to allow a current path passing through the plurality of second resistors to bypass, thereby controlling a voltage level of an output end to correspond to the voltage of the output end of the first voltage controller.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: August 11, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hui Dong Lee, Jae Ho Jung, Kwangchun Lee
  • Patent number: 9092729
    Abstract: Systems and methods for controlling frequency output of an electronic oscillator to compensate for effects of one or more parameters experienced by the oscillator incorporate artificial neural network processing functionality for generating correction signals. A neural network processing module includes one or more neurons which receive one or more inputs corresponding to parameters of an electronic oscillator, such as temperature and control voltage (or correction voltage). One or more sets of weights are calculated and applied to inputs to the neurons of the neural network as part of a training process, wherein the weights help shape the output of the neural network processing module. The neural network may include a linear summation module configured to provide an output signal that is at least partially based on outputs of the one or more neurons.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 28, 2015
    Assignee: Greenray Industries, Inc.
    Inventor: John C. Esterline
  • Patent number: 9071251
    Abstract: In some examples, a circuit is described. The circuit may include a voltage-controlled oscillator that may be configured to generate an output signal. The circuit may also include a control signal generation unit that may be configured to generate a control signal based on the output signal. The control signal generation unit may also be configured to provide the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator and the control signal generation unit may be part of a phase-locked loop (PLL) included in the circuit. The circuit may also include a feed-forward network. The feed-forward network may be configured to provide a portion of the control signal to the voltage-controlled oscillator. The voltage-controlled oscillator may generate the output signal based on the control signal from the control signal generation unit and the portion of the control signal from the feed-forward network.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 30, 2015
    Assignee: WASHINGTON STATE UNIVERSITY
    Inventors: Deukhyoun Heo, Pawan Agarwal
  • Patent number: 9053742
    Abstract: Systems, methods, apparatus, and techniques are provided for producing an estimate of a digital sequence. A continuous-time signal is obtained. The continuous-time signal is sampled with an oversampling factor to produce a discrete-time signal corresponding to the continuous-time signal. A phase offset estimate of the continuous-time signal is produced based on the discrete-time signal. The discrete-time signal is interpolated based on the phase offset estimate to produce an interpolated discrete-time signal. The interpolated discrete-time signal is processed to produce an estimate of a digital sequence.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: June 9, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Hongxin Song, Michael Madden, Gregory Burd
  • Patent number: 9054855
    Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: June 9, 2015
    Assignee: Intel Corporation
    Inventor: Assaf Ben-Bassat
  • Patent number: 9041474
    Abstract: A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: May 26, 2015
    Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Saeed Abbasi, Nima Gilanpour, Michael R. Foxcroft, George A. W. Guthrie, Raymond S. P. Tam
  • Patent number: 9024693
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Patent number: 9007109
    Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: April 14, 2015
    Assignee: Nvidia Corporation
    Inventors: Seydou Ba, Abdellatif Bellaouar, Ahmed R Fridi
  • Patent number: 8994460
    Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Grant P. Kesselring, James D. Strom, Kenneth A. Van Goor, Kennedy K. Cheruiyot
  • Patent number: 8989332
    Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 24, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Rachel Nakabugo Katumba, Darren Roger Frenette, Ardeshir Namdar-Mehdiabadi, John William Mitchell Rogers
  • Patent number: 8981856
    Abstract: An oscillator circuit includes an adjustable frequency oscillator configured to free-run at a first frequency below a desired second target frequency. This adjustable frequency oscillator is configured to modulate a frequency of its periodic output signal upwards from the first frequency to the second frequency in response to a feedback bias current. A divider is also provided, which is configured to convert the periodic output signal to a reduced-frequency control signal. This reduced-frequency control signal is provided to a frequency-to-current (F2C) converter, which is configured to drive the adjustable frequency oscillator with the feedback bias current (e.g., pull-down current) in response to the reduced-frequency control signal.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: March 17, 2015
    Assignee: Integrated Device Technology, Inc.
    Inventor: Trevor Newlin
  • Patent number: 8981855
    Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: March 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Luca Romano, Randy Tsang
  • Patent number: 8963750
    Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: David Canard, Julien Delorme
  • Patent number: 8963594
    Abstract: A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Corporation
    Inventors: Yu-Che Yang, Han-Chang Kang
  • Patent number: 8957735
    Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihide Sai
  • Patent number: 8952736
    Abstract: A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: February 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Ken Evans, Bhupendra Ahuja
  • Publication number: 20150022272
    Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 22, 2015
    Applicant: NVIDIA Corporation
    Inventors: Stephen FELIX, Jeffery BOND, Tezaswi RAJA, Kalyana BOLLAPALLI, Vikram MEHTA
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8901974
    Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Puneet Sareen, Markus Dietl, Ketan Dewan, Edmond F. George
  • Patent number: 8903345
    Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients are associated with the transitioned operating state.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 2, 2014
    Assignee: BlackBerry Limited
    Inventors: Onur Canpolat, Francis Chukwuemeka Onochie
  • Patent number: 8890626
    Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Iuan Liu
  • Patent number: 8884671
    Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: November 11, 2014
    Assignee: Synopsys, Inc.
    Inventor: Jan Grabinski