Particular Error Voltage Control (e.g., Intergrating Network) Patents (Class 331/17)
  • Patent number: 11088696
    Abstract: In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Salvatore Luciano Finocchiaro, Tolga Dine, Gerd Schuppener, Siraj Akhtar, Swaminathan Sankaran, Baher Haroun
  • Patent number: 11038513
    Abstract: A phased locked loop (PLL) having a filter output voltage that is limited to a fraction of the voltage range accepted by the tuning port of a voltage-controlled oscillator (VCO) under control and a control system responsive to the filter output voltage and for summing the filter output voltage with an elevator voltage and applying the summed voltage to the VCO tuning port.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 15, 2021
    Assignee: Raytheon Company
    Inventor: Gary I. Moore
  • Patent number: 11025154
    Abstract: A gate driving circuit for a charge pump with slowed rates of current change for reduced EMI emissions includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes a first current mirror, a first PMOS transistor, a first NMOS transistor, and a second current mirror. Gates of the first PMOS transistor and the first NMOS transistor receive a clock signal. Drains of the first PMOS transistor and the first NMOS transistor output a driving signal. When the first PMOS transistor is turned on, the first current mirror provides a charging current. When the first NMOS transistor is turned on, the second current mirror provides a discharge current.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: June 1, 2021
    Assignee: FocalTech Electronics (Shenzhen) Co., Ltd.
    Inventor: Jun-Qiao Liu
  • Patent number: 10972106
    Abstract: A delay balancing circuit includes a phase detection circuit, a controller, and a delay circuit. The phase detection circuit receives a reference clock signal having a first frequency, and a feedback clock signal derived from an output clock signal. Detection circuitry detects a phase relationship between the reference clock signal and the feedback clock signal. The phase detection circuit generates a detection signal based on the detected phase relationship. The controller operates to sample the detection signal and to generate and pass an update signal to a delay line to update a delay based on the sampled value. The delay circuit receives a third clock signal and applies a delay, based on the update signal, to the third clock signal to generate the output clock signal.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: April 6, 2021
    Assignee: Movellus Circuits, Inc.
    Inventors: Chun-Ju Chou, Yuxiang Mu, Jeffrey Alan Fredenburg
  • Patent number: 10921847
    Abstract: The clock generator is provided and includes a phase detector, a voltage generator, a voltage-to-current converter, and an oscillation circuit. The voltage generator generates a control voltage. The voltage-to-current converter converts the control voltage into an internal current having a level based on a resistance value of a resistor circuit, the resistance value set based on first control information. The oscillation circuit generates a output clock having a frequency based on the level of the internal current and a capacitance value of a capacitor circuit, the capacitance value set based on second control information. The clock generator maintains a frequency value and varies jitter characteristics of the output clock in response to the first control information and the second control information.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangdon Jung, Jaehong Jung, Seunghyun Oh, Kyungmin Lee
  • Patent number: 10868544
    Abstract: A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 15, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Abhijit Kumar Das
  • Patent number: 10862667
    Abstract: A system and method for a frequency detector circuit includes: a transition detector configured to receive a data input and provide a first edge output based on transitions in the data input; a first circuit configured to generate a second edge output; a second circuit configured to generate a third edge output; and a combinational logic configured to output an UP output when at least two of the first edge output, the second edge output, and the third edge output are high and configured to output a DOWN output when the first edge output, the second edge output, and the third edge output are all low.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Valentin Abramzon
  • Patent number: 10862490
    Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Xiaolei Wu, Yin Guo, Haitian Zhou
  • Patent number: 10830171
    Abstract: A vehicle control system includes a processor programmed to control a vehicle subsystem according to a recovered signal generated from an output signal of a sensor, and a product of a time constant of the sensor and filtered changes of the output signal with respect to time such that a magnitude and phase of the recovered signal approach a magnitude and phase of an input signal to the sensor.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: November 10, 2020
    Assignee: Ford Global Technologies, LLC
    Inventor: Tae-Kyung Lee
  • Patent number: 10794770
    Abstract: A signal detection circuit includes: a power terminal; a first current limitation circuit; a second current limitation circuit; a current-voltage conversion circuit; a first p-channel MOS transistor including a source, a gat, and a drain; a first n-channel MOS transistor including a drain, a gate, and a source; and a second n-channel MOS transistor in which a drain is connected to a first connection point connecting the resistor with the drain of the first n-channel MOS transistor, a gate is connected to a second connection point connecting the drain of the first p-channel MOS transistor with the current-voltage conversion circuit, and a source is grounded.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 6, 2020
    Assignees: ABLIC INC., THE RITSUMEIKAN TRUST
    Inventors: Fumiyasu Utsunomiya, Takakuni Douseki, Ami Tanaka
  • Patent number: 10771071
    Abstract: A digitally controlled oscillator (DCO) circuit is disclosed. The DCO circuit comprises a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword. In some embodiments, the tuning circuit comprises an integer tuning circuit configured to process the integer tuning codeword and a fractional tuning circuit configured to process the fractional tuning codeword, in order to implement the input tuning codeword. In some embodiments, the integer tuning codeword comprises an integer tuning range associated therewith and the fractional tuning codeword comprises a fractional tuning range associated therewith. In some embodiments, the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 8, 2020
    Assignee: Apple Inc.
    Inventors: Thomas Mayer, Peter Preyler
  • Patent number: 10698441
    Abstract: A clock distribution and alignment system includes at least three clock generators, each including a clock receiver circuit to receive a first clock signal having a first frequency, and a clock divider circuit to divide the received first clock signal into a second clock signal having a second frequency lower than the first frequency, each of two or more of the clock generators further including a phase detector circuit to compare the phase of the second clock signal with the phase of the second clock signal for a next one of the clock generators, and a clock adjuster circuit to adjust the phase of the received first clock signal based on the compared phases of the second clock signals. In some cases, the clock adjuster circuit is further to align the phases of the second clock signals to within a predefined tolerance of each other.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 30, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Joseph D. Cali, Steven E. Turner
  • Patent number: 10693477
    Abstract: An oscillator subsystem included in a phase-locked loop circuit of a computer system may include coarse and fine-tuning circuits. The coarse-tuning circuit may generate a coarse-tuning current based on a reference voltage, and the fine-tuning circuit may generate a fine-tuning current by combining respective currents generated by first and second complement current mirror circuits using a voltage level of a control signal. An oscillator circuit may generate a clock signal whose frequency is based on a combination of the coarse and fine-tuning circuits.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 23, 2020
    Assignee: Apple Inc.
    Inventor: Cristian Marcu
  • Patent number: 10678294
    Abstract: A method includes receiving, by a recording device, an indication of an initializing time and receiving, by the recording device, an indication of a timing pace. The method also includes maintaining, by the recording device, an updated current time based on the initializing time and the timing pace and sensing, via a sensor of the recording device, a condition. The method further includes storing, in memory of the recording device, an indication of the condition and an associated indication of the updated current time. The indication of the updated current time corresponds to when the condition was sensed by the sensor.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: June 9, 2020
    Assignee: SOUND DEVICES, LLC
    Inventors: Matt Anderson, Francois Morin
  • Patent number: 10623005
    Abstract: A PLL circuit includes a phase comparator, a charge pump 20, a loop filter 30, a voltage controlled oscillator 40, a frequency divider, and a phase compensator 70. The loop filter 30 includes a resistor 31, a first capacitance element 32, and a second capacitance element 33. The phase compensator 70 is provided in parallel to the charge pump 20 and adds a differentiation term to an open-loop transfer function. The phase compensator 70 includes a buffer 71 receiving a phase difference signal output from the phase comparator and a third capacitance element 72 provided between an output terminal of the buffer 71 and an input terminal of the loop filter 30.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: April 14, 2020
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Shunichi Kubo, Mitsutoshi Sugawara, Satoshi Miura, Akihiro Moto
  • Patent number: 10587182
    Abstract: The power conversion device may include a rectification unit, a boost converter for boosting power rectified from the rectification unit, a dc-end capacitor connected to an output end of the boost converter, an inductor current detection unit for detecting an inductor current flowing in an inductor within the boost converter, a dc-end voltage detection unit for detecting voltages of both ends of the dc-end capacitor, and a control unit for controlling the boost converter. The control unit may generate and output a converter switching control signal by performing proportional resonant control for a duty command value of a switching element within the boost converter, based on the detected inductor current and dc-end voltage. Therefore, a harmonic current component flowing through a dc-end capacitor induced by a ripple component of an input voltage may be reduced.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 10, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyeongtae Kim, Yonghwa Lee, Jeongeon Oh
  • Patent number: 10566981
    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingdong Deng, Rupert Shiu Chung Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
  • Patent number: 10566980
    Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Nitin Gupta, Jeet Narayan Tiwari
  • Patent number: 10481246
    Abstract: Embodiments of the present disclosure provide an optical range finder that includes a transimpedance amplifier (TIA) and a photodiode emulation circuitry for testing the TIA. The photodiode emulation circuitry may be coupled to an input port of the TIA and configured to receive one or more parameters specifying one or more characteristics of a test current signal to be provided to the TIA. The photodiode emulation circuitry may further be configured to provide the test current signal in accordance with the one or more parameters to the input port of the TIA while the photodiode is also coupled to the input port of the TIA.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: November 19, 2019
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Devrim Aksin, Yalcin Alper Eken
  • Patent number: 10439793
    Abstract: A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: October 8, 2019
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chung Chen, Wen-Juh Kang, Cheng-Hung Wu
  • Patent number: 10425039
    Abstract: A frequency calibrator includes an input signal generator configured to generate an input signal based on an oscillation signal and an external signal; a frequency difference extractor configured to extract, from the input signal, a frequency difference signal having a frequency corresponding to a frequency difference between an external frequency of the external signal and an oscillation frequency of the oscillation signal; a divider configured to generate a division signal by dividing a signal having the oscillation frequency by a division ratio; and a frequency tuner configured to tune the oscillation frequency of the oscillation signal based on a result of comparing the frequency difference signal to the division signal.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok Ju Yun
  • Patent number: 10361685
    Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: July 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Yoshio Takazawa
  • Patent number: 10340926
    Abstract: Aspects of this disclosure relate to reducing settling time of a sawtooth ramp signal in a phase-locked loop. Information from a loop filter of the phase-locked loop can be stored and used within the loop filter so as to improve the settling time of the sawtooth ramp signal. In certain embodiments, the settling time of a periodic sawtooth ramp signal can be reduced to less than one microsecond. An output frequency at the end of the sawtooth chirp can be brought back to an initial value without significantly modifying phase error in disclosed embodiments.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 2, 2019
    Assignee: Analog Devices Global
    Inventors: Vamshi Krishna Chillara, Declan M. Dalton, Pablo Cruz Dato
  • Patent number: 10289245
    Abstract: A noise detection method including the following steps is provided. During different time periods, plural sets of driving signals are respectively transmitted to driving lines of the touch panel to drive sensing lines of the touch panel to generate plural sets of sensing signals. The plural sets of sensing signals are respectively received and calculated to obtain plural sets of summation signals. One set of summation signals includes first summation signals, and another set of summation signals includes second summation signals. A part or all of the first summation signals is replaced by the second summation signals. A signal value of a combination of the first and the second summation signals is calculated to obtain a summation thereof. The summation of the signal value of the combination is smaller than a summation of a signal values of the first summation signals before recombination.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: May 14, 2019
    Assignee: Novatek Microelectronics Corp.
    Inventors: Hung-Cheng Kuo, Po-Wei Chen, Chun-Hung Chen
  • Patent number: 10270388
    Abstract: According to an embodiment, a voltage-controlled oscillator has a variable capacitive element with a capacitance that is changed by a voltage to be applied thereto. One electrode of the variable capacitive element is connected to a control input terminal where a control voltage that controls an oscillation frequency is applied thereto. It has a compensation voltage generation circuit that generates a voltage that changes with a temperature thereof. It has a resistive element with one end that is directly connected to another electrode of the variable capacitive element and another end that is supplied with an output voltage of the compensation voltage generation circuit.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroaki Hoshino
  • Patent number: 10225069
    Abstract: A CDR circuit includes: a comparison circuit that receives data signal on which a first clock signal is superimposed, and outputs a comparison result obtained by comparing the data signal with three different threshold values at a timing synchronized with a second clock signal; a data pattern detection circuit that detects an occurrence of a data pattern, based on the comparison result; a frequency detection circuit that outputs, when an occurrence of the data pattern is detected, a detection result indicating whether a second frequency of the second clock signal is higher than a first frequency of the first clock signal; an adjustment circuit that outputs, based on the detection result, an adjustment signal for adjusting a phase of the second clock signal and the second frequency; and an oscillator circuit that outputs the second clock signal with the phase and the second frequency adjusted, based on the adjustment signal.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 5, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Wahid Rahman, Ali Sheikholeslami, Takayuki Shibasaki, Hirotaka Tamura
  • Patent number: 10177653
    Abstract: An impedance circuit for a charge pump arrangement and a charge pump arrangement are disclosed. In an embodiment, the impedance circuit includes a first current mirror circuit with a first bias serving as a current input terminal, a first output serving as a current output terminal and a first input for coupling with a pre-selected potential. The impedance circuit further includes a first charge pump for biasing the first current mirror circuit with a first reference current, wherein the first charge pump includes a first biasing output coupled with the first bias of the first current mirror circuit.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 8, 2019
    Assignee: TDK Corporation
    Inventors: Daifi Haoues Sassene, Gino Rocca, Tomasz Hanzlik
  • Patent number: 10164316
    Abstract: A combining arrangement comprises a power combiner having at least four ports. A first match-dependent oscillator is connected to input power at a first frequency to a first input port of the power combiner. A second match-dependent oscillator is connected to input power at a second frequency to a second input port of the power combiner. A mismatch is connected to a third port of the power combiner. The power combiner is operative to combine power from the first and second oscillators and, when the first and second frequencies are different, to apply a fraction of the combined power to the mismatch. The mismatch reflects at least some of the fraction of the combined power to the first and second oscillators to phase and frequency lock their outputs. A fourth output port of the power combiner is connected to receive the combined power.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: December 25, 2018
    Assignee: TELEDYNE E2V (UK) LIMITED
    Inventors: Michael John Duffield, Craig Loch
  • Patent number: 10128864
    Abstract: A non-linear converter comprising a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function, an analog multiplexer having analog multiplexer inputs coupled to the non-linear voltage divider and configured to output an analog multiplexer output, the analog multiplexer chooses one of the plurality of resistors based on a logic signal and the non-linear transfer function, an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive the analog multiplexer output and the analog comparator configured to output a comparator voltage output and a logic loop coupled to the analog comparator and configured to receive the comparator voltage output and configured to output the logic signal, wherein the logic signal represents a linearized digital word.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: November 13, 2018
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 10069498
    Abstract: A packaged VCTCXO may include a crystal oscillator configured to output a signal of a particular frequency and a temperature sensor configured to measure an internal temperature of the crystal oscillator. In addition, the packaged VCTCXO may include a microcontroller configured to generate an internal control voltage signal based at least in part on the temperature and an external control voltage received by the packaged VCTCXO. Moreover, the packaged VCTCXO may include a combiner configured to combine an internal control voltage and the external control voltage to generate a control voltage. Further, the control voltage may be supplied to the crystal oscillator to cause the crystal oscillator to generate the signal of the particular frequency.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 4, 2018
    Assignee: Greenray Industries, Inc.
    Inventor: Jonathan George Scott
  • Patent number: 10033393
    Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 24, 2018
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD
    Inventors: Igal Kushnir, Hung-Ming Chien, Wei-Hong Chen, Theodoros Chalvatzis, Seunghwan Yoon, Chin-Ming Chien, Tirdad Sowlati, Moche Cohen, Kobi Sturkovich, Shaul Klein
  • Patent number: 10009038
    Abstract: An analog-to-digital converter may convert an analog signal into digital codes representative of the changing level of the analog signal. An analog high pass filter may receive and continuously differentiate the analog signal. A voltage controlled oscillator may receive the differentiated analog signal and continuously generates an output that is an integral of the differentiated analog signal in the phase domain. A time-to-digital converter may sample the output of the voltage controlled oscillator and convert each sample into a digital code representative of the current phase of the sampled output of the voltage controlled oscillator.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 26, 2018
    Assignee: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventor: Shuo-Wei Chen
  • Patent number: 9998127
    Abstract: A clock circuit and control method thereof to avoid missing the clock signal generated by the clock circuit when the generated clock signal is synced with an external clock signal, wherein the clock circuit comprises a current compensation circuit and a current control circuit. The clock signal is generated by alternately charging and discharging a capacitor with a charging current based on a sync current and a compensating current when an external clock signal is detected. The compensating current is generated based on a frequency of the external clock signal, and the sync current is provided based on a phase difference between the generated clock signal by the clock circuit and the external clock signal.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: June 12, 2018
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Lei Li
  • Patent number: 9977453
    Abstract: An apparatus for temperature sensing may include: a bias generator suitable for generating a complementary-to-absolute-temperature (CTAT) bias voltage; a regulator suitable for regulating a bias voltage by using CTAT bias voltage and outputting a regulated bias voltage; and a ring oscillator suitable for receiving the regulated bias voltage and generating an oscillation signal based on the regulated bias voltage.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jenn-Gang Chern
  • Patent number: 9954541
    Abstract: A frequency synthesizer comprising a first phase locked loop (PLL) circuit coupled to receive a reference frequency signal from a reference oscillator, the first PLL circuit comprising a first voltage controlled oscillator (VCO) having a bulk acoustic wave (BAW) resonator and a first fractional feedback divider circuit, the first PLL circuit outputting a first tuned frequency signal and a first plurality of integer divider circuits coupled to receive the first tuned frequency signal from the first PLL circuit and each of the first plurality of integer-only post-PLL divider circuits to provide one of a plurality of output frequency signals of the frequency synthesizer.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: April 24, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Pankaj Goyal, Stephen E. Aycock
  • Patent number: 9923554
    Abstract: A wireless power transmitter includes an amplifier configured to amplify a power; a transmitter configured to resonate the power amplified by the amplifier; and a reference signal provider configured to provide a reference signal to the amplifier and change a frequency of the reference signal.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 20, 2018
    Assignees: Samsung Electro-Mechanics Co., Ltd., University of Seoul Industry Cooperation Foundation
    Inventors: Byung Joo Hong, Je Hyuk Ryu, Hyung Gu Park, Joong Ho Choi, Hong Jin Kim, Joo Young Lee, Dong Hyeon Seo, Young Jun Park, Jong Woo Lee, Kang Yoon Lee
  • Patent number: 9847178
    Abstract: A circuit for controlling a capacitor having a capacitance adjustable by biasing, including an amplifier for delivering a D.C. bias voltage, having a feedback slowed down by a resistive and capacitive cell.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: December 19, 2017
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventor: Sylvain Charley
  • Patent number: 9784770
    Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Intel Corporation
    Inventors: Shih-An Yu, Yu-Hong Lin, Sen-You Liu, Fang-Ren Liao
  • Patent number: 9780449
    Abstract: A method includes injecting a reference input signal into each Voltage Controlled Oscillator (VCO) of a number of VCOs forming a coupled VCO array to reduce a level of injection energy required therefor. The reference input signal is configured to control operating frequency of the coupled VCO array. The method also includes utilizing a phase shift circuit: between individual VCOs of the coupled VCO array and/or in a path of injection of the reference input signal into one or more VCO(s) of the individual VCOs, and mixing outputs of the number of VCOs with signals from antenna elements of an antenna array to introduce differential phase shifts in signal paths coupled to the antenna elements during performing beamforming with the antenna array. Further, the method includes reducing a phase-steering requirement of the coupled VCO array during the beamforming based on the utilization of the phase shift circuit.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: October 3, 2017
    Assignee: Integrated Device Technology, Inc.
    Inventors: Christopher T. Schiller, Jonathan Kennedy
  • Patent number: 9748932
    Abstract: A phase locked loop includes a signal receiver configured to generate a mixed signal based on the received signal and an oscillator signal, and a frequency control circuit configured to compare the mixed signal to a reference signal, and adjust the oscillator signal based on a result of the comparing.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 29, 2017
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Jaesup Lee, Sang-Gug Lee, Jae-Seung Lee, Seok-Kyun Han
  • Patent number: 9735790
    Abstract: A radio communication device has an analog control loop unit to generate an analog control signal that adjusts a phase of a voltage control oscillation signal, a digital control loop unit to generate a digital control signal having a frequency determined by a frequency of a reference signal and a predetermined frequency setting code signal and a phase opposite to a phase of the analog control signal, a voltage controlled oscillator to generate the voltage control oscillation signal, a data slicer to generate a digital signal including the reception signal, an automatic offset controller to generate a correction signal in response to an error between a frequency of the reception signal and a frequency of the voltage control oscillation signal, and a setting code adjuster to adjust the frequency setting code signal, wherein gain of the digital control loop unit is higher than gain of the analog control loop unit.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: August 15, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akihide Sai, Hidenori Okuni, Masanori Furuta
  • Patent number: 9735788
    Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 15, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ja Yol Lee, Minjae Lee, Cheon Soo Kim, Jaehyun Kang, Junsoo Ko
  • Patent number: 9722616
    Abstract: A determination circuit receives an input data signal and determines a value of the input data signal when a logic level of a sampling clock changes. A sampling clock generation circuit generates the sampling clock on the basis of the input data signal, generates a frequency adjustment value on the basis of the frequency difference between the sampling clock and the input data signal, and adjusts the frequency of the sampling clock on the basis of the frequency adjustment value. A frequency pull-in control circuit performs integration on frequency adjustment values and obtains an integral value in an individual time period. When the integral value reaches a threshold before a single time period elapses, the frequency pull-in control circuit outputs a reset signal that causes the sampling clock generation circuit to output an initial value of the frequency adjustment value until the time period elapses.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Takayuki Shibasaki
  • Patent number: 9712317
    Abstract: In some aspects, the disclosure is directed to methods and systems for carrier synchronization in active load modulation for near field communications. A broadcast carrier is received from a remote device and mixed with a locally-generated carrier and modulated data. A carrier synchronization circuit synchronizes the locally-generated carrier with the broadcast carrier based on an identified phase error from a double Cartesian-to-polar mapping of the mixed locally-generated carrier and broadcast carrier. In some implementations, the system also includes a modulation suppression circuit for providing unmodulated carrier signals to the carrier synchronization circuit or suppressing modulation distortion to maintain frequency and phase tracking despite the presence of data.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: July 18, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Manolis Frantzeskakis, Dong-U Lee, Divyanshu Jain, Jianhua Gan, Shengyang Xu
  • Patent number: 9679885
    Abstract: Disclosed are systems, devices, circuits, components, mechanisms, and processes in which a switching mechanism can be coupled between components. The switching mechanism is configured to have an on state or an off state, where the on state allows current to pass along a current path. A monitoring mechanism has one or more sensing inputs coupled to sense an electrical characteristic at the current path. The electrical characteristic can be a current, voltage, and/or power by way of example. The monitoring mechanism is configured to output a reporting signal indicating the sensed electrical characteristic. The monitoring mechanism can be integrated with the switching mechanism on a chip.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: June 13, 2017
    Assignee: Volterra Semiconductor Corporation
    Inventors: David Lidsky, Ognjen Djekic, Ion Opris, Budong You, Anthony J. Stratakos, Alexander Ikriannikov, Biljana Beronja, Trey Roessig
  • Patent number: 9680479
    Abstract: An electronic apparatus includes a voltage-controlled oscillator and a biasing circuit. The voltage-controlled oscillator includes varactors. The voltage-controlled oscillator is configured to output an oscillating frequency at a first temperature. The biasing circuit electrically coupled with the varactors is configured to provide a first biasing voltage to the varactors at the first temperature, and provide a second biasing voltage to the varactors at a second temperature, in which the varactors have a first temperature coefficient, and the biasing circuit generates the first biasing voltage and the second biasing voltage according to values of the first temperature coefficient and a second temperature coefficient.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: June 13, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Che-Wei Chang
  • Patent number: 9628262
    Abstract: An embodiment of the present disclosure provides a phase locked loop. A controllable oscillator generates a radio frequency (RF) signal. A divider is configured to produce a divided RF signal by dividing the RF signal by a division factor. A phase detection circuit is configured to receive a dithered reference signal and the divided RF signal and to produce a phase error signal for controlling the oscillator. A dithering module is configured produce the dithered reference signal and the division factor, in which the dithered reference signal has a randomly changing frequency selected from a plurality of dither frequencies, and in which the division factor is synchronously selected to match a ratio between each selected dither frequency and a target frequency of the RF signal.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 18, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Marius Moe
  • Patent number: 9606645
    Abstract: A display apparatus is provided. The display device includes pixels, a data line, a first current compensation unit, a second current compensation unit, and a control unit. The first current compensation unit is configured for providing a first current to pixels through the data line. The first current is configured for compensating a leakage current that flows out of the data line. The second current compensation unit is configured for sinking a second current from pixels through the data line. The second current is configured for compensating the leakage current that flows into the data line. The control unit is configured for controlling the first current compensation unit to provide the first current or controlling the second current compensation unit to sink the second current according to a voltage of the data line.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: March 28, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chun-Chieh Lin, Hua-Gang Chang, Chih-Cheng Chen
  • Patent number: 9590643
    Abstract: A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John W. Stanton, Pradeep Thiagarajan
  • Patent number: 9565042
    Abstract: An ultra-low power transmitter applied in multi-channel frequency shift keying (FSK) communication is provided. The transmitter includes a fixed-frequency generation device, a low-frequency frequency synthesizer, and an injection locking device. The fixed-frequency generation device provides a reference frequency to the low-frequency frequency synthesizer. The frequency synthesizer divides the reference frequency with corresponding divisors for generating a plurality of divided frequency signals. Then, the divided frequency signals are injected into the injection locking device. The injection locking device will lock at the average frequency of previously mentioned divided frequencies. Wherein, the injection locking device filters the high frequency noise, which is produced by the frequency synthesizer, at the time of the injection locking. The ultra-low power transmitter obtains a high-frequency transmitted signal by using the frequency-locked signal.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 7, 2017
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Kuang-Wei Cheng, Wen-Hao Ho, Sheng-Kai Chang