Abstract: A dual phase-locked loop (PLL) circuit includes a phase/frequency detector, a charge pump, a frequency tuning circuit and an N divider. The frequency tuning circuit includes a coarse-tuning circuit, for coarse-tuning an output frequency of the dual PLL circuit to approximate a target frequency; a fine-tuning circuit, for fine-tuning the output frequency of the dual PLL circuit to the target frequency; and a current control oscillator (CCO), for generating an output signal of the dual PLL circuit. The output frequency of the output signal is equal to the target frequency.

Abstract: A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Abstract: A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.

Abstract: A device may include an oscillator to generate a clock signal based on first and second control signals. The oscillator may include a first buffer stage a second buffer stage. The first buffer stage may output a first signal that is based on an output of the second buffer stage and the first control signal. The second buffer stage may output the clock signal. The clock signal may be based on the first signal and the second control signal.

Abstract: A method and apparatus for compensating for temperature variation in a phase locked loop (PLL) includes receiving an error signal by a controller in which the error signal representative of an instantaneous frequency difference between a reference frequency signal and an output frequency signal of a voltage controlled oscillator of the PLL, and determining when a voltage of the error signal is outside of a predetermined voltage range. When the voltage is outside the predetermined voltage range, the method includes generating a new digital compensation signal based upon a previous digital compensation signal, and converting the new digital compensation signal to be an analog compensation signal. The method further includes filtering the analog compensation signal by a filter to produce a filtered analog compensation signal, and adjusting the output frequency of the voltage controlled oscillator in accordance with the filtered analog compensation signal.

Abstract: A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.

Abstract: A PLL frequency synthesizer provides improved phase noise characteristics. In an ADPLL frequency synthesizer, a frequency characteristic adjusting unit compares a predetermined threshold to the difference between the fractional portion of a DCO control signal and the closest integer value, and generates an adjustment signal. A supplementary varactor shifts the oscillating frequency characteristics based on the adjustment signal. By setting the predetermined threshold to a value defining the range in which the possibility of incrementing or decrementing is high, the oscillating frequency characteristics are shifted in cases when the target value of the fractional portion of the DCO control signal is in the range in which the possibility of incrementing or decrementing is high. By shifting the oscillating frequency characteristics, the target value of the fractional portion of the DCO control signal are shifted to a range in which the possibility of incrementing or decrementing is low.

Abstract: System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Abstract: Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal.

Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients coefficient are associated with the transitioned operating state.

Abstract: A digital FLL/PLL is provided which is capable of converging an oscillation frequency from a VCO to a desired frequency at a high speed even without setting a damping factor corresponding to each VCO gain. A digital FLL/PLL of the present invention includes: a comparator for comparing a channel signal to a loopback signal having an oscillation frequency to generate a signal error; a digital loop filter for generating a control voltage that determines the oscillation frequency, on the basis of the signal error; a VCO for controlling an oscillation frequency on the basis of the control voltage; a loopback path through which the oscillation frequency generated by the VCO is outputted as the loopback signal to the comparator; and a control section for monitoring the signal error, and controlling the digital loop filter such that the oscillation frequency of the VCO becomes a stationary state, when detecting that the signal error meets a predetermined condition after the channel signal is switched.

Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal.

Abstract: A signal processing apparatus of the present invention includes an input unit configured to receive a reference signal supplied from an external device, a phase detection unit configured to detect a phase difference between the reference signal received from the input unit and a clock signal, a generation unit configured to generate the clock signal with a frequency corresponding to an output of the phase detection unit, and a control unit configured to detect an error between a frequency of the reference signal received from the input unit and the frequency of the clock signal based on an output of the phase detection unit and to output information, which indicates the status of a frequency change in the reference signal, to a display device based on the detected error.

Abstract: A method and device for managing a reference oscillator within a wireless device is presented. The method includes selecting reference oscillator parameters associated with the lowest reference oscillator error, where the selection is based upon reference oscillator parameters derived using different technologies within a wireless device, acquiring a satellite based upon the selected reference parameters, determining the quality of the satellite-based position fix, and updating the reference oscillator parameters based upon the quality of the satellite-based position fix.

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Abstract: A voltage-controlled oscillator generates a first signal and a second signal having a phase reverse to that of the first signal. A switch supplies a current signal generated by a first charge pump to a loop filter. A counter counts a cycle number of the second signal included in one cycle period of a reference signal. A second charge pump supplies, to the loop filter, a first current signal having a constant value and a second current signal having a constant value whose polarity is reverse to that of the first current signal. The control circuit controls the switch and the second charge pump based on a comparison between the cycle number of the second signal counted by the counter and a value X.

Abstract: Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.

Abstract: A PLL circuit includes a storage unit for storing a control voltage at a desired frequency obtained when a reference signal is synchronized with a referenced signal; a current generator circuit that includes a pull-up circuit and a pull-down circuit, each of which outputs an electric current at a predetermined timing; a voltage detecting unit that detects an output voltage corresponding to an electric current output by the current generator circuit; and a current control unit that changes a current value of at least one of the pull-up circuit and the pull-down circuit so that respective current values match each other, and controls the respective current values of the pull-up circuit and the pull-down circuit so that the output voltage detected by the voltage detecting unit matches the control voltage stored in the storage unit.

Abstract: A PLL circuit is provided with an AD converter, a DA converter to which output from the AD converter is inputted, a filter circuit filtering an output signal of the DA converter, a voltage control oscillator outputting a signal of a different frequency in accordance with an output signal from the filter circuit and a frequency divider dividing a signal which the voltage control oscillator outputs. The AD converter operates by a timing signal from the voltage control oscillator and the DA converter outputs an analog signal corresponding to a value which the AD converter outputs by the timing signal outputted from the frequency divider.

Abstract: Methods and apparatus are described for reducing noise, such as phase noise, in an oscillating signal. The oscillating signal may be generated by a signal generator having a mechanical resonator, such as a crystal oscillator. A filter may be coupled to the output of the mechanical resonator and may have its center frequency adjusted using a phase-locked loop (PLL). A feedback signal from the filter to the signal generator may also be used.

Abstract: A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

Abstract: The present invention is a high power direct transmitter with frequency-shift keying (FSK) modulation. The transmitter implements a high power, high efficiency power voltage-controlled oscillator (VCO) which allows for production of a modulated RF signal at the final stage (ex.—right at the antenna), thereby eliminating all driving stage power amplification and frequency translation. The transmitter further provides a low SWAP-C alternative to currently available solutions.

Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Abstract: An oscillator circuit in accordance with an aspect of the present invention includes a filter capacitor that generates an oscillating frequency control voltage according to a charge amount accumulated based on an oscillating frequency setting current, an oscillator that changes a frequency of an oscillation signal to be output according to the oscillating frequency control voltage, a control circuit that generates a timing control signal, a frequency detection circuit that generates a frequency detection voltage based on the timing control signal, a voltage level of the frequency detection voltage being changed according to a length of the period of the oscillation signal, and a differential amplifier that continuously changes the oscillating frequency setting current according to a voltage difference between the frequency detection voltage and a reference voltage, and outputs the resultant oscillating frequency setting current to the filter capacitor.

Abstract: A programmable filter for LC tank voltage controlled oscillator (VCO) and a design structure for a programmable filter for LC tank VCO. The programmable filter includes a proportional control comprising a plurality of capacitance biased by different input voltages and an integral control comprising a filter element with a capacitance C1 and a set of capacitance biased by a voltage output of the filter element.

Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A local oscillator (LO) module comprises a local oscillator and a feedback circuit. The local oscillator, biased at a supply voltage, generates a local oscillator signal having a duty cycle. The feedback circuit makes an absolute adjustment of the duty cycle of the local oscillator signal in response to a difference between a first voltage signal, representing a voltage level of the local oscillator signal, and a second voltage signal, representing a voltage level of a portion of the supply voltage corresponding to a desired duty cycle for the local oscillator signal.

Abstract: The present invention provides an oscillator and a communication system using the oscillator, in particular, an LC oscillator adapted to lessen phase noise deterioration due to harmonic distortions and increase the amplitude of oscillation, thereby having a favorable low phase noise characteristic. The oscillator comprises at least one voltage to current converter consisting of a transistor and a resonator comprising two LC tanks consisting of a pair of conductive elements and inductive elements. A feedback loop is formed such that an output terminal of the voltage to current converter is connected to the resonator and a current input to the resonator is converted to a voltage which is in turn fed back to an input terminal of the voltage to current converter. Inductive elements constituting the two LC tanks constituting the resonator are mutually inductively couple and a coefficient of the mutual induction is about ?0.6.

Abstract: A systems and methods for providing phase lock conditions detection, such as a quality of phase lock and loss of lock detection, are described herein. One exemplary method comprises detecting an output frequency, comparing the output frequency with a first reference signal, providing a first signal and a second signal as a function of the output frequency and first reference signal comparison, receiving a predetermined threshold from a second reference signal, monitoring a deviation of the first and second signals from the predetermined threshold, generating a third signal as a function of the deviation, comparing the third signal to a window threshold wherein the window threshold is set based on a predetermined loop variable, generating a fourth signal a function of the third signal and the window threshold comparison, and providing an alarm based on the fourth signal.

Abstract: A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (gm) than if a single transistor were used while maintaining the same loop bandwidth and drain-to-source current through the transistor. As a result of a smaller transconductance in the VCO, a larger resistor can be used in the loop filter without increasing the noise. With a larger resistor, a smaller capacitor can be used in the loop filter as well. Alternatively, the transconductance can be reduced by a certain factor and the resistance value can be increased by the same factor to maintain a constant loop bandwidth but with a reduction in the amplitude of the noise. Thus, a smaller loop filter capacitor can be achieved albeit with the same noise level, or a lower noise level with the same size capacitor for the loop filter.

Abstract: A technique to use a two-step calibration procedure to calibrate a voltage controlled oscillator (VCO) of a phase-locked loop. The first calibration step is an open-loop calibration procedure in which a control voltage of the VCO is temperature compensated and the VCO is tuned using a search routine to generate a corresponding output frequency based on the control voltage. The second step is a closed-loop calibration procedure to adjust the tuning components of the VCO to correct for a 1 LSB error.

Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensation signal in dependence on the output of the oscillator and a reference signal; a correlator configured to frequency correlate an interferer signal and the low frequency compensation signal, and in dependence on that correlation generate a correlation signal; and an adaptive filter configured to adapt the interferer signal in dependence on the correlation signal to output a high frequency compensation signal; and a summation unit configured to combine the low frequency compensation signal and the high frequency compensation signal to form a control signal to drive the input of the oscillator.

Abstract: A PLL circuit comprises a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and two variable voltage sources. The phase detector and the charge pump each comprises low-voltage transistors, and operates with a fixed supply voltage VCC1 (e.g., 5 V) which is a potential difference applied from the variable voltage source of a power-supply voltage VL and the variable voltage source of a power-supply voltage VDC (=VL+VCC1). A tuning control signal VC generated by integrating an output current signal of the charge pump using the loop filter is input to the VCO having an input voltage range of the tuning control signal from 0 V to VCC2 (e.g., 16 V).

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: Aspects of a method and system for reduced clock feed-through in a phase locked loop are provided. In this regard, a control voltage for controlling a VCO may be generated via a filter comprising at least one switching element clocked via a clock booster circuit and comprising one or more thick oxide transistors to reduce clock feed-through. A first switching element of the filter may be a first transmission gate comprising thick oxide transistors. The first transmission gate may be part of a sample and hold circuit. A DC voltage on an input node of the sample and hold circuit may be periodically reset via a reset switching element, which may comprise thick oxide transistors. The reset switching element may be controlled via a clock booster circuit. The filter may also comprise a buffer having an input stage comprising one or more thick oxide transistors.

Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract: A loop filter for a phase-locked loop that generates an output signal having a predetermined phase relationship with a reference signal, the loop filter being arranged to control a signal generator that forms the output signal in dependence on a phase error between the output signal and the reference signal by outputting a control signal for controlling the signal generator in dependence thereon, the loop filter being arranged to form the control signal to comprise a proportional component representative of an instantaneous magnitude of the phase difference and an integral component representative of an integral of the phase difference, the loop filter comprising a proportional path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the proportional component of the control signal in dependence thereon and an integral path arranged to receive a signal representative of the instantaneous magnitude of the phase difference and form the integral component o

Abstract: A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Abstract: An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator.

Abstract: A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency.

Abstract: A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).