Abstract: Described is circuitry for improving the acquisition/locking time of phase-locked loops (PLL). The circuitry includes a node for tapping voltage from a PLL, with an analog-to-digital converter (ADC) to convert the voltage to a digital signal. A memory module stores the digital signal. A digital-to-analog converter (DAC) converts the digital signal to an analog output. A comparator/threshold detector is included to compare the voltage from the node to the analog signal from the DAC. Based on the comparison, the comparator/threshold detector provides a signal to the memory module to cause the memory module to update its stored digital signal. Upon power-up, the saved voltage is forced into the PLL to force the PLL nodes to the saved values as an initial condition, thereby decreasing acquisition time in the phased locked loop.

Abstract: A frequency phase locked loop (FPLL) includes a first feedback loop coupled to a second feedback loop. The first feedback loop is configured to correct a phase offset of an output signal of the FPLL. The second feedback loop is configured to correct a frequency offset of the output signal of the FPLL.

Abstract: Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.

Abstract: A signal processing circuit includes a feedback control loop that includes a loop filter and that detects the difference between a target value and a control value to control the difference so that the difference has a predetermined value. A closed loop formed in the feedback control loop is expressed by the delay of the entire closed loop serving as the feedback control loop, the loop filter, and simple integration of a final stage. The signal processing circuit includes a moving average calculating unit configured to calculate a moving average of outputs from the loop filter; a multiplying unit configured to multiply a value calculated in the loop filter by a certain gain; and an integrating unit provided upstream of the loop filter so that calculation results by the moving average calculating unit and the multiplication unit are concurrently fed back to an input into the loop filter.

Abstract: A phase-locked loop (PLL) system generates an oscillator signal based on an input reference signal. A calibration circuit generates a calibration current, and a voltage-to-current converter converts a control voltage into a first current. A current-controlled oscillator generates the oscillator signal based on the first current and the calibration current. A charge pump circuit, which is connected to a phase detector, the voltage-to-current converter, and the calibration circuit, generates a charge pump current based on the first current and the calibration current. The charge pump current is used to generate the control voltage based on an error signal.

Abstract: An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.

Abstract: A VCO driving circuit and a frequency synthesizer wherein the impedance viewed from a VCO control terminal is reduced to prevent the VCO phase noise characteristic from degrading. A VCO driving circuit and a frequency synthesizer having the VCO driving circuit, which comprises a coarse adjustment DAC that receives a digital data, which has a coarse adjustment frequency, to output an analog signal; a fine adjustment DAC that receives a digital data, which has a fine adjustment frequency, to output an analog signal; a low response speed LPF5 that removes noise from the output signal from the coarse adjustment DAC and then provides the resultant signal as an input to a VCO control terminal; a high response speed LPF7 that converts the output signal from the fine adjustment DAC to a voltage, thereby smoothing the signal; a resistor that connects an input stage of the LPF5 to that of the LPF7; and a capacitor used for providing a capacitive coupling such that the output of the LPF7 is added to that of the LPF5.

Abstract: Provided is an oscillation frequency control circuit for correcting its frequency, keeping the oscillation frequency stable when self-oscillating, and oscillating with a control voltage generated by making a fixed voltage given from outside variable. In the oscillation frequency control circuit, a CPU selects/outputs the control voltage preferentially according to a command of a control voltage selection. If the command is not given and the level of an outside reference signal detected by a detecting circuit is within an adequate range, it turns a select switch on. If the command is not given and the level of the outside reference signal is out of the adequate range, it turns the select switch off and outputs information about pulse generation stored in a memory to a PWM circuit.

Abstract: A circuit can be used to a control the voltage of a voltage controlled oscillator (VCO) can include a first comparator, a second comparator, an accumulator, and an output device. The first comparator outputs a first pulse signal when the control voltage is higher than a high threshold voltage. The second comparator outputs a second pulse signal when the control voltage is lower than a low threshold voltage. The accumulator increases the value of a switch control signal if the first pulse signal is received or decreases the value of the switch control signal if the second pulse signal is received. The output device generates a compensation voltage to compensate the control voltage of the VCO depending on the value of the switch control signal.

Abstract: A frequency generation unit (FGU) 100 includes a plurality of selectable voltage controlled oscillators (110) whose output frequencies are chosen in relationship with a predetermined intermediate frequency (IF) and frequency divider value (M) to provide multi-band frequency generation capability in a single communication device. A programmable reference divider (104), phase detector (174) and programmable charge pump (106) take an incoming reference frequency (120) and generate a charge pump output (124) to optimize the in-band phase noise in the FGU 100. A fixed loop filter (108) filters the charge pump output (124) to generate a control voltage (126) for the selectable VCOs (110). The desired frequency band is selected and enabled using control logic (128).

Abstract: A frequency synthesizer includes a phase locked loop (PLL) for generating a desired frequency. The PLL includes two loop filters. A characterization circuit is included, which is configured to receive a digital word for characterizing the PLL and provide a pre-charge value for pre-charging one of the loop filters to generate the desired frequency. A successive approximation analog to digital (A/D) converter is coupled between the loop filters and the characterization circuit, for providing both (a) the digital word to the characterization circuit, and (b) the pre-charge value to the selected loop filter. The digital word includes n-bits ranging in values from a most significant bit (MSB) to a least significant bit (LSB), and the pre-charge value is formed by the n-bits. The successive approximation A/D converter includes a successive approximation register (SAR) for forming the digital word, and a digital to analog (D/A) converter for forming the pre-charge value.

Abstract: In a PLL circuit, a voltage controlled oscillator 4 has two voltage-current conversion circuits 40 and 41 and a selection circuit 42 for selecting an output of either one of the voltage-current conversion circuits 40 and 41. The output of the voltage-current conversion circuit selected by the selection circuit 42 is inputted to a current controlled oscillator 45. The one voltage-current conversion circuit 41 has an input thereof connected to an output of a loop filter 3, while the other voltage-current conversion circuit 40 has an input thereof connected to an input terminal 8 for evaluating the oscillation characteristics of the voltage controlled oscillator 4.

Abstract: A clock distribution circuit, which is provided in IC that has a first sequential circuit receiving first clock through a first branch node on a first clock network, a second sequential circuit receiving second clock through a second branch node on a second clock network, and a data transfer path between the first and second sequential circuits, includes: a first PLL receiving a first feedback clock that is the first clock branched at the first branch node and outputting the first clock to the first clock network based on the first feedback clock; and a second PLL receiving a second feedback clock that is the second clock branched at the second branch node and outputting the second clock to the second clock network based on the second feedback clock. A branch node is provided at least one of between the first PLL and the first branch node and between the second PLL and the second branch node.

Abstract: An oscillator includes: a vibrator having a first electrode and a second electrode disposed with a gap with the first electrode; a reference voltage supply circuit adapted to supply a reference voltage; and a voltage adjustment circuit having a step-up circuit operating in response to input of clock pulses and adapted to convert the reference voltage into a voltage of a predetermined level and to output the voltage of the predetermined level, wherein the vibrator is configured so as to apply the voltage of the predetermined level, which is output from the voltage adjustment circuit, between the first electrode and the second electrode, and the clock pulses to be input into the step-up circuit are obtained using the vibrator as a source.

Abstract: Provided is a voltage-controlled oscillator that can hold an oscillation frequency at a desired value when an oscillation frequency changes due to the temperature, without narrowing a variable range of the oscillation frequency, and a PLL circuit, an FLL circuit, and a wireless communication device, which use the voltage-controlled oscillator. A control voltage Vt is applied to a connection point Y between variable capacitors 121 and 122 included in a variable capacitance circuit 120. A control signal Fse1 is applied to a switching element 132 included in a capacitance switching circuit 130. A power-supply voltage Vdd is applied by a control section 170 to a connection point X between inductors 111 and 112 included in an inductor circuit 110. A voltage value of the power-supply voltage Vdd is controlled such that the oscillation frequency of the local oscillation signal is held at a constant regardless of a temperature change.

Abstract: An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Abstract: A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

Abstract: A PLL circuit which can absorb variation of phase noise characteristic due to temperature and individual difference and has a phase noise suppression characteristic stable in a wide frequency band is provided. The PLL circuit comprises, at the succeeding stage, a first register for storing a first parameter for controlling the loop gain, a first multiplier for multiplying the output of the phase comparator by a first parameter, a second register for storing a second parameter for controlling the response characteristic, a second multiplier for multiplying the output of the first multiplier by a second parameter, and a CPU for setting optimum parameters in the first and second registers depending on the use frequency band, the ambient temperature, and the device individual difference. By controlling the loop gain and the response characteristic to optimum values, a good suppression characteristic in a wide frequency band is achieved.

Abstract: A digital phase locked loop has a digital controlled oscillator, a feedback loop coupled to the output of said digital controlled oscillator, a phase detector for comparing a feedback signal from said feedback loop with a reference signal to produce a phase error signal, and a low pass filter for filtering the phase error signal for controlling said digital controlled oscillator. A bandwidth calculation unit calculates the required filter bandwidth based on the phase error. The bandwidth calculation unit then controls the bandwidth of said low pass filter, which is thus adaptively adjusted in accordance with the phase error.

Abstract: A phase locked loop with a current leakage adjustment function is provided. The phase locked loop includes a phase locked loop unit having a compensation voltage node, a digitalized leakage-detection circuit generating a plurality of digital control signals based upon the phase error between a reference clock signal and a feedback signal, and a compensation circuit generating a compensation current based upon the plurality of digital control signals. When there exist current leakages of the MOS capacitors, the current leakage adjustment circuits provided by the present invention may prevent the conventional phase locked loop from un-locking due to jittering.

Abstract: A low pass filter can be built in a chip by reducing the value of circuit element forming a low pass filter in a PLL circuit, especially by reducing the value of a electrostatic capacity. An active filter used in a PLL circuit having two charge pump circuits in a subsequent stage of a phase comparator includes a first circuit component connected between the output of one charge pump circuit and a ground, a second circuit component between the output of another charge pump circuit and the ground, and a voltage adder for adding up voltages between both ends of each of the first and second circuit components.

Abstract: In a method and apparatus for controlling damping and bandwidth in a phase locked loop (PLL), a loop filter is configured to have a dual path for charge pump current. A 3 dB bandwidth of the PLL is controlled by adjusting gain of a proportional current path. An integral current path includes a gating circuit to digitally control an amount of time an integral charge pump current received is passed through as an effective integral charge pump current. A resistor and capacitor (RC) circuit filters the proportional and effective integral charge pump currents, thereby providing a filtered input to a voltage controlled oscillator. Damping and hence peaking of the PLL is precisely controlled by sampling one of every p samples of the integral charge pump current to provide the effective integral charge pump current, p being an integer.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha—?) and an integral loop gain control having a programmable loop gain coefficient (rho—?). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged.

Abstract: There is provided an oscillator including: a reference signal generator that generates a reference signal having a reference frequency; a phase comparator that outputs a voltage in accordance with a phase difference between the reference signal and a feedback signal; a loop filter that receives a voltage output from the phase comparator, and gain-adjusts a voltage output from the phase comparator by means of an external control signal; a voltage controlled oscillator that oscillates an output signal at a frequency in accordance with an adjusted signal having been gain-adjusted by the loop filter; and a frequency divider that feeds back a frequency-divided signal resulting from frequency-dividing the output signal, to the phase comparator as the feedback signal.

Abstract: A phase locked loop (“PLL”) includes a voltage controlled oscillator (“VCO”) operable to acquire and maintain lock at a selected output frequency of the VCO and control logic operable to perform steps in a method of selecting a frequency band for operating the VCO.

Abstract: An oscillator circuit generates a constant delay time by use of a current source and a load element to determine a frequency of a clock. The oscillator circuit includes an integrator which integrates the clock, a first comparator which compares an output voltage of the integrator with a reference voltage, and a variable current source which changes a current in accordance with the comparison result of the first comparator. The frequency is corrected in accordance with the current of the variable current source.

Abstract: A method is provided for selecting an operating band of a voltage-controlled oscillator (“VCO”) of a phase locked loop (“PLL”) for which the lock frequency is closest to a center of the frequency range of the operating band. In such method, steps can be performed to determine the maximum and minimum frequencies of the operating band and the center frequency between them. From the center frequency of the operating band and the lock frequency within such operating band, a difference value can then be determined. The operating bands of the PLL can be tested until an operating band having the smallest difference value is determined. The VCO can then be set to such operating band in order for the lock frequency to be closest to the center frequency of the operating band.

Abstract: According to a preferred embodiment, a clock signal generation circuit includes an oscillating circuit configured to output a clock signal having a clock frequency corresponding to a control signal, a counter configured to generate a count value by counting a pulse number of the clock signal outputted from the oscillating circuit during a predetermined time period, a subtracting circuit configured to produce differential data by subtracting the count value from a preset value previously set based on a predetermined clock frequency, a control signal correcting circuit configured to generate a correcting control signal by correcting a value of the control signal based on the differential data, and a digital-analog converter circuit configured to convert the correcting control signal into an analog correcting control signal and output the converted analog correcting control signal to the oscillating circuit.

Abstract: Provided is a PLL apparatus outputting a frequency signal from a voltage-controlled oscillation unit in synchronization with an external reference frequency signal, in which the fluctuation of the frequency is reduced even when the external reference signal has a trouble For solving the problem, as a result of monitoring the signal level of the external reference frequency signal, when its signal level falls within a set range, data regarding a phase difference created by a phase difference data creating means is used for the PLL control, but when the signal level does not fall within the set range, it is recognized that the supply of the signal has been stopped or the supplied signal has abnormality and the data regarding the phase difference stored in a storage unit, for example, the stored latest data or the pre-created data is used instead for the PLL control.

Abstract: A PLL circuit for two point modulation includes a first loop filter, a second loop filter, a plurality of switching devices, and a calibration module. The first loop filter filters an output voltage of a charge pump during a gain calibration operation. The second loop filter filters the output voltage of the charge pump during a normal operation. The first loop filter has a bandwidth wider than that of the second loop filter to perform a fast calibration by reducing a lock time. The operation of the first loop filter, the operation of the second loop filter, and the opening of the first loop filter are determined by the switching operations of the switching devices. The calibration module adjusts a gain of analog modulation data based on a frequency error accumulated in the first loop filter after the first loop filter is open during the gain calibration operation.

Abstract: An embodiment pertains to a phase locked loop (PLL) circuit. The PLL includes a voltage controlled oscillator which outputs a signal at a desired frequency. A phase detector is coupled to an output from the voltage controlled oscillator. The phase detector compares the phase of a signal output from the voltage controlled oscillator (VCO) with the phase of a reference signal. A loop filter is coupled to the VCO and the phase detector. The loop filter has a locking mode of operation for locking the phase of the VCO signal to the phase of the reference signal. The loop filter can subsequently be placed in a tracking mode of operation which adjusts the phase of the VCO signal to track the phase of the reference signal.

Abstract: An apparatus for providing an angle modulated signal includes a tunable oscillator circuit, a variable time delay circuit, and an optional scaling and delay control apparatus. The tunable oscillator circuit generates an oscillatory signal having a predetermined frequency. The variable time delay circuit operates to delay the oscillatory signal in accordance with time varying changes in an angle control signal, thereby producing the desired angle modulated signal. The scaling and delay control apparatus is configured to scale the angle control signal to account for frequency dependent phase delays of the oscillatory signal through the variable time delay circuit.

Abstract: There is provided a PLL circuit 15, a voltage follower 19, and an output terminal 23, and a control voltage V1 of a voltage controlled oscillator circuit in the PLL circuit 15 is outputted to the output terminal 23 via the voltage follower 19.

Abstract: A voltage controlled oscillator includes first and second variable capacitance circuits 120 and 130, and first and second capacitance switch circuits 140 and 150. A control voltage Vt is fixedly applied to the first variable capacitance circuit 120, and control signals Fsel2 and Fsel3 are fixedly applied to the first and second capacitance switch circuits 140 and 150, respectively. In a case where both of the control signals Fsel2 and Fsel3 are at a low level, the control signal Fsel1 is applied to the second variable capacitance circuit 130. In the other cases, the control voltage Vt is applied to the second variable capacitance circuit 130. As a result of this control, a high-frequency variable range is divided into two variable ranges, one based on upper frequencies and the other based on lower frequencies. This enables suppression of a frequency sensitivity without narrowing the high-frequency variable range.

Abstract: A PLL circuit has a phase comparator to receive an input signal and a feedback signal, a charge pump controlled by an output of the phase comparator, a lowpass filter part to receive an output of the charge pump, a current controlled oscillator controlled by an output of the lowpass filter part, and a frequency divider to frequency-divide an output of the current controlled oscillator and to output the feedback signal. The lowpass filter part has an amplifier to receive the output of the charge pump and a reference voltage, and a circuit part including capacitors and resistors to receive the output of the charge pump and an output of the amplifier.

Abstract: An All Digital PLL (ADPLL) and oscillation signal generation method using the ADPLL is provided for generating a spur-free oscillation signal by improving the frequency resolution of the ADPLL.

Abstract: A phase locked loop circuit is provided comprising a voltage controlled oscillator (VCO), frequency divider, phase frequency detector (PFD), charge pump, waveform generator, loop filter, switching circuit, and lock detector. The VCO generates an oscillation signal. The frequency divider multiplies the frequency of the oscillation signal. The PFD compares the frequency-multiplied oscillation signal and an externally inputted reference signal to generate an error signal. The charge pump generates a signal according to the error signal. The loop filter controls the VCO to modulate the frequency of the oscillation signal and generate a spread spectrum clock based on the signal of the charge pump or waveform generator. The lock detector controls the switching circuit to selectively connect the charge pump to the loop filter during a non-lock state and the waveform generator to the loop filter during a lock state.

Abstract: A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.

Abstract: Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.

Abstract: Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

Abstract: Provided is a frequency modulation circuit 1 for outputting a highly precise frequency-modulated signal regardless of variation in a characteristic of a VCO 15. A correction value calculation section 17 calculates a correction value Vt2 based on a voltage value (Vtx?Vt1) resulting from subtracting a control voltage Vt1, which is generated by a control voltage generation section 11, from a control voltage Vtx at which a sensitivity of the VCO 15 is maximized. A variable amplifier 18 amplifies the correction value Vt2. An addition section 13 outputs a control voltage Vt3, which results from adding the amplified correction value Vt2 to the control voltage Vt1, to the VCO 15 via a DAC 14.

Abstract: Methods, systems, and apparatus, including computer program products, are described for calibrating control loops, specifically phase-locked loops. In one aspect, an apparatus is provided that includes an oscillator model that generates a predicted phase based on an input, a first averaging submodule that generates an average predicted phase over a predetermined number of samples, and a first summing submodule that receives a first corrected phase error and generates a predicted repetitive phase disturbance using the first corrected phase error, the predicted phase, and the average predicted phase.

Abstract: A band selecting method applied to a voltage controlled oscillator (VCO) of a phase locked loop (PLL) and an associated method is provided. The band selecting method generates an open-loop control voltage according to a temperature signal; inputting the open-loop control voltage into the VCO; switching sequentially between a plurality of frequency bands of the VCO and generating a plurality of voltage controlled signals for the frequency bands; selecting a preferred voltage controlled signal and its corresponding frequency band as an operating band for the PLL.

Abstract: A phase locked loop is disclosed. One embodiment includes a phase comparator having two phase comparator inputs and a phase comparator output. A filter having a filter input and a filter output is provided, wherein the filter input is connected to the phase comparator output. A voltage controlled oscillator has a first oscillator input and an oscillator output. The first oscillator input is connected to the filter output and the oscillator output is connected to a first of the two phase comparator inputs. The oscillator has a second oscillator input. A coupling element is connected in parallel to the filter and arranged between the phase comparator output and the second oscillator input in such a way, that an output signal of the phase comparator is amplified and input to the second oscillator input.

Abstract: A frequency-locked clock generator includes a voltage-controlled oscillator (VCO), a frequency-to-current converter, a reference current source and a gain stage. The VCO generates an output signal. The frequency-to-current converter generates a converter current proportional to a frequency of the output signal. The reference current source generates a reference current. The gain stage generates a control signal based on a difference between the converter current and the reference current. The control signal is applied to the VCO to adjust the frequency of the output signal. Feedback forces the VCO to generate an output clock signal such that the corresponding current it produces (i.e., the converter current) is equal to the reference current. When in lock, the frequency of the output signal is determined by a time constant (or equivalent time constant) of the frequency-locked clock generator.

Abstract: A voltage-controlled oscillator (VCO) comprising a first circuit, a second circuit, a comparator circuit, and a control unit. The first circuit can determine an output common mode voltage associated with an output of the VCO. The second circuit can generate an upper control voltage limit and a lower control voltage limit associated with a control voltage received by the VCO based, at least in part, on the output common mode voltage. The comparator circuit can compare the control voltage to the upper and lower control voltage limits. The control unit can determine whether to change a switched capacitance associated with the VCO based, at least in part, on whether the control voltage is outside the upper and lower control voltage limits, thereby maintaining an optimal region of operation for the control voltage.

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract: A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.

Abstract: A fast lock circuit for phase lock loop comprising a frequency detector, a phase frequency detector, a logic unit and a corresponding charge pump for the frequency and the phase frequency detectors. Embodiments of the present invention use the logic unit to relay signals from the phase frequency detector circuit to the charge pump when the PLL is in lock. The logic circuit relay signals from the frequency detector circuit before the PLL is in lock. As a result, a constant current is supplied to a large loop filter capacitor before lock. In one embodiment, additional logic circuit may be used to maximize the output current. Therefore, using the logic circuit to supply constant current charges the large loop filter capacitor continuously and avoids a slow down in charging the large loop filter. Accordingly, current is no longer wasted and the lock time is improved.

Abstract: Methods and apparatus are provided for calibrating a voltage controlled oscillator, such as an N-stage voltage controlled ring oscillator. The voltage controlled oscillator comprises a power supply input and at least one gate delay element and has a frequency that is a function of a delay of the gate delay element and a voltage applied to the power supply input. A voltage controlled oscillator is calibrated by varying an output voltage of a programmable voltage source through a range of values; applying the output voltage to the power supply input of the voltage controlled oscillator; comparing an output clock frequency of the voltage controlled oscillator to a reference frequency clock for each of the output voltage values; and selecting a value of the output voltage that provides an approximate minimum frequency difference between the output clock frequency and the reference frequency clock.