Abstract: An apparatus for characterizing an operating parameter in an integrated circuit, in accordance with one embodiment of the present invention, includes a voltage potential module, a plurality of distribution systems and a plurality of ring oscillator modules. Each ring oscillator module is coupled to the voltage potential module by a respective distribution system. Each ring oscillator module generates an oscillator signal as a function of the voltage potential and a voltage drop caused by the respective distribution system. The characterization of the operating parameter may be extrapolated from the difference in the operating frequencies of the ring oscillator modules.

Abstract: A method and an apparatus to bias a charge pump in a phase locked loop (PLL) to compensate a voltage controlled oscillator (VCO) gain have been disclosed. One embodiment of the apparatus includes a PLL comprising a charge pump, the charge pump comprising an input and an output, and a bias circuit coupled to the input of the charge pump, the bias circuit comprising a sensor circuit to sense a temperature and at least one of a voltage and a process variation and a current reference circuit coupled to the sensor circuit.

Abstract: An integrated circuit comprises a first circuit that receives a clock signal. A first temperature sensor senses a first temperature. Non-volatile memory that communicates with the first temperature sensor outputs calibration data as a function of the first temperature. A semiconductor oscillator that communicates with the non-volatile memory and the first circuit generates the clock signal having a frequency that is related to the calibration data. A select input selects the frequency of the output signal as a function of an external passive component.

Abstract: An injection-locked frequency divider includes a selecting module for generating a control signal; a biasing module coupled to the selecting module, for receiving an original signal and generating a biasing signal according to the control signal; and an oscillating module coupled to the biasing module, for receiving the biasing signal to generate a target signal. A ratio exists between the frequency of the target signal and the frequency of the original signal.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: A tunable oscillator having a tuning voltage input includes an inductor, and first and second varactor pairs arranged with the inductor to generate a signal having a frequency responsive to a tuning voltage applied to the tuning voltage input, each of the varactor pairs having a bias voltage input that may be controlled independently of the other varactor pair. The first varactor pair may be biased such that its capacitance varies substantially linearly with the tuning voltage over a first portion of the tuning range, and the second varactor pair may be biased such that its capacitance varies substantially linearly with the tuning voltage over a second portion of the tuning range.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1–INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1–INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: A system comprising a voltage controlled oscillator is disclosed. The voltage controlled oscillator includes a single input, a power input, and an oscillation input. The oscillation input is coupled to a amplitude detection device, which in turn provides an indication of an amplitude of the output of the VCO to a threshold detect module. Based upon the threshold detected at the threshold detect module, a threshold indicator is provided to a voltage supply module. The voltage supply powering the voltage controlled oscillator is varied, based upon a value of the threshold indicator.

Abstract: An oscillator circuit for a semiconductor device is disclosed which can generate internal clocks having a stable period regardless of variations of a process of transistors and resistors, a power voltage and a temperature, by controlling an oscillator unit by separating a gate voltage and a reference voltage, and which can normally operate chip functions according to the stable internal clocks without suffering from large variations by external factors.

Abstract: A circuit arrangement for generating a reference current and also an oscillator circuit having the circuit arrangement are disclosed the arrangement includes a capacitance connected to an input of a voltage-controlled current source. Two amplifiers having different drive capabilities, between which a switching can be effected, are provided to drive the capacitance. An LC oscillator can be fed with the reference current in a current-controlled manner and at the same time in a particularly low-noise manner.

Abstract: A circuit for varying an amplitude of an oscillation signal comprises an oscillator, signal processing circuitry, a first feedback circuit, and a second feedback circuit. The oscillator generates the oscillation signal and has a control input to vary the amplitude of the oscillation signal. The signal processing circuitry processes the oscillation signal. The first feedback circuit is configured to control the control input of the oscillator by comparing a reference value and an input amplitude of an input of the signal processing circuitry. The second feedback circuit generates the reference value by comparing an output amplitude of an output of the signal processing circuitry and a predetermined value.

Abstract: A logic system with adaptive supply voltage control comprising a logic circuit clocked by a clock signal from a clock generating circuit and a voltage conversion circuit for generating a dynamically regulated supply voltage for powering the logic circuit. A critical path delay of the logic circuit is designed to be equal to or shorter than a period of the clock signal. The voltage conversion circuit dynamically regulates the supply voltage of the logic circuit based on a bias voltage of the clock generating circuit. According to the invention, the power consumption is effectively minimized while ensuring the logic circuit to function correctly throughout all conditions.

Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.

Abstract: A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.

Abstract: A voltage-controlled oscillator circuit connected to supply and reference voltage for radio frequency operation is disclosed. The circuit comprises at least one inductor and at least one varactor connected in parallel with the at least one inductor. The circuit also comprises a pair of p-channel MOS transistors connected across the at least one varactor, each p-channel MOS transistor having source, drain, and gate terminals, wherein the drain terminal of the first of the pair of p-channel MOS transistors is connected to the gate terminal of the second of the pair of p-channel MOS transistors and the drain terminal of second of the pair of MOS transistors being connected to the gate terminal of the first of the pair of MOS transistors.

Abstract: A bipolar transistor (Tr) in an oscillator stage of a tuner is provided with a diode (D10) in series with a resistor (R11) coupled between the base of the transistor (Tr) and the reference voltage to which the emitter of the transistor (Tr) is coupled. The diode (D10) allows a decreased resistor (R11) value which causes the supply voltage ripple (Vr1) on the collector originating from the base to decrease so as to better compensate the supply ripple (Vr2) on the collector directly originating from the supply voltage (Vs.).

Abstract: A first current flowing through a first resistance is determined by a series connection between a first resistance and a transistor which is short circuited between the gate and the drain. Further, a second current flowing through a second resistance is determined by a series connection between a resistance and two or more transistors each having a short circuit between the gate and the drain. By drawing the second current from below the first resistance, a current fed through a reference transistor is established to be equal to (the first current)?(the second current). The second current starts flowing when the source voltage is equal to or greater than the summed values of the voltage drops between the gate and the source of the two or more transistors. Therefore, the second current becomes zero when the source voltage is lower than a predetermined value.

Abstract: Methods to achieve low power consumption, high output amplitude and an improved high frequency stability, and high speed for voltage-controlled oscillators are disclosed These methods includes to provide a current mirror, a power supply voltage Vdd, two single-ended outputs, a lower layer of gain providing structure comprising cross-coupled transistors, an upper layer of gain providing structure, a control voltage, a pair of capacitors to block a DC-connection to the gates of said cross-coupled transistors, a pair of resistors, and an LC-tank. Important steps of these methods include to set the time instances when said transistors of lower layer of gain providing structure open and close, to shut-down the transistors of lower layer of gain providing structure as soon as the energy required to keep the oscillations in said LC-tank is secured, to add additional gain in the amplification loop; and to pump-out charges of the channels of said transistors of said lower layer gain providing structure.

Abstract: A differential negative resistance source that provides negative resistance to a differential resonator of a differential VCO. The differential negative resistance source includes first and second active devices, each having first and second current terminals and a control terminal, first and second current sinks, each coupled to a corresponding one of the second current terminals of the first and second active devices, and at least one capacitive device coupled between the second terminals of the first and second active devices. The capacitive device and the separate current sinks form a capacitive degeneration circuit that operates to reduce or otherwise eliminate net differential capacitance at the output of the differential negative resistance source. The capacitive degeneration offsets extra capacitance, which enables an increase of the maximum operating frequency for a given process, and which enables the VCO to be less sensitive to operating conditions.

Abstract: The frequency changes in a bang-bang PLL that are generated using a digital phase detector's up/down signal are initially set to produce a faster pull-in rate and then reduced to produce a slower pull-in rate. The faster pull-in involves relatively large frequency changes and the slower pull-in rate involves smaller frequency changes. The changes in frequency of a bang-bang PLL can be implemented using a step size controller that includes timing control logic and step size logic. The function of the timing control logic is to control the timing of step size changes. The function of the step size logic is to set the step size of the frequency changes that are made by the VCO in response to the pd_up/down signal that is delivered directly to the VCO from the digital phase detector.

Abstract: An oscillating circuit having a noise reduction circuit is disclosed. The noise reduction circuit is coupled to the current source for the oscillating circuit. The noise reduction circuit reduces a bias noise component from a bias current, and a supply noise component from a supply current. The noise reduction circuit is coupled to the current source at a gate and a supply for the current source. The noise reduction circuit includes a filter coupled to the gate of the current source that reduces the bias noise component. The noise reduction circuit also includes a degeneration circuit coupled to the supply of the current source that reduces the supply noise component. The current source generates an input signal to control the oscillating circuit with reduced noise.

Abstract: Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

Abstract: An oscillator circuit includes a crystal oscillating circuit for generating a clock signal using a crystal resonator, an RC oscillating circuit for generating the clock signal using an RC circuit, a control signal generation circuit for bringing one of terminals for the external component to a ground potential in response to input of a reset signal, changeover switches for connecting the crystal oscillating circuit to the crystal resonator in parallel upon receipt of a first signal and connecting the RC oscillating circuit to a resistive element in the RC circuit in response to a second signal, and a selection signal generation circuit connected to the other terminal of the external component upon receipt of the reset signal, for transmitting the first signal to the changeover switches when a current flowing through the external component is smaller than a predetermined value and transmitting the second signal to the changeover switches when the current is equal to or more than the predetermined value.

Abstract: A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output frequency. An active resistor is in parallel with the ring oscillator. The active resistor has a resistor and an n-channel transistor in series between the oscillator-power node and ground. The n-channel transistor has a fixed bias voltage on its gate and is non-linear. The non-linear effective resistance of the n-channel transistor improves overall linearity of the ring oscillator. The parallel effective resistance of the active resistor lowers overall effective resistance of the ring oscillator.

Abstract: A voltage controlled oscillator, such as a VCXO (Voltage Controlled Crystal Oscillator), for generating a desired reference frequency in a wireless terminal with a reduced start-up time is described herein. According to the present invention, the VCXO comprises an oscillator that generates the desired reference frequency based on a variable voltage applied to the oscillator by a voltage controller. In addition, the VCXO includes a start-up controller that applies a bias voltage to an oscillator input node to reduce a capacitance associated with the oscillator, and therefore, to reduce the start-up time without negatively impacting the DC current consumption or the tuning range of the VCXO.

Abstract: A multi-loop oscillator which can control variation of an oscillating frequency of a ring oscillator according to variation of a supply voltage is disclosed comprising: first to Nth delay loops, wherein oscillation signal having a predetermined period is generated by selecting one of first to Nth delay loops according to potential variation of a supply voltage. Herein, the multi-loop oscillator further comprises a loop selection section for selecting one loop from among the first to the Nth delay loops, according to potential variation of the supply voltage. Further, the multi-loop oscillator further comprises a supply voltage detection circuit section for detecting variation of the supply voltage, and the supply voltage detection circuit section controls an operation of the loop selection section. In the multi-loop oscillator, an oscillation frequency of the ring oscillator can be adjusted.

Abstract: Provided is a quadrature voltage controlled oscillator capable of varying a phase difference between an in-phase output signal and a quadrature output signal. The quadrature voltage controlled oscillator comprises a first voltage controlled oscillator, a second voltage controlled oscillator, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The first voltage controlled oscillator generates a first output and a second output. The second voltage controlled oscillator generates a third output and a fourth output. The first output is a positive in-phase signal, and the second output is a negative in-phase signal. The third output is a positive quadrature signal, and the fourth output is a negative quadrature signal. The first amplifier is controlled by a first current and drives the first output and the second output in response to the third output and the fourth output.

Abstract: A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier (213, 215) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) (300) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell (100) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.

Abstract: A gain controlled voltage controlled oscillator. A current controlled oscillator is adapted to provide an output signal oscillating at a frequency controllable by controlling a current applied thereto. A first current source provides a first control current controllable by controlling a voltage applied thereto that has a predetermined range. A first current mirror is adapted to mirror the control current to the current controlled oscillator. A second current source is adapted to provide a second control current for mirroring to the current controlled oscillator by the first current mirror when the control voltage is in a low portion of the range.

Abstract: An oscillator includes a transistor, a first bias resistor connected between the base of the transistor and a power input terminal, and a second bias resistor connected between the base of the transistor and a control-voltage input terminal. When the control-voltage input terminal is grounded, the bias voltage at the base of the transistor is below a predetermined threshold, thus causing the oscillator to stop oscillation. When the control-voltage input terminal is open, the bias voltage at the base of the transistor is above the threshold, thus causing the oscillator to start oscillation.

Abstract: The invention relates to a method of automatically tuning a loop-filter of a phase locked loop. The loop-filter includes a capacitance at an output of a charge pump of the phase locked loop, and the charge pump provides current impulses to the loop-filter. In order to enable a simple tuning of the loop-filter, the method comprises adjusting the amplitude of the current impulses output by the charge pump essentially proportionally to the capacitance at the output of the charge pump. The invention relates equally to a phase locked loop comprising means for realizing this method and to a unit comprising such a phase locked loop.

Abstract: In some embodiments, a ring oscillator includes a plurality of delay cells coupled in series as a ring, and a replica cell coupled to the delay cells to provide at least one bias signal to the delay cells. The replica cell includes a differential transistor pair formed of a first transistor and a second transistor. The first transistor has a drain terminal and a gate terminal coupled to the drain terminal. The second transistor has a drain terminal and a gate terminal coupled to the drain terminal of the second transistor.

Abstract: In order to reduce the possibility of disturbing the drain/absorption balance of a charge pump in the PLL frequency synthesizer using the charge pump, when the output voltage and output current of the charge pump come close to their driving limits, the power supply voltage of a voltage-controlled oscillator is changed to cancel a change in input voltage of the voltage-controlled oscillator.

Abstract: The present invention relates to a sensor apparatus capable of outputting an accurate sensor signal irrespective of a variation of power supply voltage. In the sensor apparatus, when an A/D conversion circuit produces and outputs digital data, a switch circuit is placed into a first switching condition so that a constant voltage is applied from a constant-voltage circuit to an oscillation circuit, and a stabilized oscillation frequency is outputted from the oscillation circuit to the A/D conversion circuit. Thus, even if a power supply voltage varies, the A/D conversion circuit carries out sampling processing on analog data on the basis of the stabilized oscillation frequency from the oscillation circuit to produce and output the digital data.

Abstract: An oscillation signal that is provided from an inverter-type oscillation circuit 4 is input to an output driving circuit 5. In the output driving circuit 5, a control circuit 53 controls a voltage control circuit 52 and a buffer circuit 51 in accordance with control data written in a memory circuit 54, to generate a clock signal with control data amplitude, duty ratio, rising/falling characteristics of an output waveform in accordance with the control data. The output driving circuit 5 is configured with a plurality of voltage control circuits and a plurality of buffer circuits to allow clock signals, each having different waveform characteristics, to be provided from a plurality of output terminals.

Abstract: An apparatus and method are provided for operating a processor core. This may include a first circuit to operate at a frequency that is dependent on a power supply voltage. A frequency control circuit may be provided to control a frequency of the first circuit by directing a voltage regulator to increase or decrease the power supply voltage.

Abstract: A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.

Abstract: A voltage controlled LC resonance oscillation circuit has a plurality of capacitive elements connected to an output node. These capacitive elements are applied with voltages at opposing terminals for selecting an oscillating frequency band, so that the oscillating frequency band can be changed step by step in accordance with the selection voltage. The capacitive elements include at least one variable capacitive element such as a MOS capacitor, the capacitance of which is varied in accordance with a voltage applied thereto. The MOS capacitor is similar in structure to a MOS transistor. The variable capacitive element can be supplied at a terminal opposite to the output node with a voltage from a variable voltage source, for example, in place of the selection voltage. The voltage controlled LC resonance oscillation circuit can measure the output amplitude and oscillating frequency without affecting the characteristics thereof, and reduce the parasitic capacitance.

Abstract: Oscillator circuitry on an integrated circuit automatically detects the presence or absence of an external resistor which is used to bias and set the frequency of an internal resistor-capacitor (RC) oscillator. If the resistor is present, the RC oscillator begins to oscillate to generate an oscillator clock. The presence of the oscillator clock is detected, and the RC oscillator continues to generate the oscillator clock. If the resistor is not present, the RC oscillator does not begin to oscillate. The absence of the oscillator clock is detected, and the oscillator circuitry automatically re-configures itself to generate the oscillator clock from an internal crystal oscillator circuit employing an external crystal.

Abstract: A CR oscillation circuit includes an oscillation unit having first through third invertion circuits connected in series between a first node and a second node, a capacitance element provided between the first node and an output terminal of the second inverting circuit, and a switch part for electrically connecting the first and second nodes according to a level of a control voltage; a constant current unit for allowing a constant current to flow according to a resistance value of an externally-provided resistive element to thereby supply a constant voltage; and a level conversion unit for converting a level of the constant voltage to thereby produce the control voltage.

Abstract: A circuit and method are disclosed for controlling current dissipated by an oscillator circuit. The circuit includes a current source adapted to source current to or sink current from the oscillator circuit. A control circuit is adapted to count a predetermined period of time following the occurrence of an event, such as completion of a power-up operation. An output of the control circuit, having a value indicative of whether the predetermined period of time has elapsed, is coupled to a control input of the current source. In this way, the output of the control circuit sets a current level sourced to or sunk from the oscillator circuit by the current source.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A voltage controlled oscillator generates an output signal whose frequency varies as a first function of a control voltage applied to a control terminal. The voltage controlled oscillator has a wide range of frequency of operation. A gain adjust circuit adjusts the gain of the voltage controlled oscillator such that the first function varies as a second function of the gain. In a preferred embodiment the gain adjust circuit includes a variable impedance that may be external or integrated onto a common chip with the oscillator core.

Abstract: A voltage-controlled oscillator (“VCO”) structure includes a plurality of VCO circuits, each having a different nominal operating frequency range. Power consumption of the VCO structure is regulated by selective activation/deactivation of the individual VCO circuits. In a preferred embodiment, only one of the VCO circuits is active at any given time. The active VCO can be selected to satisfy the requirements of the particular application and/or to compensate for semiconductor manufacturing process variations.

Abstract: A voltage-controlled oscillator including an active oscillator circuit, an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator. Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit. To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors. The resistors can be configured in several different ways so that the voltage-controlled oscillator can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

Abstract: Five circuit topologies of Voltage-Controlled Oscillators with Single Inductor (VCO-1L) are proposed. They offer lower power consumption, higher output amplitude, broader tuning range, cleaner s-rum and higher frequency stability seen as lower phase-noise. Most of the achievements are based on the development of active pull-down control circuitries of the timing and active charge dissipation in the transistors. The applications of the present invention are of critical importance for wireless communication systems not allowing any limitations in the frequency range. Among them are base stations and mobile terminals mobile phones, GSM, PCS/DCS, W-CDMA etc., as well BlueTooth, Wireless LAN, Automotive and ISM band etc. The advanced performance of the circuits is based on important architectural specifics and proven by simulation on advanced CMOS process.

Abstract: A compensation circuit for current control oscillator to correct the frequency curve of an oscillator includes a compensation circuit which has a plurality of P transistors and N transistors to improve stabilization of output frequency of the digital current control oscillator and to prevent the digital current control oscillator from occurring unlatching phenomenon in certain frequency zones.

Abstract: This invention relates to a crystal oscillation circuit that oscillates stably with a low power consumption. This crystal oscillation circuit comprises an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The sum of the absolute value of the threshold voltage of a first semiconductor switching element and the absolute value of the threshold voltage of a second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, when said inverting amplifier includes the first and second semiconductor switching elements.