Abstract: An integrated circuit with a voltage-controlled oscillator that provides an oscillation signal with an unmodulated frequency that remains constant in response to reception of a bias current having a constant magnitude and with a modulated frequency that varies in response to reception of a modulation voltage. A current-to-voltage (I:V) conversion stage converts a bias clamp current to a control voltage. A voltage-to-current (V:I) conversion stage receives the control voltage and an external modulation voltage signal and generates the control current for a current-controlled oscillator (ICO). The control voltage is based upon the threshold voltage of one of the semiconductor devices forming the I:V conversion stage and is used to drive the V:I conversion stage so long as the external modulation voltage signal is substantially zero.

Abstract: An oscillator circuit configured to generate an output signal having a frequency comprising a current source, a trim circuit, and one or more capacitors. The current source may be configured to generate a temperature independent current in response to a first adjustment signal. The trim circuit may be configured to generate the first adjustment signal. The one or more capacitors may be configured to charge to a controlled voltage using the temperature independent current. The controlled voltage may regulate a variation of the frequency of the output signal.

Abstract: Amplitude-adjustable oscillator. The oscillator includes a feedback loop to control the amplitude of an oscillator output signal. The feedback loop includes a pair of clamping transistors, wherein base terminals of the clamping transistors are coupled to an adjustable voltage signal to prevent saturation of the oscillator circuit. The feedback loop also includes a filter to monitor the current flowing through the clamping transistors. The feedback loop also includes an amplifier to compare an output of the clamping transistors to a reference signal, and a reference generator to set an operating bias for the oscillator.

Abstract: An adjustable voltage controlled oscillator has an input for receiving a voltage signal and an integrator coupled to the input for generating a ramp signal. The circuit also includes an adjustable current supply coupled to an output of the integrator for supplying an adjustable amount of current. A comparator compares the ramp signal with a predetermined voltage. The circuit further includes an output for generating a frequency output as a function of the comparison, wherein the circuit is calibratible by adjusting current generated by the adjustable current supply.

Abstract: A LC controllable oscillator (LCCO) according to the invention comprises a voltage-controlled oscillator (VCO) and a first voltage controlled current source (VCCS) of a first type for supplying a current to the VCO. The VCO is realized with a first pair of VCCS of the first type coupled with a second pair of VCCS of a second type and a LC resonator. The VCO generates a periodical oscillation frequency that is controllable by a control signal (V). The LCCO further comprises a replica scaled bias module (RSBM) supplied from the external voltage source. The RSBM is conceived to generate a control signal (BIAS CONTROL) for controlling the supplied current delivered by the first VCCS to the VCO.

Abstract: A control voltage is fed to an oscillation circuit from a control terminal, and a power supply voltage is fed thereto from a power supply terminal. An output circuit is provided between the oscillation circuit and an output terminal. The power supply terminal is connected to a feedback terminal through a DC separating capacitor and an amplifier. A signal leaking out to the power supply terminal from the oscillation circuit is fed to the amplifier through the DC separating capacitor. The amplifier amplifies the signal leaking out to the power supply terminal, and feeds the amplified signal to the feedback terminal as a feedback signal Loop.

Abstract: An electric potential of an epitaxial layer 2A provided under a bonding pad 5 to which a resonance circuit for a VCO is to be connected is fixed to a predetermined (Vcc) electric potential through a resistor 6 in a conventional floating state. Consequently, a speed of a change in the electric potential of the epitaxial layer 2A is increased and a value of a parasitic capacity is stabilized quickly. Consequently, a drift can be improved when a power supply is turned ON.

Abstract: A phase-locked loop configured to cause an output signal to tend toward a desired output frequency based on an applied reference signal. In a first configuration, the phase-locked loop includes a voltage controlled oscillator operatively coupled with a bias generator. The voltage controlled oscillator is configured to produce the output signal in response to a VCO current generated via application of a biasing signal from the bias generator. The VCO current produces a regulated VCO voltage within the voltage controlled oscillator, and the bias generator is configured so that the regulated bias generator voltage matches the regulated VCO voltage free of any direct coupling between the bias generator and the regulated VCO voltage.

Abstract: A voltage controlled oscillator comprises an oscillator connected between a power supply line and a low potential power supply voltage and having an output node for outputting an oscillation signal having a frequency changed in accordance with a voltage difference between the power supply line and the low potential power supply voltage. An nMOS transistor is connected at its drain to a high low potential power supply voltage and at its source connected to the power supply line of the oscillator. A gate electrode of the nMOS transistor is connected to receive a control signal so that a source voltage of the nMOS transistor is determined by a voltage of the control signal and is supplied to the power supply line of the oscillator, with the result that the oscillation frequency of the oscillator is controlled by the voltage of the control signal.

Abstract: In an improved charge pump bias generating circuit for a charge pump for a semiconductor integrated circuit device, the pump has a bias generator which has an input for receiving a pump enable signal. The bias generator generates a ramped bias signal in response to the pump enable signal. A voltage controlled oscillator has an input to receive the ramped bias signal and generates an oscillating signal having a frequency which is dependent upon the voltage of the ramped bias signal. As a result, the sudden turn on of the pump enable signal would cause a gradual turn on of the voltage controlled oscillator gradually turning on the clock output signal from the voltage oscillator, thereby reducing power surge in the circuit.

Abstract: This invention relates to a crystal oscillation circuit that oscillates stably with a low power consumption. This crystal oscillation circuit comprises an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The sum of the absolute value of the threshold voltage of a first semiconductor switching element and the absolute value of the threshold voltage of a second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, when said inverting amplifier includes the first and second semiconductor switching elements.

Abstract: A voltage controlled oscillator includes a first converter, a second converter and an oscillator. The first converter outputs a first current proportional to an input voltage. In this case, an increase rate of the first current is decreased as the input voltage is increased. The second converter outputs a second current proportional to the input voltage. An increase rate of the second current is increased as the input voltage is increased. The oscillator outputs an oscillation signal in response to a summation of the first current and the second current.

Abstract: A ring oscillator including a voltage-to-current converter for producing at least one control current from at least one control voltage and, a plurality of delay cells coupled to the converter, wherein at least one output of the one of the delay cells is coupled to the input of another of the delay cells, wherein the voltage-to-current converter produces a substantially linear output when the at least one control voltage is varied between zero volts and a rail supply voltage. Since the ring oscillator operates from a low voltage source, it can be used in applications where power supply (e.g., battery size) is small (e.g., pagers, cellular phone applications).

Abstract: A circuit for conditioning an input control voltage signal that is used to drive an LC tank oscillator in a phase locked loop (PLL). The conditioning circuit includes a two-stage amplifier including a first stage amplifier connected to a second stage comprising an active cascode circuit, a diode-connected transistor and a resistor tied to a reference voltage (e.g. ground). The first stage amplifier receives a control voltage input signal, which would typically be produced at the output of a loop filter in a PLL, and produces a conditioned control voltage output signal at its output, which is connected to the drain of the diode-connected transistor. The purpose of the amplifier is to lower the impedance of the conditioned output signal, which is then used to drive the LC tank oscillator, wherein the series resistor acts both to lower the impedance and to act as the degenerating resistor for the diode-connected transistor.

Abstract: An oscillator with a buffer circuit comprises: an oscillation circuit having an oscillation transistor; and a buffer circuit which has an amplification transistor and amplifies an oscillation signal outputted from the oscillation circuit by the amplification transistor. A power supply voltage is applied to the collector of either the oscillation transistor or the amplification transistor, the emitter of the other transistor has a D.C. ground connection, and the emitter of the transistor to which the power supply voltage is applied is connected to the collector of the other transistor via a resistor.

Abstract: An improved resonant tunneling device (RTD) oscillator is provided by supplying electrical power to the RTD device 23 using a photocell 21 and a light source 25 such that essentially no spurious resonances are possible.

Abstract: A method of evaluating quality of a crystal unit, capable of performing quantitative measurement of an actual operation of a crystal unit which is to be oscillated in an actual oscillator to ensure an accurate quality evaluation, is provided which comprises the steps of increasing a DC input voltage of a crystal oscillator, said crystal oscillator having at least one AGC amplifier whose amplification rate varies depending on the DC input voltage and having a crystal unit connected thereto; measuring a maximum value of the DC input voltage at a start of oscillation of the crystal oscillator; and evaluating quality of the crystal unit by the measured maximum value.

Abstract: An oscillator circuit is provided with delay cells having supply voltage terminals and being interconnected in a ring for providing a first oscillator signal. If the delay cells have supply voltage terminals in common a second oscillator signal can derived from the respective common supply voltage terminals. The first ring oscillator signal, which is possibly available in quadrature, has a low frequency providing a low power consumption to the oscillator circuit. The two highly sinusoidal oscillator signals are generated simultaneously and have a frequency, whose ratio depends on the number of delay cells in the oscillator circuit. The oscillator circuit can be easily implemented on a limited chip area for application in transmitters/receivers operating in the GHz range.

Abstract: A controller oscillator provides a periodic output signal having first and second output level states. The oscillator is responsive to an applied saw tooth signal that varies between first and second voltages (Vlow,Vhigh). The oscillator is comprised of a comparator (82) the non-inverting input of which receives the saw tooth signal applied thereto to produce the periodic output signal at its output (86). A first voltage reference circuit (88, 90, and 92) generates the second voltage (Vhigh) that is applied to the inverting input of the comparator while the periodic output signal is at the first output level state and the input signal charges from the first voltage (Vlow) towards the second voltage. As the input signal becomes equal to the second voltage the output of the comparator switches to the second output level state and a second voltage reference (92,94, 96) provides the first voltage at the inverting input of the comparator.

Abstract: A frequency synthesizer has a voltage controlled oscillator comprising a voltage controlled capacitor having a first terminal and a second terminal. A positive control voltage is applied to the first terminal of the voltage controlled capacitor and a negative control voltage is applied to the second terminal of the voltage controlled capacitor, causing the varactor to operate in a reverse biased state. A circuit for generating a negative control voltage is provided in a phase-locked loop circuit. The circuit includes a negative DC generator for generating a negative DC voltage from an AC signal, and a programmable variable attenuator for selectably attenuating the negative control voltage.

Abstract: A communications device, such as a one-way pager, comprises a receiver having a frequency down-conversion means for frequency converting an input signal using a local oscillator signal generated by a signal generating means, which may comprise a frequency synthesizer. The signal generating means (20) comprises a voltage controlled oscillator (VCO) (50) including an oscillator transistor (68) coupled to dc voltage source (54), frequency determining reactive elements coupled to the oscillator transistor (68) for determining the frequency to be generated, at least one of the reactive elements (80) being adjustable in response to an applied voltage and means (82,84) for phase modulating the oscillator transistor (68) in an opposite sense to that caused by voltage perturbations due to noise in the dc voltage supplied by the dc voltage source (54).

Abstract: A differential VCO includes a ring oscillator with a plurality of differential buffers connected in a ring, a bias circuit including a replica circuit of the differential buffers, and a differential gain increasing circuit for increasing differential gain of the differential buffers. Even when the differential gain of the differential buffer lowers as a result of obtaining a clock signal of higher frequency, the ring oscillator oscillates smooth.

Abstract: A frequency synthesizer has a voltage controlled oscillator comprising a voltage controlled capacitor having a first terminal and a second terminal. A positive control voltage is applied to the first terminal of the voltage controlled capacitor and a negative control voltage is applied to the second terminal of the voltage controlled capacitor, causing the varactor to operate in a reverse biased state. A circuit for generating a negative control voltage is provided in a phase-locked loop circuit. The circuit includes a negative DC generator for generating a negative DC voltage from an AC signal, and a programmable variable attenuator for selectably attenuating the negative control voltage.

Abstract: A dual band VCO selects between the oscillator output frequencies by switching the resonant circuit elements in the active circuit. For each output frequency selected, the oscillator produces a single frequency signal and additional energy in the form of phase noise. This phase noise may be from sideband noise produced by modulation of the single frequency or produced by the active device in the oscillator as flicker noise, or the noise figure of the active device under large signal conditions or the filtering effect or the resonant circuit. Phase noise is reduced by shifting the bias point for the active device to the level where phase noise is minimum for each output frequency. At the time the output frequency is selectively switched, the bias to the active device is selectively switched to an optimum bias level for minimum phase noise for each respective selected frequency.

Abstract: An low-power consumption integrated ring oscillator capable of stable operation throughout a wide voltage range without undergoing a large frequency change includes a first constant voltage generating circuit having an enhancement mode P-MOS transistor and a depletion mode N-MOS transistor and a second constant voltage generating circuit having a depletion mode N-MOS transistor and an enhancement mode N-MOS transistor. A first constant voltage generated by the first constant voltage circuit is applied to a gate electrode of a P-MOS transistor of transmission gates connected between respective cascaded inverters of the ring oscillator. A second constant voltage generated by the second constant voltage generating circuit is connected to the gate electrode of an N-MOS transistor of the transmission gates. By this construction, current consumption is reduced and battery lifetime can be increased. The boosting circuit for writing and erasing an EEPROM circuit may be formed with the low power ring oscillator.

Abstract: An oscillator having a tank circuit, an amplifier circuit and a switching circuit. The switching circuit switches the oscillator between a normal power consumption mode and a lower power consumption mode. The amplifier circuit includes an emitter biased transistor. The switching circuit switches between power consumption modes by switching between two selected voltages at the base of the transistor. When in the lower power consumption mode, the oscillator has sufficient current to sustain oscillation but insufficient current to meet the phase noise requirements for good fidelity and high data rates.

Abstract: A low power clock oscillator circuit for driving microprocessors and other digital circuits is provided. The clock oscillator includes a resonant network for providing a sinusoidal waveform at a predetermined frequency. A first amplifier for amplifying the sinusoidal input waveform provides an output to a second amplifier. The second amplifier converts the amplified sinusoidal waveform to a continuous pulse output having a level-shifted voltage level greater than the amplitude of the sinusoidal waveform. The first amplifier is powered from a power source having a voltage level that is less than the power source that powers the second amplifier. Additionally, the second amplifier includes an enable input for disabling the continuous pulse output to permit decreased power operation with fast restart capability.

Abstract: The present invention comprises a CMOS voltage controlled oscillator (VCO) circuit for operation at frequencies of 1 GHz and above. The circuit of the present invention includes a voltage-to-current converter circuit for receiving a VCO input, a replica circuit coupled to the voltage-to-current converter circuit, and a first and second VCO cell coupled to the replica circuit. The first and second VCO cells are also coupled to one another. The circuit of the present invention also includes a VCO output for transmitting a VCO output signal. A first current source is coupled to the first VCO cell to transmit a first current from a power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell.

Abstract: A ring oscillator has first inverters and second inverters connected in such a manner as to form a loop; the first inverters are powered through a current controller controlling the first inverters in such a manner as to decelerate the logical operation when the power voltage is increased in magnitude; the second inverters are directly powered with the power voltages so that each second inverter accelerates the logical operation when the power voltage is increased in magnitude; and the second inverters cancel the increment of the pulse period introduced by the first inverters due to increase of the power voltage for keeping the pulse period constant.

Abstract: A multiple frequency shifting oscillator that will provide a plurality of frequencies dependent upon a contents of an input shifting signal an input shifting signal is disclosed. The multiple frequency shifting oscillator has an amplifier with first input, a second input, which is coupled to a ground reference potential and an output. The multiple frequency shifting oscillator has a first impedance that is coupled between the first input of the amplifier and the ground reference potential, a second impedance that is coupled between the output of the amplifier and the ground reference potential, and a third impedance coupled between the output and the input of the amplifier. The multiple frequency shifting oscillator has a plurality of frequency shifting impedances that when selected will be coupled to the first impedance so as to shift the frequency of the multiple frequency shifting oscillator.

Abstract: With a VCO 1 which constitutes the voltage controlled oscillator according to the present invention, since NMOS transistors N11, N12 and N13 are provided in each of inverter circuits 11, 12 and 13, the oscillating frequency band can be divided into three sub ranges. As a result, even when the VCO gain effected by a control signal VCN is reduced, a wide frequency band is assured, thereby making it possible to easily support the clock frequency required by the system into which the VCO 1 is to be incorporated.

Abstract: A ring oscillator generates a pulse signal having a frequency determined in response to a level change in the source voltage.

Abstract: A crystal oscillation circuit that oscillates stably with a low power consumption includes an inverting amplifier, a crystal oscillator, and a feedback circuit that inverts the phase of an output from this inverting amplifier and feeds it back as an input. The inverting amplifying includes first and second semiconductor switching elements. The sum of the absolute value of the threshold voltage of the first semiconductor switching element and the absolute value of the threshold voltage of the second semiconductor switching element is set to be greater than or equal to the absolute value of the potential difference between first and second potentials, in order to prevent the first and second semiconductor switching elements from being on simultaneously.

Abstract: Signal-controlled oscillator structures are provided that are substantially insensitive to temperature, supply voltages and fabrication processes. They include a plurality of time-delay stages that are serially connected in a closed feedback ring and each of the stages includes an amplifier, at least one capacitor and at least one signal-controlled impedance element that couples the capacitor to the amplifier. Accordingly, the frequency of the oscillator is a function of a control signal applied to the impedance elements of the stages. In an oscillator embodiment, each of the amplifiers is a differential pair of transistors, the capacitor comprises first and second capacitors and the signal-controlled impedance element comprises first and second coupling transistors that each couples a respective one of the capacitors to a different side of the differential output.

Abstract: There is disclosed an oscillator circuit comprising the first load capacitor with one electrode there of being connected with an input side of a CMOS inverter within a quartz oscillator circuit, and the second load capacitor with one electrode there of being connected with the output side of the inverter, wherein the inverter is coupled to a lower potential side via a current-limiting device, and the other electrodes of the first and second load capacitors are coupled to a lower potential side via the above-described current-limiting device. Thus, variations in the power-supply voltages synchronized with oscillation are reduced with realization of lower current consumption.

Abstract: A frequency-adjustable direct current biasing circuit is disclosed for providing a DC bias voltage or a DC connection to ground for an RF or microwave circuit without substantially affecting the RF or microwave signal of the circuit. The biasing circuit includes a transmission line having a first portion for connection to the RF circuit and a second portion connected to a low-impedance-to-ground structure, such as a bypass capacitor or a DC path to ground. The electrical length between the first and second portions is about 90 degrees. The biasing circuit further includes an open ended tuning stub coupled to the transmission line that has a length that is adjustable. By adjusting the length of the tuning stub, the biasing or grounding circuit can provide better isolation for RF energies at different selected frequencies. Also disclosed herein is a dielectric resonator oscillator (DRO) that uses the frequency-adjustable biasing circuit.

Abstract: A CMOS voltage controlled oscillator (VCO) having an improved voltage-to-current converter and an active MOS load operating in the triode region to provide improved performance characteristics including a small differential logic swing and a high frequency output. The voltage-to-current converter of the CMOS VCO comprises a pair of MOS transistors, one of which has an aspect ratio (W.sub.P /L.sub.P) and the other of which has an aspect ratio (W.sub.P /L.sub.P)/n, wherein 1<n<4. This configuration causes a third MOS transistor in the voltage-to-current converter to operate exclusively in the triode region. The CMOS VCO also includes an ICO portion having a plurality of delay stages connected in a ring configuration. Each of the delay stages comprises a pair of input MOS transistors and a pair of load MOS transistors. In accordance with the invention, the voltage-to-current converter causes each of the load MOS transistors to operate in the triode region.

Abstract: A power-on reset circuit comprises an oscillation circuit, an oscillation end detection circuit, a voltage stabilizer for generating a predetermined voltage (VDD2) from a power-supply voltage (VDD), and a start-up circuit. The power-on reset circuit further comprises a latched circuit. While the power is rising, the latched circuit becomes of an initial state and outputs a signal for arranging the latched circuit to a power-on reset state. When a value of the VDD becomes more than the value of the VDD2, by which the VDD2 becomes of a stable state, the initial state of the latched circuit is canceled, while as the VDD becomes stable, the oscillation circuit starts the oscillation in order to arrange the latched circuit to a set state, thus outputting a signal for canceling the power-on reset state.

Abstract: An ultra-low power, fast start fuze oscillator contained in a fast moving projectile which contains a programmable projectile fuze. It is an RC oscillator which uses a low power comparator, three biasing resistors, a timing resistor and a timing capacitor to produce an output frequency as low as 8 kHz with a frequency error of less than .+-.0.1% over a -40.degree. C. to +60.degree. C. temperature range. At the same time, it is capable of surviving a high g environment (30,000 g to 60,000 g) in a reliable manner. Furthermore, the oscillator draws a very low amount of power, using a maximum of about 20 uA of current and has a start-up time limited to a maximum of 1.5 msec. An additional circuit can be connected to the positive supply voltage input of a lower current version of an RC oscillator to jump start the RC oscillator, thereby improving start-up time to 1.5 msec while reducing the current drain to 15 uA.

Abstract: A method and apparatus for biasing the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (PLL) (100) includes a bias circuit (114) providing a peak minimum/maximum voltage detector (202) tied to the control line (116) of the PLL (100). During operation, the detector (202) detects a minimum or maximum voltage on the VCO control line (116) as the bias control voltage (118) applied to the VCO (110) is varied. Detection of such a minimum or maximum voltage is equivalent to the detection of a minimum or a maximum frequency, which in turn equates to the detection of an optimal bias condition for noise.

Abstract: A voltage controlled oscillator (1) comprising a voltage controllable variable resonant circuit (2) having a control input (Vctrl), a positive feedback input (6) and a controllable variable frequency output (7). There is an amplifier (3) having an amplifier input coupled to the controllable variable frequency output (7). A positive feedback path (4) couples the amplifier (3) to the positive feedback input (6) and there is selectable load (5) in parallel with the positive feedback path (4) for selectively reducing the SideBand Noise Ratio.

Abstract: An oscillator, such as a ring oscillator, uses CMOS transistors. At least some of the transistors have forward biased, current limited source-tub junctions for lowering the threshold voltages of these transistors. This enables the oscillator to operate at very low supply voltages, and it may be used in an electronic timepiece powered by a single photovoltaic cell.

Abstract: A CMOS super high speed voltage controlled oscillator (VCO) circuit that operates at frequencies of at least 3 GHz. The VCO circuit of the present invention includes a replica circuit, a first VCO cell coupled to the replica circuit, and a second VCO cell coupled to the first VCO cell and the replica circuit. A VCO output for transmitting a VCO output signal is also included. A first current source is coupled to the first VCO cell to transmit a first current from the power supply to the first VCO cell. A second current source is coupled to the second VCO cell to transmit a second current from the power supply to the second VCO cell. The first VCO cell and the second VCO cell each have respective first and second source follower load transistors coupled to the replica circuit. In addition, the first and second VCO cells, the first and second current sources, and the replica circuit are all fabricated using n-channel MOS transistors.

Abstract: An oscillating circuit includes a low power inverting amplifier (10) having an input (208) and an output (209) and having a relatively high resistance d.c. biasing path (2) associated therewith. A relatively low resistance path (3) can be switched so as to couple the amplifier input (208) and output (209) together during a bias settling phase of the circuit. A detector (50) detects the voltage at either the amplifier input (208) or the output (209) and switches the relatively low resistance path (3) so that it does not couple the input (208) and output (209) together when the detected voltage reaches a level just before a required operating voltage level.

Abstract: An oscillator usable for a TDMA type wireless mobile communication device in which an average current at the communication terminal is decreased. The oscillator has a switching circuit or a timing circuit which controls an operating current of an amplifying element 8 for oscillation and reduces an average current in a TDMA operation without changing a voltage applied to a passive element constituting the oscillator. In particular, before initiating oscillation, elements in a negative impedance circuit are charged with a current of a value which does not cause the oscillation of the oscillator, and at the time of initiating the oscillation, a current capable of oscillating the oscillator is supplied to the negative impedance circuit.

Abstract: A system and method for regulating the voltage at an input node of a varying current demand circuit is provided. The input node may be a power supply node and the varying current demand circuit may be a controllable oscillator. In addition, a frequency synthesizer may be formed from a phase locked loop which includes the controllable oscillator and a voltage control circuit. The voltage control circuit may receive an input control signal that varies as the current demand of the controllable oscillator varies. In response to the input control signal, the voltage control circuit may provide a more stable voltage supply to the controllable oscillator even as the current demands of the oscillator vary widely. The input control signal may be generated by generating a signal from the loop path of the phase locked loop. The frequency synthesizer may be utilized in a data storage system data detection circuit, such as for example, a data detection circuit used for recovering data from an optical disk.

Abstract: A current controlled oscillator circuit comprising a "variable-ratio current mirror", for providing a variable output current that varies in response to process. The "variable-ratio current mirror" having a reference MOS transistor and a mirrored MOS transistor, and the reference MOS transistor has a greater predetermined channel length than the channel length of the mirrored MOS transistor. A second current mirror is coupled to the "variable-ratio current mirror" to provide a control current that decreases in response to an increase in the variable output current of the "variable-ratio current mirror." A multi-stage ring oscillator having a plurality of series-connected inverter stages is responsive to the control current of said second current mirror for controlling the frequency of oscillation of said multi-stage ring oscillator.

Abstract: The use of a control circuit (160) with either a programmable divider or divider(s) (190) and multiplexer (200) guarantees that, irrespective of the process variations, a voltage controlled oscillator has a low gain Vin-Fout characteristic in the desired frequency range. Low-gain voltage controlled oscillators are fundamental building blocks of low-jitter phase-locked loop (PLL) systems. The programmable divider/divider(s) (190) and multiplexer (200) are placed at an output of a current controlled oscillator(s) (180). A control circuit (160) defines the optimum current range(s) in the current controlled oscillator(s) (180). In the case of when a programmable divider is used, the control circuit (160) keeps changing the division ratio of the programmable divider until the PLL eventually achieves the "locked" state. When divider(s) and a multiplexer (200) are used, the control circuit (160) keeps changing the selected multiplexer input until the "locked" state has been achieved.

Abstract: An oscillator circuit, having an inverter with input and output terminals interconnected through a feedback resistance, operates in two modes. In a first mode, the input and output terminals are coupled to an external crystal resonator. In a second mode, an external clock signal is supplied to the input terminal. In the second mode, the input terminal is disconnected from the output terminal, and in addition, the output-drive capacity of the inverter is reduced, or the output terminal of the inverter is held at a fixed potential.

Abstract: A voltage controlled oscillator comprising: a ring of inverters comprised of an odd number of serially connected CMOS inverter stages, the inverter stages being connected between first and second oppositely poled power leads, a MOSFET having a source-drain circuit connected between one of the power leads and a first power rail, the other power lead being connected to a second power rail, apparatus for operating the MOSFET in saturation, and apparatus for applying a control voltage to the gate of the MOSFET, referenced to the second power lead, whereby the MOSFET operates as a nonlinear current conduction device having a characteristic such as to linearize the voltage-frequency characteristic of the combined MOSFET--ring oscillator combination.