Abstract: Systems, methods, and circuitries are provided for generating timing signals with a resonator-based open-loop oscillator circuitry. In one example, a system that generates a timing signal based on a target signal includes a plurality of oscillator units configured to generate a respective plurality of oscillator signals. Each oscillator unit includes a resonator that operates in an open-loop mode to generate a resonator signal having a resonator frequency. The resonator signal is used by core circuitry to generate a respective oscillator signal having a respective oscillator frequency. The resonator frequencies of the resonators in the plurality of oscillator units are different from one another. The system also includes a selector circuitry configured to select one of the plurality of oscillator units based on the target signal and provide a selected oscillator signal generated by the selected oscillator unit as the timing signal.

Abstract: A circuit and corresponding method for dynamic voltage frequency scaling (DVFS) on a chip employ a delay-locked loop (DLL)-based clocking architecture. The circuit comprises a DLL including a fixed delay line path, with a first insertion delay, and variable delay line path, with a second insertion delay, and a clock generator. The clock generator is configured to source a DLL input clock to the fixed and variable delay line paths at a start-up frequency prior to a run-time frequency. The start-up frequency is lower relative to a target frequency for the chip. The run-time frequency is configured based on DVFS, following release of the chip from reset. The chip is configured to be released from reset with the DLL locked at the start-up frequency, enabling the second insertion delay to match the first insertion delay with the DLL locked at the start-up frequency.

Abstract: The present invention provides a device and method for correcting error estimation of an analog-to-digital converter.

Abstract: A first aspect of the invention relates to an apparatus for mobile application, including a frequency spectrum generator for generating a frequency spectrum of radio waves at a current position of the apparatus and a classifier for classifying the frequency spectrum such that the frequency spectrum is assigned to one of at least two classes. A second aspect of the invention relates to a frequency spectrum generator with a tunable local oscillator, with a downmixer for downmixing a received antenna signal with the local oscillator signal for obtaining a downmixed signal, with a filter for filtering out a mirror-frequency portion in the downmixed signal, with a signal level detector for detecting a signal level of the downmixed signal at an intermediate frequency and with a control for sequentially controlling the local oscillator and the signal level detector to sample a frequency spectrum of the antenna signal.

Abstract: A method for reducing transmission interference is described. The method includes determining that an FM receiver is turned on. The method also includes determining that the FM receiver is tuned to an FM channel experiencing interference from an induction-based communication transmitter. The method further includes adjusting a transmit frequency of the induction-based communication transmitter by a temporary frequency shift.

Abstract: A high-frequency oscillator comprises a reference-frequency generator and a high-frequency generator. The reference-frequency generator generates a variable reference frequency and supplies it to the high-frequency generator. The high-frequency generator comprises a phase-locked loop and generates a high-frequency signal from the variable reference frequency. The phase-locked loop comprises at least one first mixer, a second mixer and several switches. The first mixer, the second mixer and the switches are connected in series. The mixers are connected into the phase-locked loop individually in a selective manner by means of the switches.

Abstract: Aspects of the disclosure provide a local oscillator (LO) circuit that includes a first phase locked loop (PLL) circuit and a second PLL. The first PLL circuit is configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency. The second PLL circuit is configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal.

Abstract: A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.

Abstract: A delay locked loop (DLL) circuit includes a first delay control unit configured to generate a first delay control signal in response to a first phase detection signal to control a delay amount of a first delay line and to output a first delay amount information signal, a second delay control unit configured to generate a second delay control signal in response to a second phase detection signal to control a delay amount of a second delay line and to output a second delay amount information signal, and to control the delay amount of the second delay line again in response to the first delay control signal and a half cycle information signal, a half cycle detecting unit configured to receive the first delay amount information signal and the second delay amount information signal to extract half cycle information of a reference clock signal, thereby generating the half cycle information signal, and a duty cycle correcting unit configured to combine an output clock signal from the first delay line and an output

Abstract: A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined.

Abstract: A system for reducing self interference in a mobile terminal is provided. In general, the system includes a receiver including downconversion circuitry that converts a received radio frequency (RF) signal to a downconverted signal using one or more local oscillator frequencies. The downconverted signal is processed by digital circuitry clocked by one or more clock signals to obtain information from the RF signal. The local oscillator frequencies are provided by a frequency synthesizer as a function of an output frequency signal of a phase lock loop. Divider circuitry operates to divide the output frequency signal of the phase lock loop to provide the clock signals.

Abstract: A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-?m CMOS technology, and shows 10?12 bit error rate up to speeds of 3 Gbps.

Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Abstract: A combined spread spectrum and fractional-N phase locked loop circuit comprises a chain of a reference clock divider, a phase-frequency detector, a charge pump with loop filter, a voltage controlled oscillator that provides multiple phase outputs, and a feedback loop from the multiple phase outputs of the voltage controlled oscillator to a feedback input of the phase-frequency detector. The feedback loop includes a phase selector, a feedback divider and a control block with an output controlling said phase selector to select a particular phase as an input to the feedback divider. The control block includes spread spectrum logic circuitry receiving an input from the output of the phase selector and providing a directional control output signal and a phase step control signal. The control block further includes fractional logic circuitry receiving an input from the output of the phase selector and providing a phase step control signal.

Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.

Abstract: A method and device are provided for producing mobile radio signals, which utilize a direct conversion receiver, at least one first and one second local oscillator and one regenerative divider for processing signals according to different mobile radio standards. For generating the intermediate frequency for transmission according to at least one of the mobile radio standards, a division by four in addition to a division by three of the oscillator frequency is also possible.

Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Abstract: An electrical circuit generates an oscillating signal that produces reduced electromagnetic interference by way of modulation of the frequency of the oscillating signal within a specified frequency range. A randomized signal generator creates a randomized signal, which is then used to drive a frequency range converter that is employed to produce a frequency modulation signal. The current state of the frequency modulation signal is based on the current state of the randomized signal, with the converter limiting the current state of the frequency modulation signal so that the oscillating signal will only operate within the specified frequency range. A variable frequency oscillator then generates the oscillating signal whose frequency is based on the current state of the frequency modulation signal.

Abstract: The present invention relates to an arrangement for phase locking of a Voltage Controlled Oscillator (VCO) to a selected frequency harmonic among a number of predetermined or available frequencies (harmonics), comprising a reference generator for generating a reference frequency, a phase lock loop (1; 101; 10; 4, 5, 6, 9) for producing an output signal in response to the input reference frequency, said phase lock loop comprising (enclosing) a phase defector (1), a loop filter (10), said VCO (5), adding means (4) and a power splitter (6). The arrangement also includes a sweep generator (9). It further comprises or is associated with storing means 82) for scoring information about, for each selectable or available frequency harmonic, a first (coarse) control voltage providing a VCO frequency output which is lower/higher than, and differs from the selected frequency (harmonic) by a given value (?f1).

Abstract: A method for extracting components from signals in an electronic sensor (50) having a sensing element (52). The sensing element (52) generates a first signal (60) and a second signal (62). The method comprises the steps of: receiving the first signal (60) from the sensing element (52), the first signal (60) having a frequency at an event; sampling the second signal (62) from the sensing element (52) based on the frequency of the event, the second signal (62) having a plurality of components, one of the plurality of components being a first component of interest (112, 114); generating a synchronized second signal (100) in a time domain, the second signal (62) having the plurality of components; generating complex data (110) in a frequency domain from the synchronized second signal (100) in the time domain; determining the first component of interest (112, 114) from the complex data (110); and normalizing the first component of interest (112, 114) using amplitude information from the first signal (60).

Abstract: A PLL circuit is described. The PLL circuit includes: a signal generator; and a spread spectrum modulator coupled to the signal generator, where the spread spectrum modulator receives a control voltage as an input and provides a spread spectrum control voltage to the signal generator in response to the control voltage. In one embodiment, the spread spectrum modulator includes at least one selector, where the at least one selector selects a plurality of voltage levels that correspond to a spread mode and percentage of spread for the spread spectrum modulator.

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: A phase noise measurement system including a low noise programmable synthesizer and a receiver/down converter is provided. The low noise synthesizer provides L-Band Signals which can selectively exhibit low noise close-in or low noise far out. The receiver down converter provides for absolute, additive, and down converted/direct/multiple phase noise measurement.

Abstract: A method and apparatus for compensating for the long term drift of an oscillator. Signals from hydrogen clouds are received and processed to generate an adjustment signal, which is used to adjust the frequency of the oscillator. The adjustment signal is derived from a frequency spectrum midpoint estimated from the signal strength of the received signals.

Abstract: A microwave frequency generator and method of generating a predetermined microwave signal. The invention comprises oscillator means to generate a determinable frequency signal and means responsive to the frequency signal received from the oscillator means to generate a predetermined Intermediate Frequency (IF) signal. The invention further includes means to generate a determinable ultrahigh frequency (UHF) signal, along with means responsive to the IF signal and to a UHF signal to generate a resultant frequency signal. Means responsive to the resultant frequency and to the predetermined frequency signal generated by the oscillator means are further provided to generate the desired predetermined microwave frequency signal.

Abstract: A phase lock acquisition control circuit for the local oscillator (LO) of a radar exciter. The control circuit includes a programmable logic array, a microsequencer and a counter employed as a divide-by-eight circuit which supplies a clock reference for the control circuit. The counter in turn is clocked by a crystal based oscillator also used as the reference for the exciter phase lock loop. The marker filter and zero beat detector provide frequency location information to the control circuit. The control circuit controls a ramp generator circuit which in turn can drive the phase lock loop VCO during acquisition.

Abstract: A frequency synthesizer using a fixed oscillator driving a comb line generator to generate a spectrum of comb lines, one of which is selected by a switched array of fixed-tuned, YIG passband filters. The selected comb line is combined in a mixer with a signal from a local oscillator, which, preferably, is a direct digital synthesizer. The output of the mixer is fed to another switched array of fixed-tuned YIG passband filters where only the desired sideband is selected and the comb line and the other sideband is filtered out. In various alternative embodiments, tunable YIG filters are substituted for each array. Some embodiments also use a reverse slope equalizer to break up the coherent energy in the comb line spectrum at the output of the comb line generator to allow RF amplification to be applied without saturating the amplifier.

Abstract: A multi-marker microwave sweep linearization system comprising a voltage controlled microwave oscillator utilizing an adaptive sweep control circuit is presented. The oscillator control voltage is to be adjusted as necessary to maintain a constant spacing between markers. To produce the markers, the output of the oscillator is mixed with the output at a comb generator having harmonics. The lower side bands generated as the oscillator sweeps past the comb frequencies generates a series of `chirps`, centered about each of the comb harmonics. It will be noted, that the frequency of the chirp passes through zero when the oscillator frequency is exactly equal to one of the comb harmonics. The marker is to be associated with a higher frequency in the chirp envelope to avoid phase uncertainties. This can be accomplished with a frequency-detector circuit which may comprise a retriggerable monostable multi-vibrator having a time constant equal to the period of the frequency to be detected.

Abstract: A signal receiving device is kept tuned by a tuning signal, which supplied to a tuning input of a tunable circuit in the signal receiving device. The tuning signal is supplied from a memory. The signal receiving device has an operating state and a calibrating state. The calibrating state serves to determine the tuning signal and to store it in the memory. In the calibrating state, a broadband signal source supplies a broadband signal to a band-pass filter. The band-pass filter is tuned to and passes a reference signal to the tunable circuit which provides the signal receiving device with selectivity in the operating state. The response of the tunable circuit to the reference signal is monitored and a tuning signal is selected for which it is measured that the tunable circuit is tuned to the reference signal which is passed by the band-pass filter.

Abstract: A scanning-superhetrodyne ESM receiver having a VCO for a local oscillator which is linearized and temperature compensated. A stable combline oscillator is used to generate known frequency signals which are frequency converted to an intermediate frequency (IF) using the local oscillator and frequency converter (mixer). The frequency of each combine signal is measured and a table of known voltage/frequency points is generated. The table is input to a Cubic Spline program which computes the coefficients for the best-fit third order polynomial for each pair of data points. When a particular local oscillator frequency is desired, the corresponding tune voltage is computed by solving the polynomial equation for the given frequency range. By repeating the calibration on a periodic, or an "as needed" basis, temperature compensation is achieved.

Abstract: A frequency synthesizer is described which operates over a wide frequency range at high resolution and variable step size without trading off between spurious frequency rejection and phase noise suppression. The synthesizer includes a magnetically-turned YIG oscillator which generates a desired output frequency from a received tuning signal. The output signal is fed back into a phase locked loop which generates the tuning signal. The phase locked loop includes a harmonic mixer for mixing the output signal with a reference frequency F.sub.2. The mixer receives a base frequency signal and a harmonic select signal resulting in the generation of the reference signal, F.sub.2. The mixed signal is input to a programmable divider, then to a phase detector which receives another reference signal, F.sub.1. The phase detector output is the tuning signal which is coupled to the YIG oscillator. Both reference frequencies, F.sub.1 and F.sub.2, are derived from a common base frequency.

Abstract: A frequency synthesized, microwave signal generator is disclosed that provides multiple channel frequency selection capability with rapid channel change time and low levels of spurious signals and noise. The generator uses a microwave harmonic phase locked loop to lock a microwave VCO to a programmable harmonic of a VHF reference crystal oscillator to provide coarse frequency control in steps equal to that reference frequency. The phase lock loop includes an offset mixer for injecting an offset signal frequency to achieve fine frequency control. A harmonic detection and counting scheme is used to rapidly sweep the harmonic loop and obtain phase lock at the desired harmonic.

Abstract: A low-noise frequency synthesizer comprises a low-noise oscillator, such as a crystal oscillator, a multiplier, a divider and a phase-locked loop and is adapted to provide an output signal which is a combination of the multiplied and divided frequency. Thus, a large number of frequencies are available as an output in small increments determined by the division ratio of the divider.

Abstract: The described embodiment of the present invention provides a technique for minimizing unwanted components in the output of a frequency synthesizer. The output signal of the frequency synthesizer is tapped and mixed with a selective reference control signal. The reference control signal is selected by a control logic so that, when mixed with the output signal of the frequency synthesizer, a signal is derived of constant frequency no matter what frequency the frequency synthesizer is set to provide. This constant frequency signal is provided to a power divider. One output of the power divider is provided to a phase shifter which shifts the signal 180 degrees. The other output of the power divider is provided to a high quality band pass filter tuned to the constant frequency. The output of the phase shifter and the high quality band pass filter are recombined, thus cancelling the constant signal while leaving remnants of the undesired frequency drift.

Abstract: A signal generating device and method of control thereof for producing a desired output frequency, the generator having coarse and fine tuning controls capable of producing frequency changes over a limited range, wherein the output of the device is combined in a mixing device with a multi-component reference signal produced from an oscillatory generator circuit, a beat signal is detected by processing circuitry as the frequency controls are adjusted and the values of the frequencies of the control signals occurring on such detection are stored, and using a look-up table or algorithm the value of a correction signal is determined which, when combined with the stored values, will cause the output frequency of the device to be adjusted to the desired value via the fine tuner.

Abstract: Non-inverting amplifier, with bandpass filter in regenerative feedback path, forms color reference oscillator in a color TV receiver. Phase shift circuit, responsive to an oscillator output, supplies signals to a first phase shifted signal amplifier, which shares a load with the non-inverting amplifier, and is subject to control by complementary outputs of a phase comparator functioning to compare the phase of an oscillator output with the phase of incoming color synchronizing bursts. A voltage comparator, responsive to the respective phase comparator outputs, is periodically enabled by field rate keying pulses. The voltage comparator output controls the charging or discharging of a capacitor during the keying intervals.

Abstract: A reference signal from a reference signal source is supplied to a frequency transformer and a side band signal generator. The frequency transformer is formed mainly by up-converters and produces a frequency m times as high as the frequency f.sub.s of the reference signal. The side band signal generator outputs signals of base and harmonic frequencies f.sub.s, 2f.sub.s, 3f.sub.s, . . . and nf.sub.s (where n is less than m) and produces less phase noise than does the frequency transformer. The outputs of the frequency transformer and the side band signal generator are frequency mixed by a frequency mixer, and one frequency component in the frequency-mixed output is selected by a variable filter.

Abstract: A multi-channel frequency synthesizer, including a crystal oscillator circuit that may be selectively operated to provide a reference signal at a selected reference frequency that is one of a given plural number of frequencies; an IF generator for processing the reference signal to provide an IF signal at a selected intermediate frequency that is one of a given plural number of submultiples of the selected reference frequency; a comb generator for processing the reference signal to provide a comb of signals separated from each other by the selected reference frequency; and a phase-locked loop.

Abstract: A wide band oscillator with phase lock loop is controlled by signals from an 40 MHz harmonics generator combined with the output of another phase lock loop controlled oscillator whose selectible outputs vary in MHz steps with a total range of 39 MHz. The phase lock loop of the wide band oscillator is additionally controlled by a d/a converter and by another phase lock loop controlled oscillator whose selectible outputs vary in one KHz steps. Each of these phase lock loops is digitally controlled from the input frequency selection and again therefrom via a digital-to-analog converter. The output of the wide band oscillator is combined with the output of a narrow band oscillator which may be FM modulated. Alternatively, an output amplifier for the combination difference frequency may be AM modulated.

Abstract: Synthesizer including a VCO-type oscillator covering the range from 300 to 610 MHz and driving a first mixer; a source of 80 MHz standard frequency, followed by a frequency multiplier and a tunable filter driving the first mixer; a second, sampling-type mixer driven on the one hand by the output of the first mixer and on the other hand by the standard frequency divided in a divider by 8. The output from the second mixer controls the frequency of the oscillator.Application to the production of a synthesizer with very high spectral purity.

Abstract: A microprocessor-controlled synthesizer has a low frequency section producing a first output frequency and a comb loop producing a second output frequency. The comb loop includes a multiplier which produces harmonics of 100 MHz one of which is selected and fed to a mixer in a phase-locked loop having a variable divider, the other input of the mixer being a VCO output frequency. At low values of the second output frequency, the phase detector locks to the difference output from the mixer, at higher values to the sum output. The output from the mixer is mixed in a second mixer with the output of a further VCO, and a second phase detector selects the sum output from the second mixer to cover the first half of each decade of MHz and selects the difference output to cover the second half of the decade.

Abstract: A piezo-electric crystal vibrating in several modes controls several frequencies generated by voltage controlled oscillators simultaneously. The output of each voltage controlled oscillator is fed to a summing amplifier which drives the crystal. The output of the crystal is fed to individual phase detectors; each phase detector is also supplied with the output of a voltage controlled oscillator and generates a voltage proportional to the phase difference between the voltage controlled oscillator and the crystal output for correcting the output frequency of each oscillator.

Abstract: A system is disclosed for synchronizing a free-swinging oscillator to a reference signal of a substantially lower frequency. A regulating circuit connects to the oscillator to control the frequency thereof. A quartz oscillator is provided for producing the reference signal. The reference signal is subsequently connected to a frequency multiplier and/or frequency divider, an amplifier and a pass band filter. An output signal from the pass band filter is fed to a harmonics mixer connected to the free-swinging oscillator and which produces a pattern of harmonics. A selective amplifier feeds an intermediate frequency obtained from the harmonics mixer to the regulator circuit. A filter also connected to the quartz oscillator produces harmonics which are also coupled to the regulating circuit. By phase or frequency comparison the regulating circuit adjusts the running frequency of the free-swinging oscillator.

Abstract: A comparator-discriminator is provided, suitable for use with a phaselock control system of a frequency synthesizer, to permit automatic tuning of a variable oscillator to a selected frequency lying within a frequency band for which a phaselock may occur. This system permits the frequency of the variable oscillator to lock-on to an arbitrary value in the range other than the preselected value, at which time the phaselock is broken by an injected signal, thereby permitting the shifting of the oscillator frequency to a value lying closer to the selected frequency value. Upon achievement of phaselock to the selected frequency, in a slightly more elaborate embodiment, the injected signal is inhibited and no further breaking of phaselock can occur.

Abstract: A frequency synthesizer including a phase-locked loop (PLL) is provided which does not use any variable frequency divider. The output of a reference frequency oscillator is applied to a phase comparator in the PLL through a monostable multivibrator. The oscillating frequency of a voltage controlled oscillator (VCO) in the PLL can be selected by controlling a bias DC voltage applied to a control element in the VCO. The output waves from said VCO are counted at a counter during a period of the reference frequency from the reference frequency oscillator of the PLL. The count operation is repeated at a predetermined time interval. After completion of each count operation, the number in the counter corresponding to the least digit column of the decimal number is discriminated to determine whether it is within a predetermined range or not. The range is determined correspondingly to a locking range of the PLL.

Abstract: Apparatus and method are provided to discriminate between true locking of a phase-locked loop on the main lobe of an information signal, and false locking on a side lobe thereof. The energy in the locked signal is sensed and compared with the signal energy at fixed frequency increments, preferably twice the bit clock rate frequency, above and below the lock frequency. A greater energy content at the increment frequencies than at the locked frequency indicates a false lock condition and is used to inhibit the loop from entering a locked mode.

Abstract: A phase locked oscillator provides an agile frequency signal source with low phase fluctuations for use in radar and communications systems wherein the phase fluctuations of a predetermined input signal are reduced by the phase locked oscillator by modulating the phase of a delayed feedback signal in response to the phase difference between the input signal and the output signal.

Abstract: A circuit for synchronizing a microwave oscillator with a reference source of known frequency. The synchronizing circuit includes a phase-lock loop which compares the output of a free-running, crystal-controlled, voltage-controlled oscillator with the output of a burst oscillator. The output of the burst oscillator has a comb spectrum comprising harmonics of the reference frequency and the phase-lock loop locks onto a selected one of the comb harmonics.

Abstract: A low noise discriminator circuit having particular utility for use in determining the spectral purity characteristics of an rf signal source and comprising, in addition to standard discriminator components, a down-locked reference signal source including a voltage-controlled signal generator for developing a reference signal and a corresponding train of signal pulses, a stabilizing voltage-controlled oscillator which responds to the discriminator error signal and generates a stabilizing signal having a frequency at least an order of magnitude greater than the frequency of the reference signal, and a sampling phase detector which samples the stabilizing signal at the signal pulse frequency and develops a control signal which is fed through a feed-back loop to stabilize the reference signal generator.