With Reference Oscillator Or Source Patents (Class 331/18)
  • Patent number: 9667237
    Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 30, 2017
    Assignee: MICROSEMI SEMICONDUCTOR ULC
    Inventors: Qu Gary Jin, Paul H. L. M. Schram, Krste Mitric, Cathy Zhang, Gabriel Rusaneanu, Wenbao Wang
  • Patent number: 9614557
    Abstract: A method and apparatus for phase adjustment of a RF transceiver is disclosed. Based on a first local oscillator signal and a second local oscillator signal, a beat signal that indicates the frequency and phase relationship between the first and second local oscillator signals can be generated. Using the beat signal, changing phase relationship between the first and second local oscillator signals can be cumulatively taken account for using phase averaging to allow quick restoration to observation of a previously observed channel.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Christopher Mayer, David J. McLaurin, Chris Angell
  • Patent number: 9565015
    Abstract: A signal reproduction circuit includes: an oscillator generating first clock and second clock having a same frequency but different phases; and a feedback circuit to control the oscillator in accordance with a phase relation and a frequency relation between input data and the first clock, wherein the feedback circuit includes: a frequency-phase detection circuit to compare a clock phase control signal and a clock phase detection signal and generate a frequency phase signal indicating the frequency relation between the input data and the first clock, a state detection circuit to detect a lock state in which falling edges or rising edges of the input data and the first clock synchronize and a frequency difference state in which frequencies of the input data and the first clock are different, and a selector to supply the frequency phase signal to the feedback loop only in the frequency difference state.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 9520886
    Abstract: A method for correcting long-term phase drift of a crystal oscillator in a numerically-controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base; delta-sigma modulating the phase error to generate a delta-sigma error bitstream; conditionally adding or subtracting an error correction step size from a phase increment value in each clock cycle based on the delta-sigma error bitstream, to create a modulated phase increment value; and adding the modulated phase increment value to a phase accumulator to generate an error-corrected output digital signal. The delta-sigma-based error correction method avoids the use of multipliers. The same delta-sigma error signal can be used in multiple numerically-controlled oscillators configured to different output frequency if driven by the same reference oscillator.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: December 13, 2016
    Assignee: Smart Energy Instruments Inc.
    Inventors: Donald Jeffrey Dionne, Brian Leonard William Howse, Jennifer Marie McCann
  • Patent number: 9473156
    Abstract: A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is selected with a desired settling time. A transfer function is generated based on the PLL transfer function that predicts the spurious components. A maximum level of the spurious components produced in the PLL is determined based on the maximum frequency step. If the maximum level of the spurious frequency components produced is too large, the order variable is incremented and the PLL transfer function is determined until the transfer function produces the spurious frequency components that meet the requirements. The components for a loop filter are selected based on the selected PLL transfer function. The adjustable frequency source tuning gain, the phase detector gain, the loop filter gain, and the divide factor are chosen to meet the requirements of the PLL transfer function.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: October 18, 2016
    Assignee: Dialog Semiconductor B.V.
    Inventor: Jan Prummel
  • Patent number: 9356606
    Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: May 31, 2016
    Assignee: SILICON LABORATORIES INC.
    Inventors: Aaron J. Caffee, Brian G. Drost, Hendricus de Ruijter
  • Patent number: 9225350
    Abstract: A frequency source for providing a desired source frequency has a direct digital synthesis circuit having a DDS output including a desired DDS frequency, a plurality of low-level spur frequencies and a plurality of high-level spur frequencies; a first clock input for the direct digital synthesis circuit; a second clock input for the direct digital synthesis circuit; a DDS filter in communication with the DDS output; and a controller. The controller selects one of the clock inputs to avoid having a high-level spur in an output of the DDS filter. The source frequency is provided at the DDS filter output.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: December 29, 2015
    Assignee: Keysight Technologies, Inc.
    Inventor: Steven Schupbach
  • Patent number: 9225342
    Abstract: An oscillation device corrects a setting value of an output frequency based on a detection result of an ambient temperature of a crystal unit. The oscillation device includes: an oscillation circuit; a temperature detection portion that detects the ambient temperature and outputs a digital value corresponding to the temperature detection value; an accumulator that accumulates the digital value; a rounding processing portion that performs rounding for the digital value accumulated in the accumulator; a digital filter that receives the digital value obtained from the rounding processing portion and obtains a step response gradually increasing from “0” and converging to a step value; and a correction value obtaining portion that obtains a frequency correction value of the oscillation frequency of the oscillation circuit caused by a difference between the ambient temperature and a reference temperature, wherein the setting value of the output frequency is corrected based on the frequency correction value.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 29, 2015
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Kazuo Akaike, Kaoru Kobayashi
  • Patent number: 9209745
    Abstract: Apparatus and methods for multiphase oscillators are provided. In certain implementations, an oscillator system includes a first multiphase oscillator and a second multiphase oscillator that are phase and frequency-locked. Additionally, the first and second multiphase oscillators are phase-locked by an amount of phase shift that provides colocated clock signal phases of relatively wide angular distances, which can be used by the oscillators' amplification circuits. The first and/or second multiphase oscillators include one or more amplification circuits that operate using at least one clock signal phase generated by the first multiphase oscillator and using at least one clock signal phase generated by the second multiphase oscillator.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 8, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventor: Stephen Mark Beccue
  • Patent number: 9172393
    Abstract: Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: October 27, 2015
    Assignee: Broadcom Corporation
    Inventors: David Stoops, Min Gyu Kim, Vinod Jayakumar
  • Patent number: 9154076
    Abstract: A dual-mode crystal oscillator includes a single AT-cut quartz crystal piece, a package, and an integrated circuit. The integrated circuit includes an oscillation circuit configured to cause the AT-cut quartz crystal piece to oscillate at a frequency in the MHz band, a dividing circuit configured to divide the frequency in the MHz band to generate a frequency of 32.768 kHz, a selection circuit configured to select one of a pause state where the frequency in the MHz band is not output and an active state where the frequency in the MHz band is output. The mounting surface includes three electrodes arranged in a direction along the long side and two electrodes arranged in a direction along the short side. The electrode to output the frequency of 32.768 kHz and the electrode to output the frequency in the MHz band are arranged not adjacent to one another.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 6, 2015
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Wen Jen Chen, Chisato Ishimaru
  • Patent number: 9130575
    Abstract: A method of operation of a wireless communication system includes: synthesizing an incoming clock reference by differentiating an even cycle signal and an odd cycle signal; commutating a pair of resistors (R1, R2) based on the even cycle signal and the odd cycle signal; and controlling an amplifier output by the pair of the resistors (R1, R2) for the purpose of mitigating the effects of mismatch of the pair of resistors.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gennady Feygin, Inyup Kang
  • Patent number: 9094185
    Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 28, 2015
    Assignee: MICROSEMI SEMICONDUCTOR ULC
    Inventors: Paul H. L. M. Schram, Krste Mitric, Slobodan Milijevic, Tanmay Zargar, David Colby
  • Publication number: 20150130544
    Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 14, 2015
    Applicant: MARVELL WORLD TRADE LTD
    Inventors: Xiang GAO, Li Lin
  • Patent number: 9024693
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9019018
    Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 28, 2015
    Assignee: ams AG
    Inventor: Ruggero Leoncavallo
  • Patent number: 9013240
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Publication number: 20150097627
    Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: Broadcom Corporation
    Inventor: Xicheng Jiang
  • Patent number: 8990606
    Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Oracle International Corporation
    Inventors: Sebastian Turullols, Ali Vahidsafa
  • Patent number: 8988151
    Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Jackson Labs Technologies Inc.
    Inventor: Gregor Said Jackson
  • Publication number: 20150077189
    Abstract: An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventor: TOMOYA YORITA
  • Patent number: 8975969
    Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Michael C. Meholensky, Vadim Olen, Adrian A. Hill, Paul L. Opsahl
  • Patent number: 8975970
    Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 10, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeffrey L. Sonntag
  • Publication number: 20150054589
    Abstract: According to one aspect, embodiments herein provide a PVR comprising a resonator having an oscillation frequency, the resonator comprising at least one proof-mass, a mechanical reference, at least one drive plate located adjacent a first side of the at least one proof-mass, and at least one sense plate located adjacent a second side of the at least one proof-mass, a voltage source coupled to the drive and sense plates, a reference oscillator configured to provide a reference signal having a reference frequency to the voltage source; and an output, wherein the voltage source is configured to provide a bias voltage signal to the at least one drive and at least one sense plates of the resonator to drive the oscillation frequency of the resonator to match the reference frequency, and wherein the bias voltage signal is also provided to the output of the PVR as a voltage reference signal.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Paul A. Ward, James S. Pringle, Marc S. Weinberg
  • Patent number: 8963750
    Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: David Canard, Julien Delorme
  • Publication number: 20150042407
    Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 12, 2015
    Inventors: Ming-Chung Huang, XINGLONG LIU
  • Publication number: 20150028956
    Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 29, 2015
    Inventor: Toshiharu Okamoto
  • Patent number: 8928417
    Abstract: A phase frequency detector realizes a highly linear conversion from noise-shaped ?? modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: January 6, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: David Canard
  • Publication number: 20140368282
    Abstract: A frequency generation device is provided. The frequency generation device includes a voltage generation unit configured to receive an input signal having an input frequency and to generate a feedback voltage based on the input signal, wherein the feedback voltage is proportional to the input frequency; and a feedback unit connected to the voltage generation unit and a reference voltage source, wherein the feedback unit is configured to receive a reference voltage from the reference voltage source and the feedback voltage from the voltage generation unit, so as to generate a feedback signal having a feedback frequency.
    Type: Application
    Filed: April 30, 2014
    Publication date: December 18, 2014
    Inventor: Zhigang FU
  • Publication number: 20140361840
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Application
    Filed: September 13, 2013
    Publication date: December 11, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Publication number: 20140361841
    Abstract: A signal generation circuit including a phase locked loop circuit that uses an oscillation section as a reference signal source and a switching section capable of switching a state in which a periodic signal from the oscillation section is outputted to a state in which a signal from the phase locked loop circuit is outputted.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Mitsuaki SAWADA, Tetsuya YONEMURA
  • Publication number: 20140354364
    Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Gilles J. Muller, Jeffrey C. Cunningham, Karthik Ramanan
  • Publication number: 20140347105
    Abstract: Various configurations and arrangements of systems and methods for compensating for variations in VCO output frequencies are described. A system in accordance with the disclosure can include an oscillator circuit including an oscillator, a first variable capacitance diode coupled to the oscillator and a second variable capacitance diode coupled to the oscillator. The system further includes a voltage source configured to apply a first voltage to the oscillator circuit to cause the output signal to comprise a selected frequency, the selected frequency being based on a received reference voltage. The system further includes a controller circuit configured to compare an operating voltage of the oscillator to the reference voltage while the first voltage is applied to the oscillator; and apply a second voltage to the oscillator circuit based on the comparison. The second voltage compensates for a difference between the reference voltage and the first voltage.
    Type: Application
    Filed: June 10, 2013
    Publication date: November 27, 2014
    Inventors: Dmitriy Rozenblit, Rahul Magoon
  • Patent number: 8896385
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: November 25, 2014
    Assignee: Sand 9, Inc.
    Inventors: Klaus Juergen Schoepf, Reimund Rebel, Jan H. Kuypers
  • Patent number: 8896384
    Abstract: A phase locked loop (PLL) includes a detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), a divider, and a frequency change module. The detector provides a phase difference based on a reference signal and a feedback signal. The charge pump provides a charge based on the phase difference. The loop filter provides a voltage based on the charge. The VCO provides an output signal based on the voltage received from the loop filter. The divider divides a frequency of the output signal by a value to provide the feedback signal. The frequency change module processes an input signal having a first frequency to provide a processed signal having a second frequency that is different from the first frequency. The frequency change module selects the input signal or the processed signal to provide as the reference signal to the detector. Changing the frequency of the reference signal can change a frequency of a spur.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: November 25, 2014
    Assignee: Broadcom Corporation
    Inventor: Hung-Ming Chien
  • Patent number: 8896386
    Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 25, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wen-Chang Lee, Ping-Ying Wang
  • Patent number: 8884706
    Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 11, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Publication number: 20140320215
    Abstract: An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator.
    Type: Application
    Filed: July 10, 2014
    Publication date: October 30, 2014
    Inventors: Robert Bogdan Staszewski, Masoud Babaie, Zhuobiao He
  • Publication number: 20140292418
    Abstract: An oscillation device corrects a setting value of an output frequency based on a detection result of an ambient temperature of a crystal unit. The oscillation device includes: an oscillation circuit; a temperature detection portion that detects the ambient temperature and outputs a digital value corresponding to the temperature detection value; an accumulator that accumulates the digital value; a rounding processing portion that performs rounding for the digital value accumulated in the accumulator; a digital filter that receives the digital value obtained from the rounding processing portion and obtains a step response gradually increasing from “0” and converging to a step value; and a correction value obtaining portion that obtains a frequency correction value of the oscillation frequency of the oscillation circuit caused by a difference between the ambient temperature and a reference temperature, wherein the setting value of the output frequency is corrected based on the frequency correction value.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 2, 2014
    Applicant: NIHON DEMOPA KOGYO CO., LTD.
    Inventors: KAZUO AKAIKE, KAORU KOBAYASHI
  • Patent number: 8847690
    Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Patent number: 8841973
    Abstract: A circuit arrangement for generation of radio frequency output signals which form a broadband frequency ramp, with a reference oscillator, a phase detector, a loop filter, a VC oscillator for generating the output signals, a frequency divider, a step-down mixer and a local oscillator for generating a local oscillator signal. The reference oscillator, the phase detector, the loop filter, the VC oscillator, the frequency divider and the step-down mixer belong to a phase-locking loop. The frequency divider and the step-down mixer are in the feedback path of the phase-locking loop. The step-down mixer mixes the output signals and the local oscillator signal. The frequency of the output signal is adjustable by varying the division ratio of the frequency divider. Characteristics of the output signal are improved using the adjustable frequency of the local oscillator signal.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: September 23, 2014
    Assignee: KROHNE Messtechnik GmbH
    Inventors: Thomas Musch, Nils Pohl
  • Publication number: 20140266353
    Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Yi Tang, Bo Sun
  • Patent number: 8830002
    Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 9, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Ken Yeung, Hedley Rainnie
  • Patent number: 8830001
    Abstract: A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jingcheng Zhuang, Robert Bogdan Staszewski
  • Patent number: 8816777
    Abstract: A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 26, 2014
    Inventor: Tomany Szilagyi
  • Patent number: 8791762
    Abstract: Frequency synthesizers for use with oscillators that generate an arbitrary frequency are described, as well as related devices and methods. Divider information can be generated or otherwise accessed for use in configuring a phase lock loop device that is adapted for coupling with the oscillator, where the phase lock loop device can include a plurality of integer dividers without utilizing a fractional divider, where the divider information can include frequency deviations corresponding to groups of integer divider settings for the phase lock loop device, and where each deviation of the frequency deviations can be based on a frequency differential between a standard operating frequency and an output frequency for the phase lock loop utilizing one group of integer divider settings from the groups of integer divider settings.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: July 29, 2014
    Assignee: Sand 9, Inc.
    Inventors: Reimund Rebel, Klaus Juergen Schoepf
  • Publication number: 20140191811
    Abstract: A calibration circuit includes a combinational gate configured to receive a voltage-controlled oscillator (VCO) output signal and a selected reference signal to detect a phase difference between the VCO output signal and the selected reference signal and generate an output binary signal, in which the VCO output signal has one or more unwanted frequency components. The calibration circuit also includes a loop filter configured to filter the output binary signal and generate a filtered calibration signal. The calibration circuit also includes an analog-to-digital converter configured to convert the filtered calibration signal from the analog domain to the digital domain and generate a converted calibration signal. The calibration circuit also includes a processor configured to compute the converted calibration signal and determine components of a baseband signal that cancels the one or more unwanted frequency components of the VCO output signal.
    Type: Application
    Filed: March 13, 2013
    Publication date: July 10, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Ahmad MIRZAEI, Hooman DARABI
  • Patent number: 8773181
    Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Cambridge Silicon Radio, Ltd.
    Inventors: Duncan Mcleod, Farshid Nowshadi, David Chappaz
  • Patent number: RE45619
    Abstract: Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: July 21, 2015
    Assignee: Intellectual Discovery Co., Ltd.
    Inventors: Sangho Shin, Sang-Hyun Cho, Seok-Oh Yun, Jong-Moon Kim