With Reference Oscillator Or Source Patents (Class 331/18)
  • Patent number: 10969783
    Abstract: In one embodiment, a system receives a number of times from a number of time sources including sensors and real-time clocks (RTCs), wherein the sensors are in communication with an autonomous driving vehicle (ADV) and the sensors include at least a GPS sensor. The system generates a difference histogram based on a time for each of the time sources for a difference between a time of the GPS sensor and a time for each of the other sensors and RTCs. The system ranks the sensors and RTCs based on the difference histogram. The system selects a time source from one of the sensors or RTCs with a least difference in time with respect to the GPS sensor. The system generates a timestamp based on the selected time source to timestamp sensor data for a sensor unit of the ADV.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 6, 2021
    Assignee: BAIDU USA LLC
    Inventors: Manjiang Zhang, Xiangtao You, Oh Kwan
  • Patent number: 10958275
    Abstract: Techniques are described for fast wakeup of a crystal oscillator circuit. Embodiments operate in context of a crystal oscillator coupled with a phase-locked loop (PLL). For example, prior to entering sleep mode, embodiments retain a previously obtained coarse code used to coarse-tune a voltage controlled oscillator of the PLL. On wakeup, the PLL is configured in a chirp mode, in which the retained coarse code and a sweep voltage are used to generate a chirp signal at, or close to, a target stimulating frequency for the crystal oscillator. The chirp signal can be used to inject energy into the crystal oscillator, thereby causing the crystal oscillator to move from sleep mode to steady state oscillation relatively quickly.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 23, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ahmed Emira, Faisal Hussien
  • Patent number: 10879843
    Abstract: Embodiments of voltage-controlled oscillators for wireless transmission of data are disclosed herein. In one example, an oscillator circuit includes an active network, a passive differential network coupled to the active network, and a tail tank connected to the active network through a low impedance point of the active network is disclosed. The active network is configured to generate an activating signal for sustaining oscillation of the oscillator circuit. The passive differential network has a first input impedance magnitude peak at a first frequency and a second input impedance magnitude peak at a second frequency. The tail tank circuit has a third input impedance magnitude peak at a third frequency.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 29, 2020
    Assignee: BESTECHNIC (SHANGHAI) CO., LTD.
    Inventors: Tao Zheng, Lu Chai
  • Patent number: 10848159
    Abstract: A drive circuit is configured to drive an oscillator to vibrate the oscillator that outputs a monitor signal according to a physical quantity. The drive circuit includes a drive signal generating unit that generates a drive signal having a drive frequency, a phase difference detector that detects a phase difference between the monitor signal and the drive signal, a frequency controller that controls the drive frequency based on the phase difference, automatic gain control (AGC) unit that controls an amplitude of the drive signal according to an amplitude of the monitor signal, and an output unit that outputs the drive signal having the controlled amplitude to the oscillator. This drive circuit can stably drive and vibrate the oscillator.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 24, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideyuki Murakami, Takeshi Uemura
  • Patent number: 10784826
    Abstract: The present disclosure provide a device, system, and method for generating, in an electrical device, a 1 bit or a 0 bit that is received in a switching circuit powered by a battery. The device, system, and method generates, in the switching circuit, a negative bias voltage and a positive bias voltage. The device, system, and method transmits the negative bias voltage and the positive bias voltage to a power amplifier. The device, system, and method turns the power amplifier from an off-state to an on-state in response to receiving the negative bias voltage. The device, system, and method amplifies, with the power amplifier, a power signal moving through power amplifier when the amplifier is in the on-state.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: September 22, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Carlton T. Creamer, Christopher R. Bye, Vali Touba, Stephen J Creane
  • Patent number: 10693475
    Abstract: A method for generating a clock signal by a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal and generating a loop filter output signal. In a first mode, the loop filter output signal is generated based on the phase difference signal and a predetermined frequency slope, and may include generating a phase-slope-limited version of the phase difference signal based on a predetermined phase slope limit and generating a frequency-slope-limited version of the phase difference signal based on the predetermined frequency slope limit. In a second mode, the loop filter output signal may be generated based on the predetermined frequency slope limit, a value of the loop filter output signal, and a target frequency. In the second mode, the loop filter output signal may be generated further based on a predetermined frequency step value.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 23, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Xue-Mei Gong, James D. Barnette
  • Patent number: 10680624
    Abstract: This disclosure relates to fractional-N phase-locked loops. A digital filter can filter out quantization noise from a modulator. Separate paths can process an integer part associated with an output signal of the digital filter and a fractional part associated with the output signal of the digital filter. The separate paths can be combined in the fractional-N phase-locked loop, for example, as a weighted sum.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 9, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Niall Kevin Kearney, Philip Eugene Quinlan
  • Patent number: 10673671
    Abstract: A method and apparatus for performing a cell search in a wireless communication system is provided. A narrowband user equipment (NB UE) performs the cell search at a specific frequency with a fixed frequency offset, and moves to the specific frequency with the fixed frequency offset and a channel raster.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 2, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Yunjung Yi, Bonghoe Kim, Hyunsoo Ko
  • Patent number: 10579021
    Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Didier Salle, Olivier Vincent Doaré, Birama Goumballa, Cristian Pavao Moreira
  • Patent number: 10560098
    Abstract: A mechanical resonator-based cascadable logic device includes which includes a resonator having a beam with a first fixed end, a second fixed end, and a length between the first and second fixed ends. A first electrode and a second electrode are aligned along a first side of the beam. A third electrode and a fourth electrode are aligned along a second side of the beam and opposite the first and second electrodes. A DC voltage source is coupled to one of the first and second fixed ends of the beam. At least one of the first, second, third, and fourth electrodes is coupled to a first AC voltage source so that a logic operation is performed by activating a second resonant mode of the resonator.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 11, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Saad Ilyas, Md Abdullah Al Hafiz, Hossein Fariborzi, Mohammad Ibrahim Younis
  • Patent number: 10458794
    Abstract: A micromechanical detection structure includes a substrate of semiconductor material and a driving-mass arrangement is coupled to a set of driving electrodes and driven in a driving movement following upon biasing of the set of driving electrodes. A first anchorage unit is coupled to the driving-mass arrangement for elastically coupling the driving-mass arrangement to the substrate at first anchorages. A driven-mass arrangement is elastically coupled to the driving-mass arrangement by a coupling unit and designed to be driven by the driving movement. A second anchorage unit is coupled to the driven-mass arrangement for elastically coupling the driven-mass arrangement to the substrate at second anchorages. Following upon the driving movement, the resultant of the forces and of the torques exerted on the substrate at the first and second anchorages is substantially zero.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: October 29, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Gabriele Gattere, Luca Giuseppe Falorni, Carlo Valzasina
  • Patent number: 10404261
    Abstract: A system for detecting the surrounding environment of vehicle comprising a RADAR unit and at least one ultra-lowphase-noise frequency synthesizer, is provided. A RADAR unit configured for detecting the presence and characteristics of one or more objects in various directions. The RADAR unit may include a transmitter for transmitting at least one radio signal, and a receiver for receiving the at least one radio signalreturned from the one or more objects. The ultra-lowphase-noisefrequency synthesizer may utilize a dual loop design comprising one main PLL and one sampling PLL, where the main PLL might include a DDS or Fractional-N PLL plus a variable divider, or the synthesizer may utilize a sampling PLL only, to reduce phase-noise from the returned radio signal. This system enhances the detection of the exact location of the vehicle based on the received RADAR signatures of objects, azimuth and distance.
    Type: Grant
    Filed: December 16, 2018
    Date of Patent: September 3, 2019
    Inventors: Yekutiel Josefsberg, Tal Lavian, Eran Dor
  • Patent number: 10355679
    Abstract: A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 16, 2019
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventors: Chien-Chuan Huang, Chia-Hsin Tung, Chun-Hung Chen, Hao-Jan Yang, Chieh-Hsiang Chang
  • Patent number: 10333537
    Abstract: An atomic oscillator includes: an atomic cell containing metal atoms; a light source generating light to be emitted to the atomic cell; a driver outputting a driving signal for driving the light source; a light detector detecting the light having passed through the atomic cell; a phase detector detecting an output of the light detector; a voltage controlled oscillator having an oscillation frequency adjusted based on the output detected by the phase detector; a phase modulator phase modulating an output signal of the voltage controlled oscillator and outputting the phase modulated signal; a frequency multiplier which outputs a microwave to the driver, the microwave being obtained by multiplying a frequency of the phase modulated signal; and a frequency divider which frequency divides the output signal of the voltage controlled oscillator and outputs the frequency divided output signal to the phase detector and the phase modulator.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: June 25, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Noriaki Tanaka
  • Patent number: 10320400
    Abstract: Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage control oscillator by comparing both a phase difference between rising edge of a reference signal and rising edge of a feedback signal and a phase difference between falling edge of the reference signal and falling edge of the feedback signal.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: June 11, 2019
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Chang Sik Yoo, Baek Jin Lim
  • Patent number: 10200189
    Abstract: A Dual-mode forward path PLL system and method are disclosed. The forward path PLL system includes a phase frequency detector (PFD) circuit including a first input node a second input node, a first output node a second output node, where the PFD receives a first input signal, a second input signal and generates a first output signal and second output signal, and where the first input signal is a reference frequency signal and the second input signal is a divided frequency value signal, a charge pump circuit including a third input node, a fourth input node and a third output node, where the third input node and the fourth input node are coupled to the first output node and the second output node of the PFD and where the Charge pump is programmable; and a loop filter circuit including a fifth input node and fourth output node, where the fifth input node is coupled to the third output node of the charge pump and where the loop filter circuit is programmable.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SPATIALLINK CORPORATION
    Inventors: Qiang Li, Chen Chen
  • Patent number: 9966963
    Abstract: A frequency synthesizer comprising a reference oscillator configured to generate a first clock signal with a reference frequency and a divider controller configured to receive the first clock signal, a second clock signal, and a multiplier value. The divider controller is configured to obtain a ratio of a frequency of the first clock signal to a frequency of the second clock signal and divide the resulting ratio by the multiplier value to obtain controller output value. A divider is configured to receive the first clock signal and controller output value and output an output clock signal with a frequency equal to the frequency of the first clock signal divided by the controller output value.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Hsuan Chou, Chih-Chiang Chang, Chung-Chieh Yang
  • Patent number: 9923599
    Abstract: Systems and methods which provide injection-locked circuit configurations for radiating signals in the terahertz frequency range with improved phase noise and signal output power are described. Embodiments of the invention provide an injection-locked terahertz radiator system comprising a half-quadrature voltage controlled oscillator (HQVCO), a plurality of injection-locked frequency quadruplers (ILFQs), and antenna elements. In operation according to embodiments, injection-locking provided by the ILFQs may be utilized to facilitate individual optimization of the output power and the phase noise. Intrinsic-delay compensation and harmonic boosting techniques may be utilized in configurations of the foregoing injection-locked terahertz radiator system to optimize the phase noise of the HQVCO and the output power of the ILFQs, respectively.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 20, 2018
    Assignee: City University of Hong Kong
    Inventors: Quan Xue, Liang Wu
  • Patent number: 9891116
    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: February 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shigeki Obayashi, Hiroki Shimano, Masataka Minami, Hiroji Ozaki
  • Patent number: 9866224
    Abstract: An oscillator has an oscillator which comprises a first variable capacitor to adjust capacitance based on a first signal and a second variable capacitor to adjust capacitance, generates an oscillation signal having a frequency in accordance with the capacitance of the first variable capacitor and the second variable capacitor, an integer phase detector to detect an integer phase of the oscillation signal, a fractional phase detector to detect a fractional phase of the oscillation signal, a phase error generator to generate a fourth signal indicating a phase error of the oscillation signal, a first filter to extract the first signal in a predetermined frequency band, included in the fourth signal, and to output the first signal, and a second filter to extract the second signal in a predetermined frequency band, included in the fourth signal, and to output the second signal.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 9, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Kondo, Akihide Sai, Masanori Furuta
  • Patent number: 9819350
    Abstract: A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jingdong Deng, Chung S. Ho, David Flye, Zhenrong Jin, Ramana M. Malladi
  • Patent number: 9667237
    Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 30, 2017
    Assignee: MICROSEMI SEMICONDUCTOR ULC
    Inventors: Qu Gary Jin, Paul H. L. M. Schram, Krste Mitric, Cathy Zhang, Gabriel Rusaneanu, Wenbao Wang
  • Patent number: 9614557
    Abstract: A method and apparatus for phase adjustment of a RF transceiver is disclosed. Based on a first local oscillator signal and a second local oscillator signal, a beat signal that indicates the frequency and phase relationship between the first and second local oscillator signals can be generated. Using the beat signal, changing phase relationship between the first and second local oscillator signals can be cumulatively taken account for using phase averaging to allow quick restoration to observation of a previously observed channel.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Christopher Mayer, David J. McLaurin, Chris Angell
  • Patent number: 9565015
    Abstract: A signal reproduction circuit includes: an oscillator generating first clock and second clock having a same frequency but different phases; and a feedback circuit to control the oscillator in accordance with a phase relation and a frequency relation between input data and the first clock, wherein the feedback circuit includes: a frequency-phase detection circuit to compare a clock phase control signal and a clock phase detection signal and generate a frequency phase signal indicating the frequency relation between the input data and the first clock, a state detection circuit to detect a lock state in which falling edges or rising edges of the input data and the first clock synchronize and a frequency difference state in which frequencies of the input data and the first clock are different, and a selector to supply the frequency phase signal to the feedback loop only in the frequency difference state.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 9520886
    Abstract: A method for correcting long-term phase drift of a crystal oscillator in a numerically-controlled oscillator is described. The method includes determining the phase error in an oscillator signal in comparison with an external time base; delta-sigma modulating the phase error to generate a delta-sigma error bitstream; conditionally adding or subtracting an error correction step size from a phase increment value in each clock cycle based on the delta-sigma error bitstream, to create a modulated phase increment value; and adding the modulated phase increment value to a phase accumulator to generate an error-corrected output digital signal. The delta-sigma-based error correction method avoids the use of multipliers. The same delta-sigma error signal can be used in multiple numerically-controlled oscillators configured to different output frequency if driven by the same reference oscillator.
    Type: Grant
    Filed: November 28, 2013
    Date of Patent: December 13, 2016
    Assignee: Smart Energy Instruments Inc.
    Inventors: Donald Jeffrey Dionne, Brian Leonard William Howse, Jennifer Marie McCann
  • Patent number: 9473156
    Abstract: A method for constructing a phase locked loop begins with determining spurious frequency component criteria permitted within the PLL. A PLL filter prototype is selected with a desired settling time. A transfer function is generated based on the PLL transfer function that predicts the spurious components. A maximum level of the spurious components produced in the PLL is determined based on the maximum frequency step. If the maximum level of the spurious frequency components produced is too large, the order variable is incremented and the PLL transfer function is determined until the transfer function produces the spurious frequency components that meet the requirements. The components for a loop filter are selected based on the selected PLL transfer function. The adjustable frequency source tuning gain, the phase detector gain, the loop filter gain, and the divide factor are chosen to meet the requirements of the PLL transfer function.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: October 18, 2016
    Assignee: Dialog Semiconductor B.V.
    Inventor: Jan Prummel
  • Patent number: 9356606
    Abstract: A clock generator comprises a free-running oscillator and a tunable frequency synthesizer. The free-running oscillator has an output for providing an oscillator clock signal. The tunable frequency synthesizer is coupled to the free-running oscillator and provides a clock output signal in response to the oscillator clock signal and a frequency control signal. The frequency control signal corresponds to a measured characteristic of the free-running oscillator.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: May 31, 2016
    Assignee: SILICON LABORATORIES INC.
    Inventors: Aaron J. Caffee, Brian G. Drost, Hendricus de Ruijter
  • Patent number: 9225342
    Abstract: An oscillation device corrects a setting value of an output frequency based on a detection result of an ambient temperature of a crystal unit. The oscillation device includes: an oscillation circuit; a temperature detection portion that detects the ambient temperature and outputs a digital value corresponding to the temperature detection value; an accumulator that accumulates the digital value; a rounding processing portion that performs rounding for the digital value accumulated in the accumulator; a digital filter that receives the digital value obtained from the rounding processing portion and obtains a step response gradually increasing from “0” and converging to a step value; and a correction value obtaining portion that obtains a frequency correction value of the oscillation frequency of the oscillation circuit caused by a difference between the ambient temperature and a reference temperature, wherein the setting value of the output frequency is corrected based on the frequency correction value.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: December 29, 2015
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Kazuo Akaike, Kaoru Kobayashi
  • Patent number: 9225350
    Abstract: A frequency source for providing a desired source frequency has a direct digital synthesis circuit having a DDS output including a desired DDS frequency, a plurality of low-level spur frequencies and a plurality of high-level spur frequencies; a first clock input for the direct digital synthesis circuit; a second clock input for the direct digital synthesis circuit; a DDS filter in communication with the DDS output; and a controller. The controller selects one of the clock inputs to avoid having a high-level spur in an output of the DDS filter. The source frequency is provided at the DDS filter output.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: December 29, 2015
    Assignee: Keysight Technologies, Inc.
    Inventor: Steven Schupbach
  • Patent number: 9209745
    Abstract: Apparatus and methods for multiphase oscillators are provided. In certain implementations, an oscillator system includes a first multiphase oscillator and a second multiphase oscillator that are phase and frequency-locked. Additionally, the first and second multiphase oscillators are phase-locked by an amount of phase shift that provides colocated clock signal phases of relatively wide angular distances, which can be used by the oscillators' amplification circuits. The first and/or second multiphase oscillators include one or more amplification circuits that operate using at least one clock signal phase generated by the first multiphase oscillator and using at least one clock signal phase generated by the second multiphase oscillator.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: December 8, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventor: Stephen Mark Beccue
  • Patent number: 9172393
    Abstract: Methods, systems, and apparatuses for converting a digital input signal to an analog output signal are disclosed. A first delta-sigma modulator receives a common mode reference signal and generates a common mode control signal. A data delta-sigma modulator receives a digital input signal and generates a modulated digital input signal. A shuffler receives the modulated digital input signal and the common mode control signal and generates a shuffled digital input signal. A digital to analog converter (DAC) has a plurality of tri-level unit DAC elements each receiving a corresponding portion of the shuffled digital input signal as a first input signal, and receiving second and third input signals. The tri-level unit DAC elements have first outputs coupled together generating a first output signal and second outputs coupled together generating a second output signal. An operational amplifier receives the first and second output signals and generates the analog output signal.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: October 27, 2015
    Assignee: Broadcom Corporation
    Inventors: David Stoops, Min Gyu Kim, Vinod Jayakumar
  • Patent number: 9154076
    Abstract: A dual-mode crystal oscillator includes a single AT-cut quartz crystal piece, a package, and an integrated circuit. The integrated circuit includes an oscillation circuit configured to cause the AT-cut quartz crystal piece to oscillate at a frequency in the MHz band, a dividing circuit configured to divide the frequency in the MHz band to generate a frequency of 32.768 kHz, a selection circuit configured to select one of a pause state where the frequency in the MHz band is not output and an active state where the frequency in the MHz band is output. The mounting surface includes three electrodes arranged in a direction along the long side and two electrodes arranged in a direction along the short side. The electrode to output the frequency of 32.768 kHz and the electrode to output the frequency in the MHz band are arranged not adjacent to one another.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 6, 2015
    Assignee: NIHON DEMPA KOGYO CO., LTD.
    Inventors: Wen Jen Chen, Chisato Ishimaru
  • Patent number: 9130575
    Abstract: A method of operation of a wireless communication system includes: synthesizing an incoming clock reference by differentiating an even cycle signal and an odd cycle signal; commutating a pair of resistors (R1, R2) based on the even cycle signal and the odd cycle signal; and controlling an amplifier output by the pair of the resistors (R1, R2) for the purpose of mitigating the effects of mismatch of the pair of resistors.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gennady Feygin, Inyup Kang
  • Patent number: 9094185
    Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 28, 2015
    Assignee: MICROSEMI SEMICONDUCTOR ULC
    Inventors: Paul H. L. M. Schram, Krste Mitric, Slobodan Milijevic, Tanmay Zargar, David Colby
  • Publication number: 20150130544
    Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.
    Type: Application
    Filed: November 13, 2014
    Publication date: May 14, 2015
    Applicant: MARVELL WORLD TRADE LTD
    Inventors: Xiang GAO, Li Lin
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9024693
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Patent number: 9019018
    Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 28, 2015
    Assignee: ams AG
    Inventor: Ruggero Leoncavallo
  • Patent number: 9013240
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Publication number: 20150097627
    Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: Broadcom Corporation
    Inventor: Xicheng Jiang
  • Patent number: 8990606
    Abstract: Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Oracle International Corporation
    Inventors: Sebastian Turullols, Ali Vahidsafa
  • Patent number: 8988151
    Abstract: In one embodiment, the present invention includes a method of correcting the frequency of a crystal oscillator. The method includes establishing an operating baseline for the crystal oscillator using a frequency reference, storing information in memory, and adjusting the frequency according to the information. The information corresponds to the operating baseline. Adjusting the frequency occurs in response to a power-on event and the absence of the frequency reference.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Jackson Labs Technologies Inc.
    Inventor: Gregor Said Jackson
  • Publication number: 20150077189
    Abstract: An oscillator includes a voltage controlled oscillator, a PLL circuit, a crystal unit and an oscillator circuit configured to generate a clock, a digital control circuit, and a clock switching unit. The digital control circuit is configured to set an oscillation parameter of the oscillator circuit, and a parameter of the PLL circuit. The clock switching unit is configured to supply an output signal of the voltage controlled oscillator to the digital control circuit as a clock signal so as to cause the digital control circuit to operate using the clock signal when powered on, and configured to supply an output signal of the oscillator circuit to the digital control circuit as a clock signal after the digital control circuit sets the oscillation parameter of the oscillator circuit. An initial voltage is supplied to the voltage controlled oscillator as a control voltage when the oscillator is powered on.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 19, 2015
    Inventor: TOMOYA YORITA
  • Patent number: 8975970
    Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 10, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeffrey L. Sonntag
  • Patent number: 8975969
    Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Michael C. Meholensky, Vadim Olen, Adrian A. Hill, Paul L. Opsahl
  • Publication number: 20150054589
    Abstract: According to one aspect, embodiments herein provide a PVR comprising a resonator having an oscillation frequency, the resonator comprising at least one proof-mass, a mechanical reference, at least one drive plate located adjacent a first side of the at least one proof-mass, and at least one sense plate located adjacent a second side of the at least one proof-mass, a voltage source coupled to the drive and sense plates, a reference oscillator configured to provide a reference signal having a reference frequency to the voltage source; and an output, wherein the voltage source is configured to provide a bias voltage signal to the at least one drive and at least one sense plates of the resonator to drive the oscillation frequency of the resonator to match the reference frequency, and wherein the bias voltage signal is also provided to the output of the PVR as a voltage reference signal.
    Type: Application
    Filed: August 22, 2013
    Publication date: February 26, 2015
    Applicant: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Paul A. Ward, James S. Pringle, Marc S. Weinberg
  • Patent number: 8963750
    Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: February 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: David Canard, Julien Delorme
  • Publication number: 20150042407
    Abstract: A method for detecting frequency offset of an oscillator includes: receiving an oscillation signal having an oscillation frequency; generating a self-mixing signal according to the oscillation signal; performing frequency division upon the self-mixing signal to obtain a down-converted self-mixing signal; obtaining a down-converted self-mixing frequency corresponding to a maximum power in a specific frequency range of the down-converted self-mixing signal; and computing a frequency offset of the oscillation frequency according to at least the oscillation frequency and the down-converted self-mixing frequency. A related circuit is also disclosed.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 12, 2015
    Inventors: Ming-Chung Huang, XINGLONG LIU
  • Publication number: 20150028956
    Abstract: The disclosed invention is intended to adjust the driving power of an oscillation circuit to be optimal with a simple circuit configuration. A chip includes an oscillation circuit, an amplifier, an effective value measuring circuit, and a control unit. The oscillation circuit includes an inverting amplifier and a resistor coupled in parallel to the inverting amplifier. The oscillation circuit in which the inverting amplifier is coupled to a crystal oscillator outside the chip generates an oscillation circuit by driving the crystal oscillator. The effective value measuring circuit measures an effective value of an oscillation signal produced by the oscillation circuit. The control unit controls the gain of the inverting amplifier so that the effective value will be equal to a target voltage.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 29, 2015
    Inventor: Toshiharu Okamoto
  • Patent number: RE45619
    Abstract: Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: July 21, 2015
    Assignee: Intellectual Discovery Co., Ltd.
    Inventors: Sangho Shin, Sang-Hyun Cho, Seok-Oh Yun, Jong-Moon Kim