Abstract: Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an operating frequency range of the VCO circuitry may be shifted to a different operating frequency range, and closed-loop, continuous frequency range, auto-calibration or other features may be provided.

Abstract: A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

Abstract: Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

Abstract: An apparatus, a signal source, and a method for operating the same are disclosed. The apparatus includes a first signal source, a port, controller, signal synthesizer, and a first timestamp register. The port is adapted to receive a first clock signal that includes a sequence of pulses at a constant clock frequency. The signal synthesizer generates an output signal in response to inputs from the controller, the output signal having a first frequency. The first timestamp register counts pulses from the first clock signal. The controller is adapted to receive a command to change the output signal frequency from the first frequency to a second frequency, the controller causing the signal synthesizer to change the output signal frequency to the second frequency and to generate a frequency change timestamp from the timestamp register indicating a time at which the output signal changed from the first frequency to the second frequency.

Abstract: Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

Abstract: A microwave heating device according to the present invention includes a microwave oscillation portion including a reference-signal oscillator formed from a quarts oscillator, phase variable portions and phase-locked loops and, further, includes a control portion for controlling the microwave oscillation portion, and plural radiation portions placed on a wall surface of a heating chamber for housing a to-be-heated object, wherein microwaves supplied to plural microwave feeding points provided in the radiation portions are controlled in phase and electric power, thereby controlling the aspect of radiations of microwaves radiated from the radiation portions.

Abstract: A circuit arrangement for a front end of an FMCW radar transceiver, with a signal terminal that is configured so as to couple to a signal filter device for purposes of signal exchange, a further signal terminal that is configured so as to couple to a VCO device for purposes of signal exchange, and an electronic circuit, which with the aid of a switching device included in the electronic circuit can be switched over between a reception circuit configuration and a transmission circuit configuration, is disclosed. The switching device has an RF switch, with which a signal route formed respectively in the RF switch, is embodied asymmetrically, in that the signal route in a reception circuit configuration and the signal route in a transmission circuit configuration have a different number of switching stages. A FMCW radar transceiver, and a method for the operation of a front end are also disclosed.

Abstract: Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

Abstract: In some embodiments, an integrated circuit may include a radio frequency synthesizer configured to provide a local oscillator (LO) signal at a selected frequency related to a frequency of interest. The integrated circuit may also include a re-clocking circuit having a first input to receive a clock signal having a first frequency, a second input to receive a local timing signal related to the LO signal, and an output. The re-clocking circuit may be configured to provide a local timing output signal that is a frequency adjusted version of the clock signal based upon the local re-clocking signal. The integrated circuit further may include a digital circuit including an input to receive the local timing output signal as a digital clock signal in a receive mode.

Abstract: A detector includes an oscillation source, a frequency multiplier, a transceiver and a demodulator. The oscillation source generates a first injection signal with a first frequency. The frequency multiplier receives the first injection signal, outputs an output signal and receives a second injection signal with a second frequency. The frequency multiplier uses injection locking to lock a frequency of the output signal at a multiple of the first frequency, and uses injection pulling to pull the frequency of the output signal to the second frequency. The transceiver transmits the output signal and receives a received signal with a third frequency for updating the second injection signal. The demodulator performs a demodulation operation according to the output signal so as to generate a displacement signal.

Abstract: The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.

Abstract: In some embodiments, a digitally controlled oscillator includes a first oscillator a second oscillator and a switch. The second oscillator is selectively enabled in response to a controlled signal. The switch is coupled between the first oscillator and the second oscillator and is selectively conducted in response to the controlled signal, so that an oscillator signal is provided by the first oscillator when the switch is not conducted, and provided by the first oscillator and the second oscillator when the switch is conducted.

Abstract: An apparatus for providing oscillator signals includes an oscillator circuit configured to generate a first oscillator signal with a first oscillator signal frequency for a frequency conversion of a first signal to be converted and to generate a second oscillator signal with a second oscillator signal frequency for a frequency conversion of a second signal to be converted. The oscillator circuit is configured to enable the generation of the first oscillator signal with the first oscillator signal frequency and the second oscillator signal with the second oscillator signal frequency based on at least two different possible oscillator circuit configurations. The control circuit is configured to select, based on the first oscillator signal frequency and the second oscillator signal frequency, one of the possible oscillator circuit configurations of the oscillator circuit for generating the first oscillator signal and the second oscillator signal.

Abstract: Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.

Abstract: A calibration signal is generated from a modulating signal having a first frequency and a carrier signal having a second frequency. A single-sideband mixer modulates the modulating signal on the carrier signal. At least two frequency dividers by two connected in cascade receive the modulating signal modulated on the carrier signal and generate an output of the calibration signal.

Abstract: Systems and methods for mitigating crosstalk between controlled oscillators of Phase-Locked Loops (PLLs) are disclosed. In one embodiment, a system includes a first PLL including a first controlled oscillator and a second PLL. The system further includes a compensation signal generator adapted to generate a compensation signal at an offset frequency that is approximately equal to an offset between output frequencies of the first and second PLLs and apply the compensation signal to the first controlled oscillator such that the output signal of the first controlled oscillator is modulated by the compensation signal. An amplitude and a phase of the compensation signal are such that, when the compensation signal is applied to the first controlled oscillator, a crosstalk signal output by the first controlled oscillator resulting from crosstalk from the second controlled oscillator of the second PLL to the first controlled oscillator of the first PLL is mitigated.

Abstract: Phase-locked loop (PLL) circuits and methods of operation are disclosed. At frequencies that are closer to a center frequency, the phase noise characteristics contributed by a crystal oscillator in a first PLL sub-circuit dominate over the phase noise characteristics contributed by a second PLL sub-circuit, resulting in low close-in phase noise in the overall PLL circuit output signal, while at frequencies farther from the center frequency, the phase noise characteristics contributed by the second PLL sub-circuit dominate over the phase noise characteristics contributed by the crystal oscillator in the first PLL sub-circuit, resulting in low phase noise in the overall PLL circuit output signal at those frequencies.

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract: Embodiments provide a clock generation circuit with a first phase-locked loop (PLL) and a second PLL that are coupled in parallel with one another and receive a same feedback signal. The first and second PLLs generate respective output signals that are combined to generate an output clock signal. A version of the output clock signal may be passed back to the first and second PLLs as the feedback signal. In some embodiments, the second PLL may include a switch to selectively close the second PLL after the first PLL has locked. In some embodiments, the second PLL may include a bulk acoustic wave (BAW) voltage-controlled oscillator (VCO) and the first PLL may include a different type of VCO.

Abstract: A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

Abstract: The invention provides a transmitter comprising two (or more) phase locked loops controlling respective oscillators, and implementing different phase modulation. Multiple phases are derived from the respective oscillators, and an edge rotator forms an output signal from a combination of the phases. The oscillators can operate at different frequencies, neither of which is an integer multiple of the other, whereas the output signals of the multiplexers of the first and second phase locked loops are closer in frequency and can be the same. This reduces the problem of pulling, with a circuit that can be implemented with low power and area and with the versatility of being digitally intensive.

Abstract: A local oscillation generator includes an oscillation circuit, a frequency multiplication circuit, a mixer, and a frequency divider. The oscillation circuit provides a fundamental oscillation signal. The frequency multiplication circuit provides a first oscillation signal according to the fundamental oscillation signal. The mixer provides a mixed oscillation signal according to mixing of the fundamental oscillation signal and the first oscillation signal. The frequency divider frequency divides the mixed oscillation signal so that the local oscillation generator accordingly provides a local oscillation signal.

Abstract: A clock generation system provides a low power approach for generating clock signals. The clock generation system may use a free running clock and, at intervals, maintain the accuracy of the free running clock. The free running clock may be the source of other system clocks, such as a 32 KHz clock for system timing and a 13 MHz clock to facilitate audio playback, e.g., MP3 decoding and playback. The clock generation system eliminates the need for two different crystal oscillators and a complex PLL for generating the low frequency clock.

Abstract: A network element for a packet-switched network has a plurality of network ports for exchanging synchronization messages with further network elements, a local clock, a timestamp generation module associated to each network port for triggering generation of a timestamp, and a synchronization control module selectively configurable in a first operating mode and a second operating mode as a function of a configuration signal. When the synchronization control module is configured in the first operating mode, it is adapted to adjust an offset of the local clock as a function of the timestamps of the synchronization messages received through the slave port. When the synchronization control module is configured in the second operating mode, it is adapted to compute a residence time of a synchronization message in the network element as a function of the timestamps obtained at the time of receiving and sending the synchronization message.

Abstract: Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.

Abstract: An oscillator circuit includes first and second oscillators arranged in a series configuration between a supply voltage node and a reference voltage node. The first and second oscillators are configured to receive a synchronizing signal for controlling synchronization in frequency and phase. An electromagnetic network provided to couple the first and the second oscillators includes a transformer with a primary circuit and a secondary circuit. The primary circuit includes a first portion coupled to the first oscillator and second portion coupled to the second oscillator. The first and second portions are connected by a circuit element for reuse of current between the first and second oscillators. The oscillator circuit is fabricated as an integrated circuit device wherein the electromagnetic network is formed in metallization layers of the device. The secondary circuit generates an output power combining power provided from the first and second portions of the primary circuit.

Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.

Abstract: A system and method are disclosed for performing on die jitter tolerance testing. A set of clocks are generated based on an input signal. The set of clocks include in an in-phase signal based on the data switching edge of the input signal. Additionally, the set of clocks include an inverted clock phase shifted by 180 degrees, and a pair of clocks phase shifted positively and negatively by a certain number of degrees, ?. Data input is sampled based on the inverted clock and the two phase shifted clocks. The eye opening of the input signal can be determined based on whether each of the inverted clock and the two phase shifted clocks sample the correct data from the input signal at various ? values.

Abstract: The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

Abstract: An electronic circuit includes a first PLL circuit including a first frequency divider whose frequency-division ratio is variably controlled, a second frequency divider configured to divide a frequency of a signal input into the first frequency divider, a delay circuit configured to delay an output signal of the second frequency divider, a second PLL circuit configured to receive an output signal of the delay circuit as a reference signal, and a mixer circuit configured to receive as inputs an oscillating signal of the first PLL circuit and an oscillating signal of the second PLL circuit.

Abstract: A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions.

Abstract: A signal-generating circuit includes a voltage-controlled oscillator that generates an oscillated signal; a first frequency divider that generates a first divided signal by dividing the oscillated signal; a second frequency divider that generates a second divided signal by dividing the divided signal; a phase comparator that receives as input the second divided signal and a reference signal and outputs two signals corresponding to a phase difference therebetween; a loop filter that extracts a low frequency signal between the two signals to be output to the voltage-controlled oscillator; a third frequency divider that generates a third divided signal by dividing the first divided signal; a first frequency converter that generates a first frequency converted signal by multiplying the oscillated signal by the third divided signal; and a first multiplier that generates a multiplied signal by multiplying the first frequency converted signal by a first multiplication number.

Abstract: A synchronization device has a normal-signal generator, a reference-signal generator, and a phase difference detector. The normal-signal generator generates a normal signal whose timing is synchronized with a time signal from a satellite. The reference-signal generator generates a reference signal whose timing is synchronized with a received signal. The phase difference detector detects the phase difference between the reference signal and the normal signal. The normal-signal generator then controls the normal signal on the basis of the phase difference when the time signal cannot be obtained.

Abstract: A frequency synthesizer and oscillator are disclosed for reducing noise in processed signals. The synthesizer and oscillator comprise an array of frequency dividers adapted to receive an input signal, which is derived from a single signal source having a prescribed frequency. The synthesizer and oscillator further comprise at least one frequency multiplier coupled to at least one of the frequency dividers, such that in use, the dividers and the at least one multiplier are operable to generate a plurality of frequencies which are coherent with the prescribed frequency. A regulated power supply is also disclosed comprising a filter and first and second regulators, for reducing noise in the output voltage of the power supply.

Abstract: An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A method for reducing the phase noise of a oscillator includes monitoring a phase slope of a resonator, and controlling the resonator to operate the resonator at a high phase slope condition, wherein the resonator comprises a piezoelectric material, or piezoelectric quartz.

Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.

Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A microcontroller chip includes a serial data transmitter having a serial data output pin and an inverter having an input pin and an output pin, the input pin connected to the serial data output pin of the serial data transmitter, the output pin of the inverter and the output pin of the serial data transmitter forming a differential serial data transmission line.

Abstract: A quartz transducer having four or more crystal-controlled oscillators intended for measurement of applied pressure and temperature. All four oscillators are controlled by crystal quartz resonators operating in the thickness-shear mode. Two crystals measure the pressure and temperature respectively. A third crystal is a reference, and the fourth crystal may be another reference crystal or a second temperature crystal. The output of the latter is either phase leading or phase lagging the thermal response of the main temperature sensor.

Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.

Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.

Abstract: In the field of nanoresonator oscillators or NEMS (nanoelectromechanical systems) oscillators, a circuit is proposed for measuring the oscillation frequency of a resonator, including a phase-locked loop with a frequency-controlled oscillator and a phase comparator. The resonator includes a vibration excitation input and a dynamic polarization input (using strain gauges). The frequency-controlled oscillator applies a polarization frequency f1 to the polarization input. A frequency generator supplies a fixed intermediate frequency FI; a mixer receives the frequencies f1 and FI for producing an excitation frequency f0 that is the sum or difference of f1 and FI. The phase comparator receives the frequency FI and the output signal of the resonator and produces a control signal that is sent to the frequency-controlled oscillator, indirectly locking the oscillation frequency onto the resonant frequency of the resonator.