Abstract: A PLL frequency synthesizer tunable in small step sizes that comprises: 1) a first PLL circuit comprising: i) a first feedforward frequency divider that receives an F(in) frequency and generates an F1 frequency, where F1=F(in)/P, ii) a first PLL core that receives the F1 frequency and generates an F2 frequency, where F2=(P+&Dgr;p)F1, and iii) a first feedback frequency divider that receives the F2 frequency and generates a first feedback signal having frequency F2/(P+&Dgr;p); and 2) a second PLL circuit comprising: i) a second feedforward frequency divider that receives the F2 frequency and generates an F3 frequency, where F3=F2/(N+&Dgr;n), ii) a second PLL core that receives the F3 frequency and generates an F(out) frequency, where F(out)=(N)F3, and iii) a second feedback frequency divider that receives the F(out) frequency and generates a second feedback signal having frequency F(out)/(N).

Abstract: Two oscillators produce respective signals at two different frequencies each dependent upon a parameter such as temperature in accordance with a polynomial with coefficients which are different for the two oscillators. A ratio of the frequencies is inverse to a ratio of a selected one of the coefficients of the polynomials. A mixer produces, at a sum or difference frequency of the two signals, an output signal for which a corresponding coefficient of a respective polynomial is substantially zero. The arrangement can be cascaded to produce zero coefficients for a plurality of terms in the polynomial.

Abstract: A frequency synthesizer arrangement for generating signals with frequencies for UMTS and GSM/GPRS frequency bands and a mobile terminal with a respective frequency synthesizer arrangement are proposed, comprising a reference frequency source for providing a signal of constant reference frequency, a first frequency synthesizer sub-unit for transforming the signal of the reference frequency source into a signal with a frequency in a range of a first type of frequency band, a second frequency synthesizer sub-unit for transforming the signal of the reference frequency source into a signal with a frequency in a range of a second type of frequency band, whereby the second frequency synthesizer sub-unit further transforms the signal of the reference frequency source into a signal with an intermediate frequency, and a third frequency synthesizer sub-unit transforms the signal of the reference frequency source into an auxiliary signal with a fixed frequency which is used together with the signal of intermediate freque

Abstract: The invention relates to a device (1) for producing a reference frequency signal (Se) from the response of an atomic resonator (R) to a pumping signal (Fat) transmitted thereto, comprising: a first oscillator for production of a first signal (S1) of frequency (F0) as a function of the response signal (E1) from the resonator (R); a second oscillator (13) for production of a second signal (S2) at a frequency (NF0) which is equal to a whole multiple of that of the first signal (S1). According to the invention, the second oscillator is selected to produce a second signal (S2) close in frequency to the frequency of resonance for the resonator (R).

Abstract: A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

Abstract: A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit.

Abstract: An oscillator transmission switching circuit switches between asynchronous oscillator signals with low latency. Preferably, a fast switching circuit triggers a transition from a first oscillator to a second oscillator by entering a bridge input immediately following an edge of the first oscillator, holding in the bridge input until the same edge of the second oscillator is detected, and switching to the second oscillator. Preferably, the bridge input is selectable to accommodate conditions in which the first oscillator signal is stuck at either a logic 0 or a logic 1. A change of oscillators may be triggered by a fault detection circuit or by an external signal.

Abstract: A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: To minimize the overall circuitry necessary in a multiband-frequency generator, output terminals of a voltage-controlled multiband oscillator (22-1, . . . , 22-N) are coupled to a frequency synthesis unit (10) via a frequency selective coupling unit (24). The frequency synthesis unit (10) derives a phase difference between a frequency control input signal and the output signal of the frequency selective coupling unit (24) to control the voltage-controlled multiband oscillator (22-1, . . . , 22-N).

Abstract: A control voltage is fed to an oscillation circuit from a control terminal, and a power supply voltage is fed thereto from a power supply terminal. An output circuit is provided between the oscillation circuit and an output terminal. The power supply terminal is connected to a feedback terminal through a DC separating capacitor and an amplifier. A signal leaking out to the power supply terminal from the oscillation circuit is fed to the amplifier through the DC separating capacitor. The amplifier amplifies the signal leaking out to the power supply terminal, and feeds the amplified signal to the feedback terminal as a feedback signal Loop.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: A phase locked loop (PLL) frequency synthesizer includes a voltage controlled oscillator (VCO) to provide a VCO frequency signal, a frequency offset circuit including a mixer accepting the VCO frequency signal and a signal from a second oscillator to produce a shifted-frequency signal having a frequency significantly lower than the VCO output frequency, a programmable divider accepting the shifted-frequency signal and dividing the frequency of the shifted-frequency signal by a settable amount, a phase detector to compare the phase of the output of the programmable divider to that of a reference oscillator and produce a phase difference signal; and a loop filter to filter a function of the phase difference to produce a control input to the VCO. The offset circuit shifts down the frequency without increasing the divide ratio of the loop as would a prescaler achieving the same frequency conversion as the frequency offset circuit.

Abstract: A differential oscillator circuit including first (10) and second (20) branches each including the series arrangement, between high (VDD) and low (VSS) supply potentials, of a transistor (4, 5) and bias means (2, 3, 8, 9) for imposing a determined current through the current terminals of the transistor. The transistors are interconnected so as to form a crossed pair of transistors, the most positive current terminal of each transistor (on the “drain” side) being connected to the control terminal of the other transistor of the crossed pair. This differential oscillator circuit further includes an electro-mechanical resonator (6) connected to the crossed transistor pair on the “drain” side, as well as a capacitive element (7) connected to the crossed transistor pair on the “source” side.

Abstract: A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

Abstract: A cluster of processing systems wherein each system is set to operate at a unique operating frequency. Each unique frequency is set to differ from each other by at least a predetermined frequency differential or bandwidth. When clustered, the radiated emissions will not add. Rather, the RF energy is distributed over the predetermined frequency bandwidth and in so doing achieve a reduction of measured RF energy at any singular frequency. By using RF energy dispersal in aggregate systems, the need for special or additional RF shielding is precluded. Current design and manufacturing techniques can continue to be used. Thus, reducing the overall cost of implementing aggregated systems.

Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: Method and apparatus for providing a controlled voltage to an integrated circuit is described. A first frequency value indicative of a first voltage is compared to a second frequency value indicative of a second voltage. The second frequency value is adjusted by the second voltage until the second frequency value is within a range of the first frequency value. Additionally, the second voltage may be adjusted to maintain the second frequency value within the range.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals and a first control signal in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to the first control signal.

Abstract: A high frequency signal source and method of generating a high frequency signal is disclosed. An output signal is generated from a dielectric resonator oscillator and mixed with an output signal from a voltage controlled oscillator having a predetermined tuning range and part of a phase locked loop circuit to sum the frequencies for creating a final output frequency. A portion of the final output frequency is coupled into the phase locked loop circuit that is phase locked to a reference signal from a crystal reference oscillator. The voltage controlled oscillator has a tuning range that is used to compensate for the dielectric resonator oscillator initial frequency error and drift over temperature and aging while the balance of the bandwidth is used to provide the tuning range on the local oscillator output.

Abstract: A tuning circuit for use in tuning multiple voltage-controlled oscillators (VCOs) of a phase-locked loop (PLL) is provided. A search algorithm is used to determine which VCO to use for a given frequency to be synthesized by the PLL. The tuning circuit provides a binary representation, associated with the frequency to synthesize, to the PLL. The PLL responds to this representation by attempting to synthesize the associated frequency. New binary representations are provided until an indication of a threshold frequency between multiple VCOs is determined. A record of the threshold frequency is stored. The binary representation of a frequency to be synthesized and the stored record of the threshold frequency are used to provide an indication of which VCO of the PLL to use to synthesize the desired frequency.

Abstract: A communications system using a phase locked loop employing two-point modulation is disclosed. The phase locked loop further includes a master oscillator having an output operably coupled to a first input of the phase detector; a slave oscillator having an output operably coupled to a second input of the phase detector, and a forward-gain-adaptation module having a first input operably coupled to the raw-error terminal of the phase detector.

Abstract: A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.

Abstract: One of outputs of reference frequency sources 11 and 12 is selected by a switch 13, as a reference frequency signal and compared with the phase of an output of a frequency divider 19 by a phase comparator 14. A voltage controlled oscillator 16 is controlled by a result of comparison. An output of the voltage controlled oscillator 16 and an output of another reference frequency source 18 are mixed by a mixer 17. An upper side band frequency signal of the mixer 17 is used as an output of the multiple PLL oscillator, and a lower side band frequency signal of the mixer 17 is supplied to the frequency divider 19. With the configuration, in the multiple millimeter PLL oscillator, even when the dividing number of frequency increases, lock-up time to reach a desired frequency can be shortened. Thus, stability of a PLL can be improved and specifications of the oscillation frequency of the millimeter wave band and a step frequency of hundreds kHz can be realized.

Abstract: In one embodiment, a first circuit is configured to receive an input reference signal and a feedback signal, and present a reference clock signal based on a difference (e.g., phase difference) between the input reference signal and the feedback signal. The first circuit is further configured to present the reference clock signal even when the reference signal is disrupted. A frequency divider may be employed to scale the frequency of the feedback signal. The reference clock signal may be presented to another circuit to generate one or more output clock signals that are phase-locked to the reference clock signal, for example.

Abstract: A cluster of processing systems is provided wherein each processing system is set to operate at a unique operating frequency. Each unique frequency is set to differ from each other by at least a predetermined frequency differential or bandwidth. When clustered, the radiated emissions will not add. Rather, the RF energy is distributed over the predetermined frequency bandwidth and in so doing achieve a reduction of measured RF energy at any singular frequency. By using RF energy dispersal in systems consisting of aggregated processing elements as subsystems, the need for special or additional RF shielding is precluded. Current design and manufacturing techniques can continue to be used. Thus, reducing the overall cost of implementing aggregated systems.

Abstract: A mobile radio communications device has a first crystal oscillator for providing a first master clock frequency for the timebase of a first communications system, a second crystal oscillator for providing a second master clock frequency for the timebase of a second communications system, and a phase locked loop connected between the first and second crystal oscillators and arranged to lock the first and second crystal oscillators together so that the two timebases cannot drift.

Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: The invention relates to the locking of a phase-locked loop when the frequency setting (an) of the loop is changed. The locking speed of the loop is improved at the expense of noise characteristics so that these are momentarily degraded. When changing the frequency, the difference between the new frequency set for the VCO (430) and the actual frequency (fVCO) is measured and the VCO is immediately controlled according to this difference. To that end, counters (441, 444) dividing a reference frequency (fref) and the VCO frequency are made to simultaneously start counting from zero. Thus the length of the pulse issued by a phase difference detector (410) corresponds to the said frequency difference. After the setting of the new frequency value the loop filter (420) is turned into a purely capacitive circuit the output voltage (vc) of which changes proportionally to the length of the pulse from the phase difference detector.

Abstract: A multi-band transceiver having a receiver portion and a transmitter portion, wherein the receiver portion includes a direct conversion receiver system for directly downconverting a signal to baseband frequencies. The direct conversion receiver system includes a frequency translator having first and second inputs and an output. A first signal at a first frequency is applied to the first input. A second signal having a second frequency is applied to the second input. The first frequency is preferably an nth order subharmonic of the second frequency, wherein n is an integer greater than 1. A low pass filter is integral with or inherent to the first input, and a high pass filter is integral with or inherent to the second input. The corner frequencies of both the low pass and high pass filters is above the first frequency and below the second frequency.

Abstract: The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) each having a voltage controlled timing circuit for receiving a constant master voltage signal and variable slave voltage signal. Each CTS also includes a control logic circuit for selecting the constant master voltage signal for use by the voltage controlled timing circuit when the CTS is master and for selecting the variable slave voltage signal when the CTS is slave. Using a constant master voltage signal eliminates the need for a separate master oscillator in each CTS. Oscillators are typically expensive, consume significant space on the printed circuit board and have location restrictions on where they may be placed on the printed circuit board.

Abstract: A first and second phase-locked loop each having their frequency of operation under programmable control by changing the divider ratio. A single programming word contains the divider ratio for the first phase-locked loop and addressing bits which address a plurality of auxiliary registers for changing the divider ratio of the second phase-locked loop. In a cellular telephone, this allows the digital signal processor to change from receive to transmit mode or from one transmit mode or from one frequency to another utilizing a single command word.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A frequency synthesizer for generating an oscillator signal with a desired frequency includes a first phase locked loop and a second phase locked loop, which is connected in a cascaded manner to the first phase locked loop, such that the second phase locked loop receives, as a reference frequency, a frequency generated by the first phase locked loop. The second phase locked loop outputs the desired oscillator signal at the output of a divider provided in the feedback path of the second phase locked loop. A method of supplying a mixing oscillator signal to a mixer is also provided.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a plurality of output clock signals in response to a reference clock signal and a feedback signal. The second circuit may be configured to select one of the plurality of output clock signals as the feedback signal in response to a first control signal. The first control signal may be configured to minimize a difference in delay between the plurality of output clock signals.

Abstract: A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.

Abstract: A circuit includes a first voltage-controlled oscillator (VCO) that generates a feedback clock. The circuit further includes a phase frequency detector, a charge pump and a loop filter that together receive a reference clock and the feedback clock, and in response thereto, generates a first voltage signal. The circuit further includes a timing generator that generates a control signal having varying periods, and a voltage modulator that receives the first voltage signal and the control signal, and in response thereto, generates a second voltage signal and a third voltage signal. The second voltage signal is provided to the first VCO. The circuit also includes a second VCO that receives the third voltage signal and which outputs a spread spectrum clock.

Abstract: The present invention provides a balanced input/output filter device comprising two resonators, a pair of coupling capacitors, a positive input terminal and a negative input terminal, and a positive output terminal and a negative output terminal. Both sides of one resonator are serial connected to spiral-type inductors on the other metal layers, and both sides of the other resonator are serial connected to parallel-type capacitors on the other metal to layers. The coupling capacitors couple between the spiral-type inductors and the parallel-type capacitors respectively, and the output and input terminals are coupled to the spiral-type inductors and parallel-type capacitors respectively, which are coupled to the resonators.

Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: A local oscillator apparatus is disclosed for use in radio frequency communication systems. The local oscillator apparatus comprises at least one mixer coupled to an oscillator input signal and to a feedback signal such that a local oscillator signal may be produced by fractional multiplication of the oscillator input signal. In an embodiment of the invention, the local oscillator apparatus includes a regenerative modulator comprising a pair of frequency dividers and a single side band mixer.

Abstract: A frequency generating circuit comprises a first, fine PLL frequency synthesiser circuit (FS2) which consumes a low current and is slow to settle, a second, coarse PLL frequency synthesiser circuit (FS1) which consumes a high current and is fast to settle, and a signal combining circuit (36) for additively combining the outputs of the first and second frequency synthesiser circuits to provide a final output frequency. The first frequency synthesiser circuit is energised sufficiently in advance of the second frequency synthesiser circuit that both achieve lock substantially simultaneously. The overall current consumed is less than would be consumed if a single PLL frequency synthesiser is used to generate the final frequency.

Abstract: A clock recovery circuit for recovering clock signals from one of a plurality of input reference signals, includes an acquisition phase locked loop (PLL) for each input. The acquisition PLL having phase comparator for comparing the phase of an input signal to a feedback signal, and first and second digital controlled oscillators (DCOs) receiving an input from the phase comparator. The first DCO of the acquisition PLL is in a feedback loop to supply an input to the phase comparator and the second DCO of the acquisition PLL has a control input to introduce a phase offset therein relative to said the DCO of the acquisition PLL and provides an output for the acquisition PLL. An output PLL has a phase comparator selectively connectable to the output of each of the acquisition PLLs. The output PLL has a first DCO providing an output for the circuit and a second DCO in a feedback loop providing a feedback signal to the phase comparator of the output PLL.

Abstract: A microwave synthesizer includes a drift-cancel loop having a narrow-band input, a low-frequency comb input, a wide-band input, and an output for providing an adjustable-frequency output signal. A narrow-band synthesizer is coupled to the narrow-band input, and a comb generator is coupled to the low-frequency comb input. Instead of using a wide-band synthesizer to drive the wide-band input, as conventional topologies have done, the instant invention employs a highly stable, low noise high frequency oscillator. The output of the oscillator is mixed with the output of the comb generator to produce low-noise, high frequency combs. The low-noise, high frequency combs are then used to drive the wide-band input of the drift-cancel loop. Significant reductions in phase noise can be achieved as compared with conventional designs.

Abstract: An adaptive process controller drives a process variable to be substantially equivalent to a set point and adapts the controller gain, the controller reset, and/or the controller rate, based on model free adaptation. The adaptive controller combines a controller gain computed from an oscillation index with a controller gain computed from a steady state estimate and that adapts the controller reset/rate by forcing the ratio of two of the controller proportional, integral or derivative terms to be equal to a predetermined value.

Abstract: A clock generator including a PLL circuit serves to generate an output frequency cycled in a predefined range and containing a desired clock frequency. The PLL circuit contains a voltage-controlled oscillator (18), the oscillating frequency of which is adjustable by means of an analog control voltage to the desired clock frequency in a fixed relationship to a reference frequency applied to the PLL circuit. The clock generator contains a second voltage-controlled oscillator (22), the oscillating frequency of which can be cycled in the predefined range. The second oscillator (22) is configured so that its oscillating frequency can be varied by means of a digital incrementally variable control signal in the predefined range. By varying the output frequency of the clock generator a spreading of its output frequency spectrum is attainable, resulting in a reduction in high-frequency interference by the signal generated by the clock.

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: A PLL circuit having a gain control function includes: a first phase comparator for outputting a first phase difference signal indicating a phase difference between a first input signal and a second input signal; a first loop filter for smoothing a signal based on the first phase difference signal and outputting a first control voltage; a VCO for oscillating at a frequency based on the first control voltage and thereby outputting a first clock; and a dummy VCO having characteristics identical with those of the VCO for oscillating at a frequency based on a second control voltage and thereby outputting a second clock.

Abstract: A dual-mode telephone with a satellite communication adapter is disclosed. According to one embodiment of the present invention, a cellular-type handportable phone is equipped with a connector for the attachment of accessories. This connector provide a satellite communications adapter accessory access to the handset's signal processing resources which may operate in an alternative mode to process signals received from the satellite and converted by the adapter into a suitable form for processing. The processing translates the satellite signals into voice or data, and vice-versa.

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, wireless communication frequency synthesizer for generating multiple band high-frequency signals is disclosed having a first VCO selectable for a first frequency band and a second VCO selectable for a second frequency band.