Polyphase Output Patents (Class 331/45)
  • Patent number: 9762181
    Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs.
    Type: Grant
    Filed: July 30, 2016
    Date of Patent: September 12, 2017
    Assignee: Maxlinear, Inc.
    Inventors: Abhishek Jajoo, Pawan Tiwari, Vamsi Paidi
  • Patent number: 9490823
    Abstract: Described herein is a self-biased oscillator. The self-biased oscillator comprises a first differentiator with adjustable resistance or capacitance, the first differentiator having an output node and an input node; and a second differentiator with adjustable resistance or capacitance, the second differentiator having an input node coupled to the output node of the first differentiator, and having an output node coupled to the input node of the first differentiator.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventor: Taner Sumesaglam
  • Patent number: 9473069
    Abstract: Apparatus and methods for phase linearization and interpolation in rotary traveling wave oscillators (RTWOs) are provided. In certain configurations, an RTWO system includes a first elongated RTWO and a second elongated RTWO that are phase-locked to one another with a non-zero phase shift. The first and second elongated RTWOs each include two elongated sections of differential transmission line of high phase linearity. For example, such long and straight sections of the differential transmission lines can have uniform capacitance loading and avoid non-uniformities in length and/or thickness associated with poor phase linearity. The RTWO system further includes tap circuitry that receives clock signal phases from the elongated sections of the RTWOs. In certain implementations, the tap circuitry includes one or more interpolation circuits that interpolate received clock signal phases to increase the number of available phases. The RTWO system can include a large number of taps of high phase linearity.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 18, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Stephen Mark Beccue
  • Patent number: 9374091
    Abstract: The invention relates to an input circuit arrangement (11), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection (13) for supplying a connection signal (SWI) and a detection circuit (14). The detection circuit (14) is coupled on the input side to the connection (13) and is designed to put the input circuit arrangement (11) into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI).
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: June 21, 2016
    Assignee: AMS AG
    Inventors: Michael Böhm, Johannes Fellner
  • Patent number: 9106234
    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 11, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yunliang Zhu, Yiwu Tang
  • Publication number: 20150123738
    Abstract: One embodiment of the present invention features a poly-phase local oscillator generator combining frequency dividers and direct-injection-locked phase correctors. The poly-phase local oscillator generator comprises a plurality of phase correctors configured to relax frequency and tuning range of a reference local oscillator (LO), and a plurality of frequency dividers, coupled to the phase correctors, configured to offer different frequency segments. The phase correctors are expandable, so that phase accuracy can be optimized by cascading more of themselves.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: University of Macau
    Inventors: Ka-Fai UN, Pui-In MAK, Rui Paulo da Silva MARTINS
  • Patent number: 9019030
    Abstract: A memristor-based emulator including a memristor circuit for use in digital modulation that includes a first current feedback operational amplifier (CFOA) having multiple terminals in communication with a capacitor Cd and in further communication with a resistor Ri. A second CFOA having multiple terminals is in communication with the first CFOA and is adapted to be in further communication with a voltage vM to provide an input current iM for integration by a capacitor Ci. A nonlinear resistor is in communication with the second CFOA. A third CFOA having multiple terminals is in communication with the nonlinear resistor and is in further communication with the first CFOA and a resistor Rd. The third CFOA and the resistor Rd act as an inverting amplifier associated with the nonlinear resistor to increase a current gain to increase a difference between ON and OFF values of a resistance of a realized memristor.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: April 28, 2015
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Muhammad Taher Abuelma'atti, Zainualbideen Jamal Khalifa
  • Patent number: 9019021
    Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: April 28, 2015
    Assignee: Intel Corporation
    Inventors: Rotem Banin, Ofir Degani, Eran Socher
  • Patent number: 9007135
    Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 14, 2015
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Publication number: 20150084703
    Abstract: An oscillator and a method of fabricating the oscillator are described. The oscillator includes a resonator with a plurality of transmission lines. An oscillation frequency of the oscillator is independent of at least one dimension of the plurality of transmission lines. The oscillator also includes a negative resistance circuit coupled to the resonator that cancels internal loss resistance of the resonator.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Mihai A. Sanduleanu, Bodhisatwa Sadhu
  • Patent number: 8957736
    Abstract: The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 17, 2015
    Inventor: Akira Takizawa
  • Patent number: 8952760
    Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 10, 2015
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Shing Yu, Chia-Hsiang Chang, Ting-Hao Wang
  • Patent number: 8937512
    Abstract: A voltage-controlled oscillator is disclosed. The voltage-controlled oscillator includes an inverter circuit configured to output an oscillation signal. The first inverter circuit includes a complementary transistor pair and a transistor string. The complementary transistor pair includes a first switch transistor and a second switch transistor. The second switch transistor is connected to the first switch transistor, in which a first terminal of the second switch transistor is connected to a second terminal of the first switch transistor. The first delaying unit includes at least one delaying transistor. A first terminal of the at least one delaying transistor is connected to a control terminal of the second switch transistor. A second terminal of the at least one delaying transistor is connected to a control terminal of the first switch transistor. A control terminal of the at least one delaying transistor is configured to receive a voltage control signal.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jr Huang, Nan-Hsin Tseng, Wei-Hao Kao, Ping-Han Tsai, Wei-Pin Changchien
  • Patent number: 8928369
    Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 6, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Kent Jaeger, Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed
  • Patent number: 8867671
    Abstract: A conversion circuit (20) for converting a complex analog input signal having an in-phase, I, component and a quadrature-phase, Q, component resulting from frequency down conversion of a radio-frequency, RF, signal (XRF) to a frequency band covering 0 Hz into a digital representation is disclosed. It comprises a channel-selection filter unit (40) arranged to filter the complex analog input signal, thereby generating a channel-filtered I and Q components, and one or more processing units (53, 53a-b). Each processing unit comprises four mixers (60-75) for generating a first and a second frequency-translated I component and a first and a second channel-filtered Q component based on two LO signals with equal LO frequency and a 90° mutual phase shift. Furthermore, each processing unit comprises a combiner unit (85, 120) for generating a first, a second, a third, and a fourth combined signal proportional to sums and differences between said frequency translated I and Q components.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 21, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Lars Sunström, Roland Strandberg
  • Publication number: 20140306772
    Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of out-put signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 16, 2014
    Inventors: Rotem Banin, Ofir Degani, Eran Socher
  • Patent number: 8847691
    Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhi Zhu, Xiaohua Kong, Nam V. Dang
  • Patent number: 8816780
    Abstract: An exemplary calibration apparatus for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes a capturing block arranged to capture phase error samples, and a calibrating block arranged to adjust timing of said edge rotator according to said phase error samples. An exemplary calibration method for calibrating timing mismatch of an edge rotator operating on multiple phases of an oscillator includes the following steps: capturing phase error samples, and adjusting timing of said edge rotator according to said phase error samples.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 26, 2014
    Assignee: Mediatek Inc.
    Inventors: Chi-Hsueh Wang, Robert Bogdan Staszewski
  • Publication number: 20140218120
    Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.
    Type: Application
    Filed: August 29, 2012
    Publication date: August 7, 2014
    Applicant: RAMBUS INC.
    Inventors: Mohammad Hekmat, Farshid Aryanfar, Kambiz Kaviani
  • Patent number: 8797108
    Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: August 5, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Hirashiki, Shinichiro Ishizuka, Nobuyuki Itoh
  • Patent number: 8773182
    Abstract: A stochastic beating time-to-digital converter (TDC) can include triggered ring oscillator (TRO) and a stochastic TDC (sTDC). The TRO, when triggered by a reference signal edge, can generate a periodic TRO signal with a TRO period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The TRO period can be greater than or less than the VCO period by the specified ratio. The sTDC with an event triggered memory can include an sTDC component with a plurality of groups of latches. Each group of latches can be configured to sample and store a VCO state at an edge of a TRO signal. The sTDC component can trigger a capture of a select number of VCO states of the group of latches when one latch in the group of latches transitions to a different digital state referred to as a transition edge.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Ashoke Ravi, Hasnain Lakdawala, Rotem Banin
  • Patent number: 8729972
    Abstract: A phase-shift keying (PSK) demodulator and a smart card including the same are disclosed. The PSK demodulator includes a delay circuit and a sampling circuit. The delay circuit generates a plurality of clock signals by delaying the input signal. The sampling circuit samples the input signal in response to the clock signals, and generates output data.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Jong Song, Sang-Hyo Lee
  • Patent number: 8723609
    Abstract: A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: May 13, 2014
    Assignee: Idustrial Technology Research Institute
    Inventors: Chih-Hsiang Chang, Nai-Chen Cheng, Yu Lee, Ching-Yuan Yang
  • Patent number: 8713345
    Abstract: A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: April 29, 2014
    Assignee: Sony Corporation
    Inventor: Tatsuya Sugioka
  • Patent number: 8680929
    Abstract: The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (?) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (?) equal to zero.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: March 25, 2014
    Assignee: ST-Ericsson S.A.
    Inventors: Gerben W. De Jong, Dennis Jeurissen
  • Patent number: 8674773
    Abstract: In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: March 18, 2014
    Assignee: Fujitsu Limited
    Inventor: Nikola Nedovic
  • Patent number: 8638174
    Abstract: The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator (200) for a mixer of a radiofrequency receiver, the signal generator (200) comprising a bit sequence generator (201) having a plurality of parallel output lines (203), a digital signal generator (202) having a serial output line (204) and a plurality of input lines connected to respective output lines (203) of the bit sequence generator (201) and a clock signal input line (205), wherein the digital signal generator (202) is configured to provide an output bit sequence on the serial output line (204) at a rate given by a clock signal provided on the clock signal input line (205) and a sequence given by a sequence of bits from the bit sequence generator (201) on the plurality of input lines (203).
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: January 28, 2014
    Assignee: Integrated Device Technology inc.
    Inventors: Nenad Pavlovic, Johannes Hubertus Antonius Brekelmans, Jan van Sinderen
  • Patent number: 8610508
    Abstract: A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Nicolas Sornin
  • Patent number: 8610509
    Abstract: A method for generating an oscillator signal uses a multiphase oscillator having a plurality of input stages and a reference stage. Each input stage produces an input stage voltage that represents a phase for the oscillator. The input stage voltages produced by each of the input stages are compared to a reference voltage produced by the reference stage. An input stage having a maximum input stage voltage is selected and an output of the selected input stage having the maximum input stage voltage is changed. A current need of the oscillator is detected with a negative feedback loop coupled to the reference stage. An appropriate supply current is provided to each input stage with the negative feedback loop.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 17, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Behzad Mohtashemi, Allen Chang
  • Publication number: 20130278344
    Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 24, 2013
    Applicant: MStar Semiconductor, Inc.
    Inventor: Jian-Yu Ding
  • Patent number: 8508309
    Abstract: A wideband phase modulator comprises a multiphase generator, a phase selector, and a phase adjuster. The wideband phase modulator is configured to receive an N-bit digital phase-modulating signal comprising a timed sequence of N-bit phase-modulating words, where N is a positive integer representing the bit resolution of the N-bit digital phase-modulating signal. The multiphase generator generates a plurality of coarse carrier phases, all having the same carrier frequency but each offset in phase relative to the other. The M most significant bits of the N-bit phase-modulating words are used to form M-bit phase select words that control the output phase of the phase selector. The phase adjuster performs a precision rotation operation, whereby a selected coarse carrier phase is adjusted so that the phase of the resulting final precision phase-modulated signal more closely aligns with a desired precision phase.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 13, 2013
    Inventor: Earl W. McCune, Jr.
  • Patent number: 8487708
    Abstract: An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Isamu Hayashi
  • Patent number: 8456251
    Abstract: An adjustable-frequency oscillator, is formed by two looped systems, functioning at the same frequency but the signals are phase shifted by 90°. Each looped system includes a phase shift device, an active element providing the gain and a resonator having a fixed phase-frequency characteristic. As the phase shift in each loop is imperatively a whole multiple of 2?, the phase shift added in each loop by the phase shift device entails that each resonator introduces a complementary phase shift to comply with the oscillation criterion. This complementary phase shift is produced at a frequency defined by the resonator, this then defining the frequency of oscillation. The frequency is adjusted by two phase shift stages, which carry out the analogue multiplication of the signals coming from the two looped systems by control voltages and the summing of these products.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 4, 2013
    Inventor: Patrick Magajna
  • Patent number: 8456246
    Abstract: A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 4, 2013
    Assignee: National Chung Cheng University
    Inventors: Shuenn-Yuh Lee, Liang-Hung Wang, Yu-Heng Lin
  • Patent number: 8436689
    Abstract: A voltage controlled oscillator includes a resonant circuit including one or more transformers and a plurality of variable capacitor circuits connected in parallel to the one or more transformers and generating a plurality of oscillation signals having multiple phases, and a negative resistance circuit including a plurality of transistors cross-coupled via the one or more transformers and generating negative resistance for maintaining the oscillation of the resonant circuit.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: May 7, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventor: Young Jae Lee
  • Publication number: 20130088301
    Abstract: The present invention is directed to an oscillator circuit comprising an oscillator input for providing an input signal, a first integrator circuit comprising a first integrator capacitor and a first integrator output, a comparator, a discharge circuit for discharging said first integrator capacitor once per cycle of said oscillator circuit, and an oscillator output for providing an output signal, wherein said oscillator circuit further comprises a second integrator circuit comprising a second integrator capacitor and a second integrator output, and wherein said oscillator circuit is arranged for allowing said input signal to be subsequently integrated by said first and second integrator circuit in an alternating manner, and for providing said integrated output signal of said first and second integrator circuit subsequently to said comparator in said alternating manner.
    Type: Application
    Filed: November 10, 2010
    Publication date: April 11, 2013
    Applicant: ANAGEAR B.V.
    Inventors: Petrus Johannes Maria Kamp, Hermanus Johannes Nijrolder
  • Patent number: 8410858
    Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: April 2, 2013
    Assignee: Analog Devices, Inc.
    Inventor: John Wood
  • Patent number: 8378754
    Abstract: Multiple multi-stage delay circuits each have n (n is an integer) output terminals. The multi-stage delay circuits each apply delay times to a corresponding input signal, and output, via n output terminals, n delayed signals to which different delay times have been applied. Multiple inverters invert the respective input signals. The multiple multi-stage delay circuits and multiple inverters are alternately connected in the form of a ring.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: February 19, 2013
    Assignee: Advantest Corporation
    Inventor: Kazuhiro Yamamoto
  • Patent number: 8373512
    Abstract: A signal generator provides a plurality of oscillating signals, whereby each oscillating signal has a different peak voltage and has a predictable and consistent phase relationship with the other oscillating signals. The signal generator includes a plurality of stacked oscillators arranged between two reference voltages, such that each oscillator in the stack generates an oscillating signal having a different peak voltage. Each oscillator stage in a designated oscillator includes a transistor that is connected to a transistor of a corresponding stage in another oscillator. This arrangement of the oscillators provides for charge transfer between the corresponding stages to provide for similar voltage swings in each oscillating signal, as well as to provide for predictable phase relationship between the oscillating signals.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: February 12, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Visvesh S. Sathe
  • Patent number: 8358175
    Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: January 22, 2013
    Assignee: NXP B.V.
    Inventors: Kevin Mahooti, Sanket Gandhi, Min Ming Tarng
  • Patent number: 8319563
    Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: November 27, 2012
    Assignee: Fmax Technologies, Inc.
    Inventor: Iain Ross Mactaggart
  • Publication number: 20120249250
    Abstract: According to embodiments of the present invention, a quadrature voltage controlled oscillator is provided.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 4, 2012
    Inventors: Kuang-Wei Cheng, Minkyu Je
  • Patent number: 8274338
    Abstract: A method is provided for generating local oscillator signals for a mixer. The method includes providing a reference frequency signal and generating a differential in-phase signal and a differential quadrature signal from the reference frequency signal. The method further includes re-clocking each of the differential in-phase and differential quadrature signals using the reference frequency signal. The re-clocked differential in-phase and differential quadrature signals are then provided as the local oscillator signals for the mixer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 25, 2012
    Assignee: NXP B.V.
    Inventors: Frank Harald Erich Ho Chung Leong, Olivier Aymard
  • Patent number: 8253501
    Abstract: The present invention concerns a device having a first and a second differential oscillators (1, 2; 1?2?) coupled to and in quadrature-phase with each other, comprising first and second resonant electronic means (L1, C1, C2; L2, C3, C4) respectively, which are apt to provide, respectively on first two and second two terminals (NODE—1, NODE—2; NODE—3, NODE 4), first two and second two oscillating signals (VNODE—1, VNODE—2; VNODE—3, VNODE—4), said first two oscillating signals (VNODE—1, VNODE—2) being in phase opposition to each other and in quadrature-phase with said second two oscillating signals (VNODE—3, VNODE—4), the device being characterised in that it comprises first generator electronic means (M13-M24) apt to detect first instants of passage through a first reference value of each one of said first oscillating signals (VNODE—1, VNODE—2) and to generate first power supply pulses for said second resonant electronic means (L2, C3, C4) in second instants, and in that it comprises second generator electroni
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: August 28, 2012
    Assignee: Universita Degli Studi di Roma “La Sapienza”
    Inventors: Adriano Carbone, Fabrizio Palma
  • Patent number: 8232843
    Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 31, 2012
    Assignee: STMicroelectronics International N.V.
    Inventor: Prashant Dubey
  • Patent number: 8232848
    Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takahiro Kato
  • Patent number: 8217725
    Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Limited
    Inventor: Masafumi Kondou
  • Patent number: 8212625
    Abstract: Provided are a differential voltage-controlled oscillator (VCO) and a quadrature VCO using center-tapped cross-coupling of a transformer. The differential VCO and the quadrature VCO can be driven by low power through a current reuse structure and have an excellent phase noise characteristic by center-tapped cross-coupling through a transformer. Further, variable capacitance units for frequency variation are divided into variable capacitance units for coarse tuning and variable capacitance units for fine tuning. Therefore, it is possible to obtain a wide tuning range while voltage oscillation gain is reduced. Further, the differential VCO and the quadrature VCO are configured in such a manner that the respective variable capacitance units operate linearly throughout the entire capacitance region due to control voltage distribution by resistors. Accordingly, it is possible to obtain a linear control voltage-oscillation frequency characteristic.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 3, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young Jae Lee, Cheon Soo Kim
  • Patent number: 8198945
    Abstract: The present invention relates to an oscillator circuit and a method of controlling the oscillation frequency of an in-phase signal and a quadrature signal. First oscillator means (2) with a first differential oscillator circuit and a first differential coupling circuit are provided for generating the quadrature signal. Furthermore, second oscillator means (4) with a second differential oscillator circuit and a second differential coupling circuit are provided for generating the in-phase signal. A frequency control means is provided for varying the oscillation frequency of the in-phase signal and the quadrature signal by controlling at least one of a common-mode current and a tail current of the first and second oscillator means. Thereby, a high-frequency IQ oscillator with high linearity is obtained.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: June 12, 2012
    Assignee: NXP B.V.
    Inventors: Mihai A. T. Sanduleanu, Eduard F. Stikvoort
  • Patent number: 8198923
    Abstract: The invention includes a harmonic suppression circuit, an injection-locked frequency divider circuit (ILFD) and associated methods. The harmonic suppression circuit comprises a source voltage, two suppression modules, two input terminals, two smoothed output terminals and a ground. The ILFD comprises a ground, an input transistor, an input terminal, two divider legs, two output terminals and a source voltage. The associated method to improve harmonic suppression comprises acts of synthesizing differential-phase signals and simultaneously suppressing second harmonics of in-phase signals. The method to extent an ILFD's locking range comprises acts of decreasing quality factor while keeping resonance frequency constant.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: June 12, 2012
    Assignee: National Taiwan University
    Inventors: Shey-Shi Lu, Hsien-Ku Chen