Abstract: The oscillating unit 11 generates a signal having a frequency of n*f, i.e., n times a target frequency f. The control voltage generation circuit 21 compares the phase difference between a divided signal of a signal generated in the oscillating unit 11 and the reference signal, and outputs a DC control voltage according to the phase difference to the oscillating unit 11, thereby controlling an oscillation frequency. The divider circuit 22 converts a signal generated in the oscillating unit 11 to the target frequency f, by dividing the aforementioned signal into n equal units. By setting the oscillation frequency of the oscillating unit at n times the target frequency, the inductance and the capacitors can be formed on a semiconductor integrated circuit board.

Abstract: The waveform generator includes a free-running ring oscillator, and algebra module, a switching module and an output module. The free-running ring oscillator includes a plurality of delay elements connected in a loop and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module generates an output signal indicating a first rising edge of the arbitrary waveform in response to an input signal. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication with the free-running ring oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of free running ring oscillator taps in response to the signal indicative of a first rising edge received at the switch input port.

Abstract: Voltage controlled oscillator (“VCO”) circuitry includes LC tank or ring VCO circuitry and frequency divider circuitry that divides the frequency output by the oscillator circuitry by a selectable integer factor that is at least 2 in the case of a ring oscillator or at least 4 in the case of an LC tank oscillator. This arrangement allows the oscillator circuitry to operate at frequencies that are higher than the desired final output frequencies, which has such advantages as reducing the size and power consumption of the oscillator circuitry, and allowing the circuitry as a whole to have a wide range of operating frequencies while reducing the frequency range over which the oscillator circuitry may be required to operate.

Abstract: An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signal. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Abstract: A quadrature signal generator capable of phase-tuning with respect to all of four generated quadrature signals. The quadrature signal generator includes four phase tuning units each having two input terminals, one receiving a differential signal, the other being grounded, and changing a phase of the differential signal to thereby generate quadrature signals. Accordingly, it is possible to tune phases of all the four generated quadrature signals. It is also possible to prevent the amplitude of quadrature signals from being deviated from a reference value.

Abstract: A ring oscillator and a phase error calibration method are provided. The ring oscillator may include a first voltage-current converter for controlling and outputting an amount of tail current Itail according to a magnitude of a first control voltage applied in feedback in a PLL circuit; a second voltage-current converter for controlling and outputting an amount of shift current according to a magnitude of a second control voltage applied from a system phase error detector; and differential amplifiers for controlling, for output signals, a delay time of signals based on the applied tail current amount and a shift time of the signals based on the shift current amount. Thus, a phase relation between in-phase and quadrature-phase signals outputted from the ring oscillator may be controlled.

Abstract: A pulse width modulation circuit comprises a multiphase clock generation section which generates multiphase clock signals based on a reference clock, and a pulse width modulation signal generation section which generates pulse width modulation signals based on input data and on multiphase clock signals generated by the multiphase clock generation section. The multiphase clock generation section has a phase-locked loop circuit and a clock selection circuit which selects an arbitrary clock signal from among the multiphase clock signals and outputs the selected clock signal to the phase-locked loop circuit as a feedback clock.

Abstract: A tail-tank coupling technique combines two complementary differential LC-VCOs to form a quadrature LC-VCO. The technique reduces phase noise by providing additional energy storage for noise redistribution and by cancelling noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum 1+?, similar to a differential LC-VCO driven by an ideal noiseless current source. However, its figure-of-merit is higher, due to the absence of voltage head-room being consumed by a current source. The optimal ratio of tail-tank capacitor to main-tank capacitor for minimizing phase noise is approximately 0.5. The method can be extended to combine any even number of LC tanks resonating at fo and 2fo to form an integrated oscillator producing quadrature phase at frequency fosc and differential output at 2fosc.

Abstract: A quartz oscillator for quadrature modulation has a quartz oscillating circuit including a transistor, a quartz oscillator, a capacitor, and a resistor, a double-mode quartz filter, a reactance element, and an amplifier. The quartz oscillator is constituted so that an output of the quartz oscillating circuit is a first output, and its output is connected to one terminal of the double-mode quartz filter where a common electrode is grounded. The reactance element is connected in parallel between the other terminal and the ground, and a second output is obtained from a connected point via the amplifier.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: A quadrature voltage controlled oscillator having low phase noise and excellent output swing characteristics includes a first voltage controlled oscillator for outputting a positive in-phase output signal and a negative in-phase output signal; a second voltage controlled oscillator for outputting a positive quadrature-phase output signal and a negative quadrature-phase output signal, the second voltage controlled oscillator having a symmetrical structure with the first voltage controlled oscillator and constituting a feedback loop together with the first voltage controlled oscillator; a first constant current source for supplying constant current to the first voltage controlled oscillator in response to the output signals; and a second constant current source for supplying constant current to the second voltage controlled oscillator in response to the output signals.

Abstract: A clock synthesis circuit) including a phase-locked loop and one or more frequency synthesis circuits is disclosed. The phase-locked loop includes a voltage-controlled oscillator (VCO) having a sequence differential stages o produce equally spaced clock phases. The frequency synthesis circuit includes a sequence of adder-and-register units that select one of the VCO clock phases. An output multiplexer receives each of the selected clock phases, and selects among these clock phases in sequence; the output of the multiplexer is applied to a first toggle flip-flop that changes state in response to rising edge transitions at the output of the multiplexer. A second toggle flip-flop is clocked by the output of the first toggle flip-flop, itself toggling in response to rising edge transitions at the output of the first toggle flip-flop. One or more additional flip-flops can be similarly connected in sequence.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The first voltage-control oscillator circuit includes a first LC tank and a first inductor assembly unit. The second voltage-control oscillator circuit includes a second LC tank and a second inductor assembly unit. A mutual inductance effect is generated between the inductors of the first voltage-control oscillator and the inductors of the second voltage-control oscillator.

Abstract: Circuits, methods, and apparatus that provide a sequential start-up of outputs of an oscillator following a power-up or restart. The outputs are gated by enable signals. These enable signals are derived sequentially, the first in a series being triggered by a specific output of the oscillator.

Abstract: Provided is a quadrature voltage controlled oscillator having only one resonant mode characteristic. The quadrature voltage controlled oscillator has a structure in which two clocks generated from respective LC resonant circuits are 90 degrees out of phase with each other using a phase detector and a loop filter, instead of a general structure in which two LC tank resonant circuits are mutually coupled to constitute an LC quadrature voltage controlled oscillator. The quadrature voltage controlled oscillator includes two resonant circuits having the same oscillation frequency; and a phase controller receiving oscillation clocks of the two resonant circuits to control at least one of oscillation phases of the two resonant circuits according to a phase difference between the two oscillation clocks.

Abstract: To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave oscillating circuit has two triangular wave generating circuits 10A and 10B for generating two phased triangular waves A and B with phases opposite each other, a middle point potential fixing element 20 that always fixes the middle point potential of the output voltage A and B of the two triangular wave generating circuits 10A and 10B at a fixed value, and a mode switching element 30 that instantly switches the output voltage generation mode (up-slope waveform mode/down-slope waveform mode) in the two triangular wave generating circuits 10A and 10B at a preset reference wave crest value level.

Abstract: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to the first self-resonant body.

Abstract: A voltage controlled oscillator unit is provided with cross coupled voltage controlled oscillators to generate quadrature phases. One control stage adjusts coupling between the oscillators. Another control stage adjusts the tail current that applies operating bias to the oscillators and to the couplers, respectively. The cross coupling and tail current control stages are arranged so that tuning one simultaneously and oppositely tunes the other for simultaneous adjustment in opposite directions. This limits the power consumption of the oscillator unit throughout the range of frequency control.

Abstract: An oscillator for ensuring the phase relationship between two resonant circuits coupled by a coupling circuit. A first resonant circuit outputs two signals having different phases, and a second resonant circuit outputs two signals having different phases. The coupling circuit includes a plurality of inverters connected in a ring manner, and couples the first resonant circuit and the second resonant circuit such that the two signals output from the first resonant circuit and the two signals output from the second resonant circuit have different phases. A filter is connected to the input side of each of the plurality of inverters. With this structure, a signal output from each of the plurality of inverters has either a phase lead or a phase lag according to the phase characteristics of the corresponding filter, and thus the phase relationship between the first resonant circuit and the second resonant circuit is ensured.

Abstract: A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: There is provided an oscillator for generating an oscillating signal having desired frequency, having a reference oscillating section for generating a reference signal having predetermined frequency, a plurality of first variable delay circuits, connected in cascade, for receiving the reference signal and outputting the received reference signal by sequentially delaying by almost equal values of delay, a phase comparing section for comparing phase of the reference signal generated by the reference oscillating section with phase of a delay signal outputted out of a final stage of the plurality of first variable delay circuits, a delay control section for controlling a value of delay of the plurality of first variable delay circuits so that the phase of the reference signal becomes almost equal to the phase of the delay signal outputted out of the final stage of the plurality of first variable delay circuits and a frequency adding circuit for generating the oscillating signal in which edges of the respective in

Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.

Abstract: A multiphase voltage controlled oscillator includes at least one ring oscillating unit and a resistor ring; the ring oscillating unit is formed by connecting a plurality of phase-delay elements in cascade and the resistor ring is formed by connecting a plurality of resistor elements in cascade; wherein the connecting nodes of each ring oscillating unit are electrically connected to the connecting nodes of the resistor ring such that the ring oscillating unit can generate a plurality of oscillating signals with uniform phase differences.

Abstract: The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

Abstract: Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an operation clock generated by a clock generator at a prescribed time. An output clock generating device outputs output clock time data per the one cycle in accordance with frequency control data. The output clock time data has a value corresponding to a phase of a virtual output clock generated by dividing the operation clock in accordance with the time resolution. A phase difference detecting device detects a difference between phases of the input signal and the virtual output clock, and outputs a phase difference signal in accordance with the detection result. The frequency control device changes the frequency control data in accordance with the phase difference signal.

Abstract: A modulator, comprising an input unit configured to receive a modulating signal, a control unit configured to provide a control signal on the basis of the modulating signal, an oscillating unit configured to provide a plurality of instances of at least two phase components of a carrier frequency signal, a phase selector configure to select, on the basis of the control signal, a combination of the phase component instances so that an output signal representing the information contents of the modulating signal is obtained, and a combiner configured to combine the selected phase component instances to form a modulated output signal.

Abstract: A voltage-controlled oscillator for generating differential output is disclosed. The voltage-controlled oscillator comprises a Colpitts oscillator having a first inductor and a capacitive divider having at least two capacitors connected in series. A varactor is connected in series with the capacitive divider and to a reference voltage, and a second inductor is mutually coupled to the first inductor for providing the differential output. A second inductor is substantially centrally tapped and connected to the reference voltage for providing a substantially balanced output. The operating frequency of the voltage-controlled oscillator is dependent on an applicable potential difference across the varactor.

Abstract: Circuits and methods and for generating oscillator outputs using standard integrated circuit components. The basic circuit generally includes two inverters and a variable capacitor to configure a delay of the circuit input and/or output. The oscillator circuit generally includes a plurality of inverter circuits, at least one of which uses a variable capacitor to adjust a delay between stages, and thereby adjust a frequency of oscillation. Thus, the oscillator outputs may be tuned using a single control voltage. The method generally includes the steps of (1) applying an operating voltage to a ring oscillator comprising a plurality of stages; and (2) applying a control voltage to a variable capacitor coupled to a node between at least two of those stages. The circuits have particular advantage in quadrature oscillators, and may be easily implemented using widely available CMOS technology.

Abstract: An even number phase ring oscillator having at least eight, equally spaced phases. The oscillator includes at least eight stages, defining at least four pairs of stages, with each pair including a first stage and an associated second stage. The first stages are arranged such that an output of a first stage defines a primary input of another first stage, with the output of the first stage of the last pair defining the primary input of the second stage of the first pair. The second stages are arranged such that an output of a second stage defines a primary input of an another second stage, with the output of the second stage of the last pair crossing over the output of the first stage of the last pair and defining a primary input of the first stage of the first pair, thereby defining a closed loop.

Abstract: The oscillator includes: a first oscillator circuit in which first and second transistors cross-connected to each other are connected to a resonant circuit; and a second oscillator circuit in which third and fourth transistors cross-connected to each other are connected to a resonant circuit, wherein a coupling capacitor and coupling resistor are serially provided between a collector terminal of the first transistor and a base terminal of the fourth transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the second transistor and a base terminal of the third transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the third transistor and a base terminal of the first transistor, and a coupling capacitor and coupling resistor are serially provided between a collector terminal of the fourth transistor and a base terminal of the second transistor.

Abstract: The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

Abstract: An oscillator that provides a quadrature output and has a cross-coupled configuration is disclosed. The oscillator generates an output signal having a frequency. Two phase shift circuits, or stages, are activated by a control signal to provide phase shifts within the oscillator. Each phase shift circuit includes poles to provide the phase shift. A pole includes a varactor to tune, adjust or vary the phase shift accordingly.

Abstract: Electronic circuitry for generating and distributing standing wave clock signals. The electronic circuitry includes one or more two-conductor transmission line segments that are interconnected with an odd number of voltage-reversing connections to form a closed loop. A regeneration device is connected between the conductors of the transmission line segments and operates to establish and maintain a standing wave on the loop. At any location on a segment there is a pair of oppositely phase oscillations.

Abstract: A ring oscillator of an even number of stages of inverting/summing amplifiers that adds, to an input of each of the amplifiers, a signal from one such of the amplifiers as to be distant by an even number of stages therefrom, to realize a desired oscillation operation, thereby directly generating signals having phases shifted by 90 degrees from each other. Further, the signals in the ring oscillator are complementary to each other, so that by arranging these signals close to each other in a wiring, it is possible to realize low sensitivity to a mixed external signal.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Abstract: A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m?1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

Abstract: An automatic quadrature phase compensation system comprises an on-chip analog phase sense circuit capable of detecting small differences in quadrature phase error and providing a corresponding DC voltage, a voltage-controlled or programmable phase delay circuit to implement quadrature phase error correction, and a feedback system or compensation engine used to process the sensed error voltage and apply a corresponding correction signal to the adjustable phase delay.

Abstract: A pulse width of a pulse having a nominal pulse width is modulated in accordance with a digital value to be communicated. The number of clock cycles that the modulated pulse width exceeds the nominal pulse width is counted. Various embodiments use a counter to determine the extent that the modulated pulse exceeds the nominal pulse width. The counter is initialized to a value (P) upon detection of a first edge of the extended pulse. The counter is configured to rollover or is reset when the counter reaches a count of P+M, where M represents the nominal pulse width count. In various embodiments, P is zero. The counter is halted upon detection of a second edge of the extended pulse. The resulting count represents the digital data value.

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

Abstract: A ring-type voltage-controlled oscillator with a good duty cycle for use in a PLL frequency synthesizer. The delay cell circuit used in the ring-type VCO comprises two first inverters, two resistance units, and a differential delay circuit. The inverters receive respective differential input signals and generate respective differential signals to resistance units. The differential delay circuit is coupled to the resistance units, generating differential output signals which are a delayed version of the differential input signals. The resistance units have a resistance value adjusted according to a resistance control voltage for controlling the strength of inverters so as to alter the time delay of the first and second differential output signals.

Abstract: A method and an apparatus for scanning a data signal are provided whereby a plurality of scanning signals (P0, P1, P2, P3) delayed successively by a respective phase difference are generated, for example, by a quadrature oscillator (1). A first data signal (D) is scanned with these scanning signals (P0–P3) in order to generate a plurality of second data signals (D0–D3). Because the direction of rotation of the quadrature oscillator (1) can vary, depending on random starting conditions, the direction of rotation is determined by means of phase detectors (4). These phase detectors (4) are preferably connected to the outputs of the clock dividers (3). Depending on the direction of rotation determined, the second data signals (D0–D3) are allocated to output channels (A0–A3) by a change-over unit (6).

Abstract: A turn-round is provided in the middle of a plurality of differential amplifiers A1–A4. A first-stage differential amplifier A1 is provided in close proximity to a final-stage differential amplifier A4 so that distances between adjacent differential amplifiers are substantially equal to each other. With this, signal lines between the differential amplifiers are uniform in length and propagation delays are uniform. As a result, a high single-frequency oscillation signal is output.

Abstract: The invention relates to a method and related circuitry for multiple phase-splitting. The method includes: while generating M output clocks with a same frequency f1 and different phases, generating N reference clocks with a same frequency (M/N)*f1 and different phases (wherein M>N), and triggering (N/M) frequency division using different periods within each reference clock to generate (M/N) output clocks of different phases for each reference clock, such that the M output clocks of different phases are generated from the N reference clocks of different phases.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: Circuits, methods, and apparatus that provide a sequential start-up of outputs of an oscillator following a power-up or restart. The outputs are gated by enable signals. These enable signals are derived sequentially, the first in a series being triggered by a specific output of the oscillator.

Abstract: Techniques are described for slewing a clock frequency of a clock signal from an initial clock frequency to a final clock frequency. An oscillator provides a number of phase outputs. A current frequency divider value is set to an initial frequency divider value, the initial frequency divider value corresponding to the initial clock frequency. A period of a feedback signal is modified through a number of periods from an initial period to a final period, utilizing one or more of the phase outputs. The current frequency divider value is changed when the period of the feedback signal reaches the final period. The modify and change operations are performed until the current frequency divider value reaches a final frequency divider value, where the final frequency divider value corresponds to the final clock frequency.

Abstract: A voltage controlled oscillator includes two gain stages to split the bias current and reduce phase noise.