Abstract: An RTWO apparatus includes an N-phase RTWO (N is an integer greater than or equal to two) and a phase correction circuit. The N-phase RTWO includes a closed-loop transmission line formed as a Moebius strip. The closed-loop transmission line includes N transmission line segments, to which N voltage controlled capacitors are coupled. The N transmission line segments provide N output phases. The phase correction circuit operates to detect phase errors between output phases, and, depending on the detected phase errors, generates N control voltages for controlling the capacitances of the N voltage controlled capacitors. Controlling the capacitances of the N voltage controlled capacitors in this coordinated manner reduces the phase errors among the N output phases, thereby providing a phase accurate multi-phase RTWO output.

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value.

Abstract: A ring oscillator comprises a control circuit for receiving a frequency-selection signal operative to select from at least two ring oscillator frequencies, said control circuit using said control signal to generate a first control signal and a second control signal; a primary chain of an odd number of serially connected NOT gates, said primary chain including a primary switching NOT gate responsive to the first control signal and operative to perform a logical NOT or an IGNORE function on a first oscillating input signal to generate a first output signal; and a secondary chain of serially connected NOT gates, said secondary chain logically parallel to at least said primary switching NOT gate, said secondary chain including a secondary switching NOT gate responsive to the second control signal and operative to perform a logical NOT or an IGNORE function on a second oscillating input signal to generate a second output signal.

Abstract: The present invention concerns a device having a first and a second differential oscillators (1, 2; 1?2?) coupled to and in quadrature-phase with each other, comprising first and second resonant electronic means (L1, C1, C2; L2, C3, C4) respectively, which are apt to provide, respectively on first two and second two terminals (NODE—1, NODE—2; NODE—3, NODE 4), first two and second two oscillating signals (VNODE—1, VNODE—2; VNODE—3, VNODE—4), said first two oscillating signals (VNODE—1, VNODE—2) being in phase opposition to each other and in quadrature-phase with said second two oscillating signals (VNODE—3, VNODE—4), the device being characterised in that it comprises first generator electronic means (M13-M24) apt to detect first instants of passage through a first reference value of each one of said first oscillating signals (VNODE—1, VNODE—2) and to generate first power supply pulses for said second resonant electronic means (L2, C3, C4) in second instants, and in that it comprises second generator electroni

Abstract: A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.

Abstract: A voltage-controlled ring oscillator comprises a ring oscillator having a plurality of differential delay stages for generating signals having a common programmable oscillation frequency with different phases, and a pair of single-sideband mixers coupled to the differential delay stages for producing in-phase and quadrature phase signals having a frequency that is higher than the oscillation frequency.

Abstract: A system for generating a multiple phase clock is provided. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M. Another structure generates multiple phases using a multi-dimensional oscillator including ring oscillators constructed as vertical and horizontal loops with shared elements between the oscillators. A memory system includes a ring oscillator structure with vertical and horizontal loops, the ring oscillator structure receiving an input clock and outputting a multiple phase clock to one or more of a memory controller, memory devices and a memory interface device.

Abstract: A phase-locked method includes: generating a selection signal according to a detection result of a phase/frequency detector (PFD) of a phase-locked loop (PLL); generating a plurality of oscillation signals according to at least a first oscillation signal generated by the PLL, wherein the plurality of oscillation signals respectively correspond to a plurality of phases; and from the plurality of oscillation signals, selecting an oscillation signal as an output signal of the PLL according to the selection signal.

Abstract: A signal generator for generating multiple phases includes a ring oscillator with at least one first adjustable delay stage and at least one second delay stage being serially arranged, wherein an output of the first delay stage is provided for delivering at least one first output phase and an output of the second delay stage is provided for delivering at least one second output phase, and an adjustment circuit for adjusting the delay of the first adjustable delay stage, wherein the adjustment circuit is provided for adjusting the phase relationship between the first output phase and the second output phase by means of setting a first propagation delay for the first delay stage.

Abstract: A multi-phase oscillator is provided. Said multi-phase oscillator includes a plurality of resonator stages series-connected in an ordered closed loop. Each stage is used for providing one or more oscillating voltages corresponding to an oscillating current. The oscillating current includes a natural current that is generated by the stage and one or more injected currents from a previous stage in the closed loop. The oscillating voltages provided by all the stages have substantially the same frequency; on the other hand, the oscillating voltages provided by each stage and the previous oscillating voltages provided by the previous stage have a corresponding phase difference. The oscillator further includes a coupler between each stage and the previous stage; the coupler is used for generating the injected currents according to the previous oscillating voltages.

Abstract: A method for arranging electronic elements is provided. The method is suitable for a set of N electronic elements in which N is an odd number. The set of N electronic elements include a first electronic element subset and a second electronic element subset. The electronic elements of the first electronic element subset are arranged according a first predetermined method and the electronic elements of the second electronic element subset are arranged according to a second predetermined method, wherein the second electronic element subset is adjacent to the first electronic element subset.

Abstract: A digital phase locked loop apparatus includes an input signal time detecting device that detects a phase of an input signal with prescribed time resolution obtained by dividing a cycle of an operation clock generated by a clock generator at a prescribed time. An output clock generating device outputs output clock time data per the one cycle in accordance with frequency control data. The output clock time data has a value corresponding to a phase of a virtual output clock generated by dividing the operation clock in accordance with the time resolution. A phase difference detecting device detects a difference between phases of the input signal and the virtual output clock, and outputs a phase difference signal in accordance with the detection result. The frequency control device changes the frequency control data in accordance with the phase difference signal.

Abstract: An L-C resonant circuit with an adjustable resonance frequency, having a capacitor and a first inductor electrically coupled together and a second inductor magnetically coupled to the first inductor. Additionally, there is a control circuit to sense a signal representing a first current flowing through the first inductor and to force through the second inductor a second current that is a replica of the first current for setting the adjustable resonance frequency of the L-C resonant circuit.

Abstract: A radiation hard design for oscillator circuits and circuits having differential outputs is described. The design includes connecting or otherwise coupling outputs of these circuits to a passive polyphase filter. The passive polyphase filter provides four quadrature outputs that are free of glitches that may have occurred at the filter input.

Abstract: A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.

Abstract: Timing signal generation and distribution are combined in operation of a signal path exhibiting endless electromagnetic continuity affording signal phase inversion and having associated regenerative active means. Two-or more-phases of substantially square-wave bipolar signals arise directly in traveling wave transmission-line embodiments compatible with semiconductor fabrication including CMOS. Coordination by attainable frequency synchronism with phase coherence for several such oscillating signal paths has intra-IC inter-IC and printed circuit board impact.

Abstract: Disclosed are multiphase oscillators comprising a plurality of delay stages serially coupled in a loop by a plurality of nodes, with the loop being folded to provide two concentric rings of delay stages with equal numbers of allocated nodes. A second plurality of negative-resistance elements are provided, each element having a first output coupled to a node on the first concentric ring and a second output coupled to a node on the second concentric ring. Each such output switches between first and second voltage levels, and provides a negative resistance to a signal coupled to it during at least a portion of the transition between voltage levels. The outputs of an element switch to opposite voltage levels. With this construction, a high-voltage pulse propagates around the loop of delay stages, with a low-voltage pulse propagating behind it. Also disclosed are circuits to control the direction of pulse propagation.

Abstract: A system and method of conditioning differential clock signals iteratively adjusts the duty cycles and phases of the clock signals. The duty cycles of the clock signals are adjusted by comparing respective voltage corresponding to the duty cycles of respective clock signals in each of the differential pairs. The result of the comparison is used to adjust the duty cycles of the clock signal until the magnitudes of the voltages are substantially equal. The phases of the clock signals are adjusted by selecting two sets of two clock signals each that are assigned relative phases that differ from each other by the same amount. The selected sets of clock signals are processed so that the duty cycles of resulting signals correspond to the phases of the clock signals. The duty cycle of these signals is measured as described above and used to adjust the phases of the clock signals.

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

Abstract: A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

Abstract: A system for generating local oscillator (LO) signals for a quadrature mixer includes an oscillator configured to provide a reference frequency signal, at least one frequency divider configured to divide the reference frequency signal into three offset phase signals, a first summing circuit configured to generate two nominal 90 degree offset phase signals from the three offset phase signals, and a second summing circuit configured to generate at least two amplitude-corrected 90 degree offset-phase quadrature signals.

Abstract: A PLL circuit includes a polyphase reference clock output circuit, which outputs multiple reference clocks, each clock being of different phase. The PLL circuit further includes a digital voltage controlled oscillator, which, using any one of the multiple reference clocks chosen as an operating clock, outputs an output clock whose frequency varies according to a value of a frequency control signal, and which outputs a delay amount data representing a phase difference between the phase of the output clock and an ideal phase gained by computing based on the value of the frequency control signal. The PLL circuit further includes a selection circuit which is responsive to the delay amount data to select and output the output clock synchronized with one of the multiple reference clocks.

Abstract: Jitterless transition of the programmable clock waveform is generated employing a set of two coupled direct digital synthesis (DDS) circuits. The first phase accumulator in the first DDS circuit runs at least one cycle of a common reference clock for the DDS circuits ahead of the second phase accumulator in the second DDS circuit. As a phase transition through the beginning of a phase cycle is detected from the first phase accumulator, a first phase offset word and a second phase offset word for the first and second phase accumulators are calculated and loaded into the first and second DDS circuits. The programmable clock waveform is employed as a clock input for the RAM address controller. A well defined jitterless transition in frequency of the arbitrary waveform is provided which coincides with the beginning of the phase cycle of the DDS output signal from the second DDS circuit.

Abstract: A clock synthesis circuit includes a polyphase numerically controlled oscillator, an extraction circuit, and a clock signal generation circuit. The polyphase numerically controlled oscillator generates sets of periodic output signals. Each set of the periodic output signals represents a different phase of a periodic waveform signal. The extraction circuit extracts a most significant bit from each set of the periodic output signals of the polyphase numerically controlled oscillator to generate most significant bits. The clock signal generation circuit converts the most significant bits into a serial bit stream that serves as an output clock signal.

Abstract: Embodiments of the invention may provide for an LC quadrature oscillator that includes two LC oscillators that are cross-coupled with each other to generate I/Q clock signals and a phase and amplitude mismatch compensator. The phase and amplitude mismatch detector may include an amplitude mismatch detector, a transconductor, and a capacitor for compensating for both phase and amplitude mismatches between I/Q clock signals generated in the LC quadrature oscillator.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The second voltage-control oscillator circuit and the first voltage-control oscillator circuit have a plurality of inductors, and the inductors in the second voltage-control oscillator circuit are respectively cross-coupled with the inductors in the first voltage-control oscillator circuit to generate a mutual inductance effect, so as to output a plurality of oscillating signals with different phases.

Abstract: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to the first self-resonant body.

Abstract: Various embodiments of the present invention provide systems, circuits and methods that allow for switching between two or more multiphase clocks. As one example, a system for switching between multiphase clocks is disclosed. The system includes a multiphase clock multiplexer. The multiphase clock multiplexer receives a first multiphase clock and a second multiphase clock. The first multiphase clock includes at least a first phase clock and a second phase clock, and the second multiphase clock includes at least a third phase clock and a fourth phase clock.

Abstract: A multi-port correlator and a receiver having the same are provided. A multi-port correlator includes an oscillating unit which generates a plurality of oscillating signals having different phases, a combining unit which combines the plurality of oscillating signals respectively with a radio frequency (RF) signal and outputs a plurality of composite signals.

Abstract: A phase controlling apparatus is disclosed. The phase controlling apparatus controls phases of signals which are output from a plurality of signal sources corresponding to first phase information which indicates a phase of a predetermined signal. The phase controlling apparatus includes a phase information storing section and a phase controlling section. The phase information storing section stores second phase information which indicates a phase of a signal which is output from each of the plurality of signal sources. The phase controlling section changes a phase of a signal which is output from at least one of the plurality of signal sources corresponding to the second phase information stored in the phase information storing means to control the difference of phases of signals which are output from the plurality of signal sources.

Abstract: A quadrature voltage controlled oscillator includes oscillation circuits for generating in-phase and quadrature-phase oscillation signals that are used to generate in-phase and quadrature-phase output signals. A compensation circuit adjusts biasing in the oscillation circuits depending on a phase relationship between the in-phase and quadrature-phase output signals to automatically control the phase relationship between the oscillation signals.

Abstract: A frequency synthesizer according to the present invention digitally controls an analog oscillator to generate an analog output signal at a desired frequency. A digitizing circuit converts a feedback signal derived from the oscillator output signal to a digitized multi-phase feedback signal. A comparator compares the digitized multi-phase feedback signal to a reference signal generated by the reference signal generator to generate an error signal indicative of the phase error in the output signal. A control circuit generates a control signal based on the error signal to control the frequency of the oscillator output signal.

Abstract: Devices (1) for exchanging ultra wide band signals comprise frequency translating stages (20,30) for frequency translating signals and oscillating stages (40) for supplying main inphase/quadrature oscillation signals to the frequency translating stages (20,30). By providing the oscillating stages (40) with polyphase filters (43,44) for reducing harmonics in oscillation signals, the main oscillation signals will be sufficiently clean. The oscillating stages (40) comprise mixers (46) for converting first inphase/quadrature oscillation signals and second inphase/quadrature oscillation signals into the main oscillation signals. The polyphase filters (43,44) may be located before and after the mixers (46). Frequency selectors (45) replace prior art multiplexers located after the mixers (46).

Abstract: A system and method for synchronizing an oscillator with multiple phases at a desired phase angle difference. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The various phases may have different inherent frequencies that are synchronized to a common frequency such as an average of the different frequencies.

Abstract: A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.

Abstract: A multi-phase voltage-control oscillator including a first voltage-control oscillator circuit and a second voltage-control oscillator circuit is provided. The first voltage-control oscillator circuit includes a first LC tank and a first inductor assembly unit. The second voltage-control oscillator circuit includes a second LC tank and a second inductor assembly unit. A mutual inductance effect is generated between the inductors of the first voltage-control oscillator and the inductors of the second voltage-control oscillator.

Abstract: An oscillator is described. The oscillator includes segments of two-conductor transmission line being connected together by an odd number of connection means to form a closed loop. A plurality of current switches is connected to the conductors of the segments and a high impedance element, such as an inductor or transmission line, is connected to a conductor of at least one segment. The high impedance element sources current into the closed loop and the current switches sink current from one or the other of the conductors of the loop depending on the state of the switch. The switches cause a wave to be established and maintained on the loop and the wave changes the state of the switches as it oscillates. One embodiment of the switches employs npn transistors whose emitters are connected to a current source and another uses NMOS transistors.

Abstract: A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

Abstract: A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

Abstract: A harmonic-rejection modulation device is provided, which includes a phase splitter, a low pass filter, and a modulator. Based on a square wave, the phase splitter generates a plurality of unfiltered local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The low pass filter filters the high frequency components of the unfiltered local oscillating signals to generate a plurality of local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The modulator modulates a baseband signal with the local oscillating signals, wherein the third harmonics of the local oscillating signals are eliminated by the modulation process of the modulator. The invention also provides a method of modulating a baseband signal.

Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: Apparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input.

Abstract: An element for interacting with electromagnetic radiation is disclosed, including a first self-resonant body, a second self-resonant body, and a directional device interposed between the first self-resonant body and the second self-resonant body. The directional device is adapted to inhibit propagation of electromagnetic radiation from the second self-resonant body to the first self-resonant body.

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract: A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A radiation hard design for oscillator circuits and circuits having differential outputs is described. The design includes connecting or otherwise coupling outputs of these circuits to a passive polyphase filter. The passive polyphase filter provides four quadrature outputs that are free of glitches that may have occurred at the filter input.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract: An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Abstract: A multi-phase clock generator for generating a set of multi-phase clock signals is disclosed. The multi-phase clock generator includes a signal generator, a phase adjusting circuit, and a phase interpolator. The signal generator generates a plurality of first clock signals according to a reference clock signal. The phase adjusting circuit, which is a phase rotator or a phase selecting circuit and coupled to the signal generator receives the first clock signals and adjusts the phases of the first clock signals according to a control signal to generate a plurality of second clock signals. The phase interpolator, which is coupled to the phase adjusting circuit, interpolates the second clock signals to generate the set of multi-phase clock signals.

Abstract: Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and ?90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller.