Oscillator Used To Vary Amplitude Or Frequency Of Another Oscillator Patents (Class 331/47)
  • Patent number: 9600023
    Abstract: A method for providing a timestamp in a real-time system, whereby the real-time system has an FPGA and a CPU, which cooperate with one another, and at least one register, which contains a system time, is implemented in the FPGA. The method includes the steps of providing a CPU counter for the system time, which is driven by a clock signal of the CPU, providing a synchronization counter in the CPU, whereby the synchronization counter is driven by a clock signal of the CPU, reading of the counter for providing the system time by a real-time application, querying the synchronization counter in the real-time application, and synchronizing the counter with the system time in the real-time application, when the synchronization counter outputs a value that corresponds to more than a predefined time period since the last synchronization of the CPU counter with the system time.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: March 21, 2017
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Ralf Grosse Boerger, Marco Schmidt
  • Patent number: 9461636
    Abstract: Techniques and architecture are disclosed for improving spurious performance in a signal generator/system. The disclosed techniques/architecture can be used, for example, to enhance/improve the wideband and/or narrowband spurious free dynamic range (SFDR) between a given carrier signal and spurious signals. In some example instances, wideband and/or narrowband SFDR may be improved to about ?40 dBc or better. In some other example instances, wideband and/or narrowband SFDR may be improved to about ?70 dBc or better. The disclosed techniques/architecture can be implemented in a wide variety of signal generators/systems, such as a direct digital synthesizer (DDS)-based system, and over a wide range of input clock frequencies (e.g., in the range of about 10 MHz to 40 GHz, or higher).
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: October 4, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Robert Ensinger, David M. Gillespie
  • Patent number: 9356608
    Abstract: A method and system are provided for reducing mismatch between oscillators in an LC VCO array. In an implementation, a method comprises measuring the mismatch between the driver strengths, by measuring the corresponding oscillation amplitudes, and a mismatch between the resonance frequency of each LC VCO in the array of VCOs, and adjusting each LC VCO to reduce the measured amplitude and frequency mismatches. In an implementation, the measuring and adjusting is performed once to calibrate the array of VCOs. In another implementation, the system measures and adjusts the array of VCOs repeatedly. In another implementation, the LC VCO array has a master VCO and a plurality of slave VCOs connected to the master VCO by slave PLLs to reduce phase noise caused by mismatches.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: May 31, 2016
    Assignee: Microsemi Storage Solutions (U.S.), Inc.
    Inventors: Mark Hiebert, Srinivasa Rao Madala, Hormoz Djahanshahi
  • Patent number: 9041478
    Abstract: An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: May 26, 2015
    Assignee: ANHARMONIC B.V.
    Inventor: Antonius Johannes Maria Montagne
  • Patent number: 9035705
    Abstract: An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 19, 2015
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Ola Bruset, Tor Oyvind Vedal
  • Patent number: 9024693
    Abstract: A crystal-less clock generator (CLCG) and an operation method thereof are provided. The CLCG includes a first oscillation circuit, a second oscillation circuit, and a control circuit. The first oscillation circuit is controlled by a control signal for generating an output clock signal of the CLCG. The second oscillation circuit generates a reference clock signal. The control circuit is coupled to the first oscillation circuit for receiving the output clock signal and coupled to the second oscillation circuit for receiving the reference clock signal. The control circuit is used to generate the control signal for the first oscillation circuit according to the relationship between the output clock signal and the reference clock signal.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jen-Chieh Liu, Chi-Yang Chang, Yo-Hao Tu, Kuo-Hsing Cheng
  • Patent number: 9013240
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 9000852
    Abstract: Aspects of the disclosure provide a circuit. The circuit includes a signal amplifying circuit coupled with a crystal component of a natural frequency to form a crystal oscillator, and a signal generator circuit configured to generate a signal with an energy distribution about the natural frequency, and to provide the signal to the crystal oscillator to assist the crystal oscillator to begin oscillating.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 7, 2015
    Assignee: Marvell International Ltd.
    Inventors: Dennis Sinitsky, Junshi Qiao, Pei Wang, Song Chen, Haiqing Zhang, Tao Shui
  • Patent number: 9000849
    Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: April 7, 2015
    Assignee: Oracle International Corporation
    Inventors: Suwen Yang, Frankie Y. Liu
  • Patent number: 8981854
    Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8975973
    Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 10, 2015
    Assignee: Panasonic Corporation
    Inventor: Junji Sato
  • Patent number: 8975969
    Abstract: Disclosed are control systems, and more specifically control systems which benefit from a long-gate time for measurement and a rapid sample time to enhance responsiveness and methods and systems for utilizing multiple-staggered, overlapping gates where the gate time is an integer multiple of the time between ends of adjacent gates. The system continuously counts at the wavefronts or zero-crossings of a frequency reference signal and temporarily records them in registers and compares the contents of registers separated by a gate time and outputs a sample after every sample time.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 10, 2015
    Assignee: Rockwell Collins, Inc.
    Inventors: Michael C. Meholensky, Vadim Olen, Adrian A. Hill, Paul L. Opsahl
  • Patent number: 8947169
    Abstract: An oscillating device includes an atomic oscillator, an oven controlled crystal oscillator, a correcting unit configured to correct an output signal of the oven controlled crystal oscillator on the basis of an output signal of the atomic oscillator, a housing configured to house the atomic oscillator and the oven controlled crystal oscillator, and a temperature adjusting unit configured to adjust the temperature in the housing to a predetermined temperature.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: February 3, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Tomohiro Tamura, Yoshiyuki Maki, Noriaki Tanaka
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8902529
    Abstract: An oscillator is disclosed comprising a first crystal operable to generate a first oscillating signal at a first frequency, and a second crystal coupled to the first crystal and operable to generate a second oscillating signal at a second frequency higher than the first frequency. The oscillator further comprises a DC restore circuit operable to generate a third oscillating signal comprising a substantially fifty percent duty cycle in response to the second oscillating signal.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 2, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: George J. Bennett
  • Patent number: 8901983
    Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator configured to generate an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of temperature, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Micro Crystal AG
    Inventors: David Ruffieux, Nicola Scolari
  • Patent number: 8902007
    Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8896385
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: November 25, 2014
    Assignee: Sand 9, Inc.
    Inventors: Klaus Juergen Schoepf, Reimund Rebel, Jan H. Kuypers
  • Patent number: 8896359
    Abstract: The temperature compensated timing signal generator comprises a crystal oscillator that generates a reference time signal, and a divider circuit that receives the reference time signal as input and outputs a coarse time unit signal, the coarse time unit signal having an actual frequency deviating from a desired frequency as a function of temperature of the crystal oscillator. The signal generator also includes a high frequency oscillator that generates an interpolation signal having a frequency greater than the frequency of the crystal oscillator. A finite state machine computes a deviation compensating signal as a function of the temperature signal, the signal comprises an integer part representative of an integer number of pulses to be inhibited or injected in the divider circuit and a fractional part representative of how much the output of a new time unit signal pulse should further be delayed to compensate for any remaining deviation.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Micro Crystal AG
    Inventors: David Ruffieux, Nicola Scolari
  • Publication number: 20140266474
    Abstract: A MEMS resonator system comprises a MEMS resonator, kick start circuitry, feedback circuitry, an oscillator, and a switch. The MEMS resonator system is configured to provide a pulsed kick-start signal having a frequency and period such that energy delivered to the MEMS resonator is optimized in a short period of time, resulting is reduced oscillator startup time. The MEMS resonator system is configured to switch out the kick-start signal when the MEMS resonator oscillation has been achieved, and switch in feedback circuitry to maintain the MEMS resonator in a state of oscillation.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Mark E. Schlarmann, Deyou Fang, Keith L. Kraver
  • Patent number: 8816777
    Abstract: A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 26, 2014
    Inventor: Tomany Szilagyi
  • Patent number: 8798198
    Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment for receiving an amplitude-modulated calibration signal from the electronic device. The calibration system may include calibration computing equipment for extracting pre-distortion coefficients from the amplitude-modulated calibration signal. The calibration computing equipment may be configured to detect a bulk phase drift in the amplitude-modulated calibration signal. The calibration computing equipment may be configured to remove the bulk phase drift from the amplitude-modulated calibration signal. The wireless communications circuitry may include a power amplifier that distorts a signal generated by the wireless communications circuitry. The wireless communications circuitry may include a pre-distortion compensator for countering the distortion.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventor: Gary Lang Do
  • Patent number: 8779865
    Abstract: A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: July 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, John F. Bulzacchelli, Daniel J. Friedman, Ankush Goel, Alexander V. Rylyakov
  • Patent number: 8638175
    Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: January 28, 2014
    Assignee: STMicroelectronics International N.V.
    Inventor: Prashant Dubey
  • Patent number: 8630382
    Abstract: Embodiments of data recovery apparatus include oscillators, edge detection circuitry, and data storage. The oscillators generate data detection signals, which convey first series of pulses during time periods for which a serial bit stream conveys a logical 1, and second series of pulses during time periods for which the serial bit stream conveys a logical 0. The edge detection circuitry detects transition edges of the first and second series of pulses, and generates data storage signals that include first indications of detected transition edges in the first series of pulses and second indications of detected transition edges in the second series of pulses. In response to receiving a first indication, a logical 1 is written into an unmasked subset of data storage bit locations. In response to receiving a second indication, a logical 0 is written into the unmasked subset of bit locations.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: January 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: John R. Oakley, Uday Padmanabhan, Samir J. Soni
  • Patent number: 8624679
    Abstract: The proper operation of a phase locked loop is determined by monitoring certain signals within the loop for their phase relationship or duty cycle. If a malfunction of the loop is detected, proper operation may be imposed or restored by resetting a phase-frequency detector, or by flipping the output of the phase-frequency detector.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: January 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Abhinav Kumar Dikshit, Gadam Chetty Deva Phanindra Kumar, Anjan Kumar Krishnaswamy
  • Patent number: 8618887
    Abstract: A spread spectrum oscillator includes a high frequency oscillator circuit configured to oscillate at a first frequency, and a low frequency oscillator circuit configured to oscillate at a second frequency and resistively coupled to a current summing node of the high frequency oscillator circuit. The first frequency is higher than the second frequency.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: December 31, 2013
    Assignee: Hamilton Sundstrand Corporation
    Inventor: John A. Dickey
  • Patent number: 8610508
    Abstract: A signal generator for generating an output signal with a frequency that is a multiple of a frequency of a reference signal, the signal generator including an oscillator configured to generate the output signal in dependence on the reference signal and a control signal and a control circuit configured to generate the control signal to comprise a series of pulses in which one or more of the pulses is offset in phase relative to the reference signal, the control circuit thereby being capable of controlling the frequency and/or phase of the output signal.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 17, 2013
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Nicolas Sornin
  • Patent number: 8570108
    Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ashwin Ragunathan, Marzio Pedrali-Noy, Sameer Wadhwa
  • Patent number: 8564375
    Abstract: In one general aspect, an apparatus can include a reference oscillator counter circuit configured to produce a reference oscillator count value based on a reference oscillator signal, and a target oscillator counter circuit configured to produce a target oscillator count value based on a target oscillator signal where the target oscillator signal has a frequency targeted for calibration against a frequency of the reference oscillator signal. The apparatus can include a difference circuit configured to calculate a difference between the reference oscillator counter value and the target oscillator counter value, and a summation circuit configured to define a trim code based on only a portion of bit values from the difference.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: October 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John R. Turner, Tyler Daigle
  • Patent number: 8558624
    Abstract: A semiconductor integrated circuit capable of reliably detecting oscillation stop of a vibrator-type oscillation circuit and reliably restarting the oscillation circuit when oscillation stop is detected is provided. The semiconductor integrated circuit includes one or more main oscillation circuits configured to generate a main clock signal by a vibrator, a ring oscillator configured to always operate independently of the main oscillation circuit, a main clock detection circuit configured to monitor the main clock signal on the basis of an output clock signal of the ring oscillator and to determine an operation state of the main oscillation circuit, and an switch circuit configured to switch a combination of elements making up the main oscillation circuit in response to a detection result of the main clock detection circuit.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: October 15, 2013
    Assignee: Panasonic Corporation
    Inventor: Kazuhisa Raita
  • Patent number: 8552804
    Abstract: An apparatus includes an adjustable oscillator circuit configured to generate an output signal having a frequency that varies responsive to a frequency control signal and a frequency reference generator circuit configured to produce a frequency reference signal. The apparatus further includes a calibration circuit configured to determine a relationship of the output signal to the frequency reference signal and to enable and disable the frequency reference generator circuit based on the determined relationship.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: October 8, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Chenxiao Ren, Tao Jing
  • Patent number: 8525599
    Abstract: Aspects of a method and system for frequency tuning based on characterization of an oscillator are provided. A value of a first control word which controls a variable impedance of an oscillator may be determined. The determined value may be mapped to a corresponding value of a second control word which controls a variable impedance of a tuned circuit. The mapping may be based on a relationship between the variable impedance of the oscillator and the variable impedance of the tuned circuit, such as logical and/or mathematical relationship. The value of the first control word may be determined based on desired frequency of the tuned circuit and/or based on a desired impedance of the variable impedance of the tuned circuit. The tuned circuit may comprise, for example, an oscillator or a filter.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: September 3, 2013
    Assignee: Broadcom Corporation
    Inventor: Ahmadreza Rofougaran
  • Publication number: 20130222069
    Abstract: Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 29, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Arun Paidimarri, Danielle Griffith, Alice Wang
  • Patent number: 8508304
    Abstract: Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 13, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Vishnu Ravinuthula
  • Patent number: 8466751
    Abstract: A precise, low-consumption low-frequency oscillator includes a low-consumption low-frequency oscillator, operating at a frequency FA, a temperature-compensated oscillator B used as frequency standard, operating at a frequency FB, and a circuit for supplying a stable frequency Fcorr.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 18, 2013
    Assignee: Thales
    Inventor: Jean-Pierre Simondin
  • Patent number: 8461934
    Abstract: An IC includes first and second pads. The first pad is configured to receive an external clock. Alternatively, the first and second pads are configured to be coupled to a crystal oscillator and receive a reference clock. Alternatively, the second pad is configured to be grounded. The IC includes an internal oscillator for generating an internal clock, and an oscillator detector coupled to the second pad. The oscillator detector includes a transistor having a gate coupled to the second pad configured to pull a source-drain region to a first state if the second pad receives the reference clock or allow the source-drain region to be pulled to a second state if the second pad is grounded. The IC includes a buffer for transferring the first state to the internal oscillator for keeping the internal oscillator enabled and transferring the second state to the internal oscillator for disabling the internal oscillator.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: June 11, 2013
    Assignee: Marvell International Ltd.
    Inventors: Ovidiu Carnu, Xiaoyue Wang, Shafiq M. Jamal
  • Patent number: 8456246
    Abstract: A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 4, 2013
    Assignee: National Chung Cheng University
    Inventors: Shuenn-Yuh Lee, Liang-Hung Wang, Yu-Heng Lin
  • Patent number: 8456245
    Abstract: One embodiment of the present invention relates to a system that provides a high frequency local oscillator (LO) signal. The system comprises a first LO that generates a first frequency LO signal component, a mixer that generates a difference signal from the first frequency LO signal component and a second frequency LO signal component, and a second LO that generates the second frequency LO signal component that is a harmonic of the difference signal.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: June 4, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Gireesh Rajendran
  • Patent number: 8416025
    Abstract: A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: April 9, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Liang Lin, Chao-Cheng Lee
  • Patent number: 8378751
    Abstract: A frequency synthesizer with multiple tuning loops, e.g., a fine tuning loop and a coarse tuning loop, is described. The fine tuning loop may operate over a limited tuning range and may have fine frequency resolution. The coarse tuning loop may operate over a wide tuning range and may have coarse frequency resolution. The fine tuning loop may receive a reference signal at a reference frequency and generate a fine tuning signal at a first frequency adjustable in fine steps. The coarse tuning loop may receive the reference signal, generate an output signal at an output frequency, and generate a coarse tuning signal at a second frequency based on the output signal and the fine tuning signal. The second frequency may be adjustable in coarse steps, e.g., in integer multiples of the reference frequency. The output frequency may be determined based on the first frequency and the second frequency.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 19, 2013
    Assignee: QUALCOMM Incorporated
    Inventor: Russell John Fagg
  • Patent number: 8358175
    Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: January 22, 2013
    Assignee: NXP B.V.
    Inventors: Kevin Mahooti, Sanket Gandhi, Min Ming Tarng
  • Publication number: 20120286881
    Abstract: An oscillator architecture and a method for powering up/down the oscillator architecture are described. In one embodiment, an oscillator architecture includes a reference generator configured to generate reference signals and an in-phase/quadrature (IQ) oscillator configured to generate oscillation signals based on the reference signals. The reference generator includes a distributed start-up circuitry that includes multiple start-up circuits. The IQ oscillator includes at least one turbo comparator having a low power functional mode and a turbo functional mode. Other embodiments are also described.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 15, 2012
    Applicant: NXP B.V.
    Inventors: KEVIN MAHOOTI, SANKET GANDHI, MIN MING TARNG
  • Patent number: 8306067
    Abstract: The invention discloses a dual frequency multiplexer by which a first and second coaxial harmonic oscillator type band pass filters are disposed in a box. The box includes a base body, a cover plate and a cover body. The two coaxial harmonic oscillator type hand pass filters are located on the base body and spaced each other by a metal plate; the multiplexer port, first and second ports are positioned on lateral side of the base body. The blocking capacitors are contained in the coaxial chamber of the two coaxial harmonic oscillator type band pass filters. The cover plate is secured on the base body; the first and second direct current circuits are placed on the cover plate; the low pass filters of the first and second direct current circuits are fixed on an edge of a top surface of the coaxial chamber by means of a support member; the cover body and the base body are fastened with each other. The blocking capacitors each are of distributed parameter capacitor.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: November 6, 2012
    Assignee: Comba Telecom System (China) Ltd.
    Inventors: Yingjie Di, Tao He, Bin He, Mengmeng Shu, Jingmin Huang
  • Patent number: 8258881
    Abstract: A radio circuit may be driven by a high frequency oscillator such as a crystal oscillator that may have sleep and wake time intervals. The sleep time interval length may be adjusted. A low frequency oscillator or low power oscillator (LPO) that may experience frequency drift may regulate the sleep and/or wake time intervals. The frequency drift may be detected based on two or more LPO calibrations and/or one or more clock adjustments. The LPO frequency drift may be detected based on an LPO frequency sampled after a first LPO calibration and a corresponding LPO clock adjustment, a second LPO frequency sampled after a second LPO calibration and a time interval between the two frequency samples. The LPO may be calibrated based on the HFCXO output. Sleep time intervals may be adjusted by adding and/or subtracting a time interval to an expected time to wake the radio circuit.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: September 4, 2012
    Assignee: Broadcom Corporation
    Inventor: John Walley
  • Publication number: 20120161883
    Abstract: A circuit including a first oscillator configured to oscillate at a first frequency; a second oscillator configured to oscillate at a second frequency, the second frequency being different from and one of a harmonic or sub-harmonic of the first frequency; and a coupling between the first oscillator and the second oscillator configured to injection lock at least one of the first oscillator and second oscillator to the other of the first oscillator and second oscillator.
    Type: Application
    Filed: July 6, 2011
    Publication date: June 28, 2012
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventor: Prashant Dubey
  • Patent number: 8159306
    Abstract: An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: April 17, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Shian-Ru Lin
  • Patent number: 8144249
    Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: March 27, 2012
    Assignee: MStar Semiconductor, Inc.
    Inventors: Cheng Ting Ko, Chung Hsiung Lee
  • Patent number: 8143955
    Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: March 27, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gireesh Rajendran, Debapriya Sahu, Alok Prakash Joshi, Ashish Lachhwani
  • Patent number: RE44097
    Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: March 19, 2013
    Assignee: Psigenics Corporation
    Inventors: Scott A. Wilber, Patrick A. Wilber, Christopher B. Jensen