Abstract: A timer circuit having an oscillator circuit that has low power consumption and a stable frequency of the output signal. Timer circuit 10 has highly stable oscillator 21, counter 22 and frequency dividing value controller 24. Highly stable oscillator 21 generates a standard signal at a prescribed frequency. Counter 22 determines the frequency ratio of the frequency of the internal signal to the frequency of the standard signal, and, corresponding to the frequency ratio, frequency dividing value controller 24 changes the frequency dividing value of frequency divider 12. Because the difference between the frequency of the internal signal and the frequency of the standard signal can be known from the frequency ratio, it is possible to perform control such that the frequency of the output signal is kept stable at a prescribed frequency.

Abstract: A divider circuit including a plurality of latch circuits which are connected in series such that each of the latch circuits is responsive to a control signal to latch data which is output from a preceding latch circuit in the series and a logic circuit which receives the data output from plurality of latch circuits and which outputs a logic operation result to a first latch circuit in the series of the plurality of latch circuits.

Abstract: A system and method for synchronizing a plurality of synchronizable oscillators are disclosed. The method includes monitoring a respective output signal of each synchronizable oscillator, each output signal having a respective frequency, generating a synchronization signal based on the output signal having the highest frequency of all of the output signals, and providing the synchronization signal to all of the synchronizable oscillators.

Abstract: Random pulse generators and generating systems using at least three oscillators. The output signals of at least two of the oscillators are combined to disturb the output signal of a final oscillator. For one configuration, combined output signals of at least two phase shift oscillators are used to modify the feedback signal of a final phase shift oscillator, thus disturbing the output signal of the final oscillator. For another configuration, the output signals of at least two phase shift oscillators are used to drive a subtractor whose output signal is combined with the output signal of a final phase shift oscillator to drive a subsequent subtractor, thus disturbing the output signal of the final oscillator.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: A voltage-controlled oscillator comprises a control terminal applied to a control voltage, first and second output terminals, first and second ring oscillators, first and second output buffer circuits and a latch circuit. Each of the first and second ring oscillators includes an odd number of inverting amplifier circuits connected in series and a transfer gate circuit connected between the inverting amplifier circuits and a resistive element connected in parallel to the transfer transistor. The transfer gate circuit includes a transfer transistor connected between the inverting amplifier circuits. The transfer gate circuit has a control terminal connected to the control terminal. Each of the first and second output buffer circuits has an input connected to the first or second ring oscillator and an output connected to the first or second output terminal. The latch circuit is connected to the first and second ring oscillators.

Abstract: A circuit and method for generating a variable frequency clock signal that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The circuit includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator and outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: A light source device for use in image readout devices capable of light emission in which a dielectric barrier discharge fluorescent lamp is synchronized with an external synchronization signal without attendant fluctuation in optical power. A phase comparator compares the oscillation signal phase of a variable frequency oscillator divided by a frequency divider with an external synchronization signal. The phase comparator controls the oscillation frequency of a variable frequency oscillator as a function of the phase difference. Consequently, the oscillation phase of the variable frequency oscillator is phase locked by the external synchronization signal. The oscillation signal of the variable frequency oscillator is input to the gate signal generation circuit, and the switch devices of an inverter circuit are opened and closed by the output of a gate signal generation circuit.

Abstract: A weighing apparatus includes a SAW oscillator and a “push oscillator” to force the SAW oscillator into a desired mode of operation. A SAW temperature oscillator and a thermistor are also provided. The frequency of the “push oscillator” is made immune to temperature changes by generating it via a mixer mixing the SAW temperature oscillator with an adjustable fixed frequency oscillator. Long term stability of the SAW temperature oscillator is achieved by periodic calibration with the thermistor.

Abstract: A circuit and method for generating a variable frequency clock signal that uses a first, lower frequency oscillator, to modulate and vary the frequency of a second, higher frequency oscillator to generate a variable frequency clock signal. The circuit includes a first oscillator, a control circuit, and a second oscillator. The first oscillator generates a first signal having a substantially fixed-frequency magnitude. The control circuit is coupled to receive the first signal from the first oscillator and outputs control signals based on the received first signal. The second oscillator is coupled to receive the control signals from the control circuit and generates the variable frequency magnitude clock signal in response to the received control signal.

Abstract: A real time clock, suitable for use in mobile units in a radiocommunication system, is calibrated during production, and corrects for timing inaccuracies during normal operation. As a result, the accuracy of the real time clock's crystal oscillator is increased economically and efficiently. Frequency error correction is performed by periodically adjusting the frequency of the real time clock by a fixed amount once for every interval of time defined by an adjustment value. The adjustment value is determined by a calibration procedure performed during manufacture of the mobile unit.

Abstract: A coupled oscillator arrangement is provided comprising first and second VCOs (voltage controlled oscillators), and a bi-directional interconnect which injection locks the first and second VCOs to each other. Advantageously, this provides a mechanism which effectively eliminates the phase jitter between the phase of first and second VCOs which makes them suitable for use in a diversity receiver, while at the same time providing a redundancy arrangement in which the failure of one of the VCOs does not effect the functionality of the other. The use of a bi-directional interconnect minimizes the complexity and cost of coupling the two VCOs. Preferably, the bi-directional interconnect injects a first signal representative of an output signal of the first VCO to the output of the second VCO and injects a second signal representative of an output signal of the second VCO to the output of the first VCO.

Abstract: Two or more equal amplitude periodic output signals which are mutually shifted in phase by an integer fraction of 360 degrees, such as 90°, are generated by injection locking a ring type oscillator circuit arrangement with a periodic low phase noise signal source. More particularly, a first ring oscillator is injection locked by a low phase noise signal source, one having a noise characteristic which meets the GSM radio standard of at least −132 dBc/Hz at a 3 MHz offset. An identical second ring oscillator is then driven with the output of the first ring oscillator. In one circuit configuration, an even numbered, e.g., a four stage ring oscillator is injection locked to a low-phase noise oscillator having a predetermined noise specification which is application specific and wherein a second even numbered stage, e.g., a four stage ring oscillator is coupled to the first ring oscillator. In a second circuit configuration, a first odd numbered, e.g.

Abstract: An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a support layer, a fixed layer positioned on a support layer, remaining portions of a sacrificial layer positioned only on portions of the fixed layer, and an oscillating layer positioned on the remaining portions of the sacrificial layer, overlying the fixed layer in spaced relation therefrom, and extending lengthwise generally transverse to a predetermined direction for defining a released beam for oscillating at a predetermined frequency. The spaced relation is preferably formed by removal of unwanted portions of the sacrificial layer.

Abstract: An oscillation apparatus is provided with a signal input unit for supplying a pulse sequence consisting of pulses sequentially continuously occurred; a state quantity generating unit for generating state quantity having a value which is monotonously increased with the passage of time; a state quantity transition unit for transferring a value of state quantity in the course of generation in said state quantity generating unit to a value changed by a predetermined amount in a varying direction of the value of the state quantity with respect to a present value of the state quantity, whenever one pulse is fed from said signal input unit to said state quantity transition unit; a state quantity reset unit for comparing the present value of the state quantity generated in said state quantity generating unit with a predetermined threshold value, and resetting the present value of the state quantity generated in said state quantity generating unit to a predetermined initial value when the present value reaches the thr

Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.

Abstract: A phase-locked-loop-stabilized voltage controlled oscillator relies on a sampling of the analog-frequency-control voltage of a voltage-controlled oscillator in a phase-locked-loop circuit to act as a reference voltage for a second free-running voltage-controlled oscillator. A vernier-adjustment voltage is injected into the control input of the second voltage-controlled oscillator to produce a finely variable derivative frequency not otherwise producible by a conventional phase-locked-loop circuit.

Abstract: In a method of calibration of a voltage controlled oscillator (VCO), the VCO (100) provides an output signal which is used to drive a dividing oscillator (10) such as a relaxation oscillator (RO). The RO has at least two states, one in which the RO provides an output signal which has a first frequency that is related to the VCO output signal by a first ratio (e.g. 1/N) and one in which the relaxation oscillator provides a RO output signal which has a second frequency that is related to the VCO output signal by a second ratio (e.g. 1/(N+1)). By measuring the first and second frequencies (and knowing the relationship between the first and second ratios), the VCO frequency is calculated and stored (110). Several VCO frequencies can be calculated and stored for several applied voltages. As a result the VCO can be driven to any selected frequency in the calibrated range and can be used to provide an injection frequency for a radio.

Abstract: A circuit for synchronizing transmission local oscillating frequency in a co-channel microwave system, with more reliability, synchronizes horizontal and vertical polarization waves phase locked dielectric resonators which generate transmission local oscillating frequencies in a digital co-channel microwave system.

Abstract: A temperature sensitive oscillator circuit and control circuit which together form a current source. The temperature sensitive oscillator circuit generates an output signal which controls a frequency of a refresh oscillator circuit. The duty cycle of the output signal of the temperature sensitive oscillator circuit is temperature dependent and increases for increases in temperature. The output signal of the temperature sensitive oscillator circuit controls the control circuit which sources current between the refresh oscillator circuit and a supply node. As the duty cycle of the output signal of the temperature sensitive oscillator circuit increases a time duration during which the control circuit sources current between the refresh oscillator circuit and the supply node increases. This increase increases the frequency of the output signal of the refresh oscillator circuit. The output signal of the refresh oscillator circuit is an internal clock signal which controls a refresh cycle of a memory circuit.

Abstract: A circuit arrangement is provided with a controlled switch which is controlled by means of a periodic switching signal for operating an oscillation circuit at a frequency f, and with a control circuit for generating the periodic switching signal. The control circuit comprises a pulse width generator for generating a periodic square wave signal with a half cycle duration which is adjustable in steps of a value T and which has a value of at least t. The circuit arrangement is characterized in that, with 2*(t+N1*T)<1/f<2*(t+(N1+1)*T) in which N1 is an integer number, the periodic switching signal is built up from a repetitive chain of square wave signals with a repetition cycle which comprises n1 half cycles of a duration t+N1*T and n2 half cycles of a duration t+N2*T, wherein N2 is >N1 and is an integer number.

Abstract: A voltage-controlled oscillator, with high noise rejection of the supply voltage, includes a plurality of delay cells in an odd number N.gtoreq.3, which are connected to form a first ring oscillator and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR. The VCO comprises at least one second ring oscillator formed by a plurality of delay cells in an odd number M.gtoreq.3, at least one of which is also a delay cell of the first oscillator and at least two of which do not belong to the first oscillator. At least one of these two cells is powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.

Abstract: A kinetically multicolored light source is described, comprising: a light source capable of producing a plurality of primary colors; oscillatory means for driving said light source; and means for moving said light source. The oscillatory driving means may drive the light source so that one or more of the primary colors is alternately turned on and off at a frequency above the critical fusion frequency of an observer, whereby each of the colors appears to emanate simultaneously and continuously thereby appearing to the observer as a single secondary color when the light source moves slowly with respect to the observer.The light source may move relative to the observer sufficiently rapidly that each of the oscillating primary colors if viewed alone would appear to the observer to emanate from bright segments of a curvilinear path with intervening dark segments.

Abstract: A method and apparatus for producing a temperature stable frequency at reduced cost. Advantage is taken of an existing, relatively temperature insensitive, low frequency and low cost watch crystal and an existing, high frequency, low cost, but relatively temperature sensitive system clock. A calibration module coupled to the watch crystal and clock calibrates the watch crystal to a reference frequency at a reference temperature and calibrates the clock to the watch crystal at an operating temperature, to relate the clock frequency to the reference frequency at any operating temperature and thereby provide a high precision, relatively temperature insensitive time or frequency base at low cost.

Abstract: A circuit for automatically substituting a reference oscillator for synchronizing two transmitter co-channel local oscillators. The circuit includes a first bias switching device for switching a first power supply to a first reference oscillator and a second bias switching device for switching a second power supply to a second reference oscillator. The first and second reference oscillators generate first and second reference signals for synchronizing the oscillator frequencies. A first divider firstly and secondly divides and outputs the power of the first reference signal. A second divider firstly and secondly divides and outputs the power of the second reference signal. A first combining device inputs the power of the firstly-divided first reference signal and the secondly-divided second reference signal and outputs the power to the phase locked dielectric resonator oscillator for the vertical polarization wave.

Abstract: A relatively low frequency oscillator in junction with a much higher frequency oscillator is used to produce a clock that is both accurate and minimizes power consumption. The high frequency oscillator is enabled only during a small portion of the clock's operation and is used to gauge the output of the low frequency oscillator. The output of the high frequency oscillator is counted during its operation period, and the amount counted is accumulated for subsequent time periods. When the accumulated count reaches a predetermined value, a clock output is provided.

Abstract: The oscillation frequency of a non-externally voltage-controlled oscillator produces a control signal for the monolithic integrated voltage-controlled oscillator. This control signal is opposed to the influence of the operating temperature and the manufacturing parameters of the semiconductor chip in a similar way as the frequency of the voltage-controlled oscillator. The control signal is emitted through an iterative network consisting of a monostable multivibrator, a low-pass filter, and an amplifier. The iterative network produces an actuating signal for the voltage-controlled oscillator to counteract frequency deviations.

Abstract: A monolithic device is shown having a number of phase locked loops (PLLs) constructed thereon. At least one of the PLLs is constructed as a multiple loop having an output of one PLL loop tied back to the feedback path of the other loop of the pair. In this manner, tight resolution can be obtained in one loop while the bandwidth of that loop is coarse. The bandwidth of the second loop is tight, thereby giving good resolution to the first loop while still avoiding the problems inherent with noise injection locking from other PLLs on the same device.

Abstract: A temperature sensitive oscillator circuit and control circuit which together form a current source. The temperature sensitive oscillator circuit generates an output signal which controls a frequency of a refresh oscillator circuit. The duty cycle of the output signal of the temperature sensitive oscillator circuit is temperature dependent and increases for increases in temperature. The output signal of the temperature sensitive oscillator circuit controls the control circuit which sources current between the refresh oscillator circuit and a supply node. As the duty cycle of the output signal of the temperature sensitive oscillator circuit increases a time duration during which the control circuit sources current between the refresh oscillator circuit and the supply node increases. This increase increases the frequency of the output signal of the refresh oscillator circuit. The output signal of the refresh oscillator circuit is an internal clock signal which controls a refresh cycle of a memory circuit.

Abstract: A temperature compensated oscillator circuit includes an oscillator (1) which is controlled by a processor (8) . The output frequency (fx) of the oscillator (1) or an external reference frequency (fref) are used as reference signal in conjunction with a dual mode oscillator (9) which can be switched to provide temperature dependent fundamental (f1) and third (f3) harmonic frequencies. By the use of switches (S1, S2 S3), a divider (2) and first and second counters (3, 10) both calibration and temperature compensation of the oscillator (1) are carried out via the processor (8), using the substantially linear temperature dependence of the frequency difference between the third harmonic (f3) and three times the fundamental frequency (3f1).

Abstract: A semiconductor diode is connected across the cathode-to-anode path of a magnetron and through a storage capacitor and collector resistor to a supply voltage for enabling charging of the capacitor. A control pulse causes a switching transistor to conduct to discharge the capacitor through its collector-to-emitter path, an emitter resistor, and the magnetron, for causing the latter to oscillate. A feedback signal representative of the difference between the magnetron output frequency and a reference frequency is applied to a linear amplifier transistor which conducts through the emitter resistor for controlling the current flow through the switching transistor and the operating frequency of the magnetron.

Abstract: A direct digitally synthesizer-based, injection locked oscillator includes a direct digital synthesizer for generating a digitally synthesized signal at frequency f.sub.0, an analog oscillator circuit for generating an analog signal at frequency f.sub.1 and a filter coupled to the direct digital synthesizer for filtering the digitally synthesized signal to provide a signal at frequency Nf.sub.0. N may be an integer from 1 to 10. Also included is a coupler to couple the filtered, digitally synthesized signal into the analog oscillator to lock the frequency of the analog output signal to the frequency of the digitally synthesized signal such that the frequency f.sub.1 is equal to the frequency Nf.sub.0. The coupler also electrically couples the analog signal from the analog oscillator circuit to a second filter to filter the analog signal. An amplifier electrically coupled to the second filter amplifies the filtered signal to provide an analog oscillator output signal.

Abstract: A low-frequency low bandwidth Linear Frequency Modulation (LFM) waveform, nominally a 1 MHz to 10 Mz swept frequency analog sinusoid or digital square wave, is produced by direct digital synthesis. This waveform is upconverted in frequency and expanded in bandwidth, nominally to microwave frequencies with bandwidths of nominally 160-360 MHz, in a multiplying offset phase locked loop. The phase locked loop also linearly frequency modulates a X-band carrier with the microwave frequency LFM waveform to produce an output signal suitable for Synthetic Aperture Radar. The phase locked loop induces low phase error, and may be closed around the radar transmitter to remove phase errors induced by that unit.

Abstract: A digitally controlled oscillator (100) having a first oscillator circuit (108) for providing an oscillator signal F.sub.o of a defined frequency and a digital divider (110) for dividing the oscillator signal F.sub.o by a selectable number controlled by a digital word for providing a clock signal F.sub.clk. A second oscillator circuit (104) receives the clock signal F.sub.clk and provides a low frequency signal F.sub.c. The second oscillator circuit includes a digitally controlled resonator element (112) for determining the frequency of the low frequency signal and has a center frequency dependent upon the clock signal. Circuitry (118, 120, 138) is included for providing first and second pairs of quadrature phase shifted signals derived from the clock signal F.sub.clk and the low frequency signal F.sub.c and from the oscillator signal F.sub.o, respectively.

Abstract: A phase-lock loop scheme which can be implemented in an application specific integrated circuit using CMOS elements is disclosed which is directed to controlling a plurality of slave gate array circuits such that each of the master gate array circuit and the slave gate array circuits are clocked at the same time and are within a fixed time delay from a device reference clock signal. The master gate array circuit receives the input clock synchronization signal from the master clock of the device containing the master and gate array circuits and produces an internal clock signal which is then sent to each of the slave gate array circuits, by means of equal delay paths. The phase-lock loop circuitry utilized by each of the gate arrays can be implemented on program logic array chips along with the logic which receives the synchronized clock signals generated by the respective phase-lock loops of each of the gate array chips.

Abstract: A radar transmitter chain employing injection locked oscillator, e.g., a magnetron, as an output stage. Problems arise with maintaining the injection locking bandwidth centered on the radar source transmit frequency. This alignment is maintained by allowing the magnetron (38) free running frequency to drift, along with its injection locking bandwidth and then to force the radar source frequency (30) to follow the magnetron frequency. A phase difference measurement (44) between the injection signal (35) and the magnetron output signal (37) provides the control for a feedback loop (60) which may control a tunable VCO (48) or selection from a bank of fixed frequency oscillators (78).

Abstract: An inexpensive yet effective circuit for producing an irregular pulse train of variable frequency and duty cycle, particularly for generating simulated sounds, such as engine sounds for toy vehicles, is disclosed. The circuit comprises an integrated circuit including a plurality of Schmitt trigger inverters (U1A, U1B) configured for oscillation at different frequencies, and a resistance element (R3, R7) in series with one, and preferably both, of the power supply connections to the inverters, with the circuit output comprising the output of one of the Schmitt trigger inverters (U1B). In a preferred embodiment, a capacitance element (C4) is connected between the output of a Schmitt trigger inverter and its system voltage input for further modulating the circuit output.

Abstract: This invention provides an improved method for synchronizing a slave oscillator with a master oscillator. The slave includes two counters designated Reference and System, driven by its oscillator; the master includes a System Counter driven by its oscillator. The master sends a reset signal to the slave, simultaneously resetting its System Counter. Periodically, the master sends to the slave a synchronization signal, which signal is generated at predetermined intervals based upon the master's System Counter. Upon receipt of the reset signal, the slave resets its counters. Later, upon receipt of the synchronization pulse, the slave modifies the value of its System counter based upon the closest multiple of the expected count value for the synchronization signal interval. The Reference Counter is not synchronized and runs free.

Abstract: A high accuracy atomic frequency standard and clock which utilizes a micrmputer. The microcomputer compensates for aging and temperature variations in the atomic standard and its slave crystal oscillator and generates an error signal which is used to either correct the frequency of the slave crystal oscillator or to adjust the number of clock pulses per unit time interval. No C-field adjustment is employed.

Abstract: An integrated circuit random number generator which uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.

Abstract: A random number generator designed for use with an electronic key uses a triangular output analog oscillator to vary the frequency of a higher frequency voltage controlled oscillator. The output of the voltage controlled oscillator is sampled at a rate much less than the rate of oscillation of the voltage controlled oscillator to produce random digital values.

Abstract: The invention comprises a weather radar system in which a magnetron transmitter is controlled in frequency by injecting therein a low power locking signal from a stable frequency source. Frequency lock between the source and the magnetron is maintained without requiring injection signals of excessive power by an automatic frequency control (AFC). The AFC determines the frequency and phase error between the injection signal and the magnetron output and adjusts the frequency of the source so as always to be within a narrow band of frequencies centered about the natural frequency of the magnetron. Over the long term, therefore, the frequency of the source will vary by an amount equal to the change in the natural frequency of the magnetron occurring during that time. Over the short term, however, the difference in frequency between the injection signal and the magnetron output is zero, while the phase difference is less than 90.degree..

Abstract: A dielectric resonator oscillator utilizing transmission-type injection-locking for frequency stabilization is disclosed as including a transistor, two microstrip lines, and a dielectric resonator. One microstrip line is coupled to the transistor, while the other microstrip line receives the broadband signal. The dielectric resonator is positioned adjacent to and between the first and second microstrip lines and is operable for coupling an injection-locking signal into the transistor for locking the oscillation frequency of the oscillator. The two microstrip lines are preferably oriented at right angles so that various sizes of the dielectric resonator can be accommodated.

Abstract: A four-diode bridge is positioned within the cavity of a Gunn diode oscillator. A subharmonic signal is applied to the diode bridge and the diode bridge couples an odd harmonic of the injected signal into the cavity. The cavity is thus caused to resonate at the odd harmonic of the injected signal. The injected signal can be changed using a frequency synthesizer in order to provide a microwave oscillator with multiple-channel operation. The diode bridge provides a feedback signal indicative of the phase of cavity oscillation. The feedback signal is applied to a varactor which pretunes the Gunn diode oscillator and thereby provides phase-locked control.

Abstract: An oscillator circuit for generating a square wave output for space or terrestrial applications comprising a main oscillator and a saturable transformer forming the feedback loop of the power inverter. According to the invention, a synchronization circuit comprises transistors for shortcircuiting respective branches of the primary winding of this transformer upon detection of signal from differentiators connected to the main oscillator. Means connects a main limiting resistor to the center tap of the primary winding so that flux inversion is effected in the saturable transformer at the end of a power inverter recovery time.

Abstract: Phase locked, pulsed oscillator apparatus, for example, for radar use, comprises a pulsed r.f. oscillator, a pulse repetition frequency (PRF) generator and a pulse shaping network. The PRF generator pulsed output signal of frequency, f.sub.1, is reshaped by the pulse shaping network to provide to the input gate of the r.f. oscillator a train of triggering pulses each having a very fast rise time, t.sub.r, which caues the triggering pulses to exhibit significant harmonic power near the r.f. oscillator's free running frequency, f.sub.FR. The reshaped pulses provided by the pulse shaping network gate the r.f. oscillator on and off and cause coherency of the pulsed oscillator output signal relative to the PRF generator output signal. The reshaped pulse rise time, t.sub.r, is preferably less than about 3-4, and more preferably is about two, times the oscillator output signal period, l/f.sub.FR. The peak turn on voltage, V.sub.p, of the reshaped pulses is preferably about twice the average voltage, V.sub.

Abstract: A voltage controlled oscillator (VCO) is stabilized against variations in output frequency resulting from changes in temperature or the power supply voltage by trimming the voltage controlled oscillator from a second master VCO which is connected into a phase lock loop. Each of the two voltage controlled oscillators has an output frequency which is a function of two inputs. The signal input to one control input of each of the VCO's is the output of the low pass filter in the phase lock loop. The VCO's may both be implemented by cross-coupled NOR gates with grounded capacitor inputs.

Abstract: Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

Abstract: An injection-locked waveguide oscillator comprises a first diode (3) having a free-running fundamental frequency above the local cut-off frequency of the waveguide (1) and a second diode (4) having a fundamental frequency below and a higher harmonic above the local cut-off frequency. The first diode (3) may be an IMPATT diode and the second diode (4) a Gunn diode. The free-running fundamental frequency of the first diode (3) is close to the higher harmonic of the second diode (4) so that the second diode (4) injection-locks the first (3). Locking in the reverse sense is inhibited by the inherent loss in conversion from the higher harmonic to the fundamental in the second diode (4), thus avoiding the need for a circulator or isolator. The two diodes (3, 4) preferably are mounted in a common waveguide (1) for a simple compact structure.