Abstract: This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with reduced phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry. The first cell and the second cell may each include a portion of the CM noise of the VCO. Moreover, gate terminals of switches of the first cell and the second cell may be cross-coupled to drain terminals of the switches of the second cell and the first cell respectively. An interdependency of voltages of the first cell and the second cell may reduce an amplitude of the respective portions of the CM noise on the first cell and the second cell.

Abstract: Disclosed in the present invention is a high-frequency crystal oscillator based on automatic phase error correction. The high-frequency crystal oscillator comprises a high-frequency crystal, a load capacitor, two single-pole double-throw switches, a ring oscillator, an 8-frequency-dividing circuit, a twisted ring counter, a peak detector, a buffer, a digital module, a multiplexer and an amplifier. In the present invention, when a circuit performs energy injection on a high-frequency crystal, a phase error between an injection signal and a crystal oscillation signal is also detected and automatically corrected, such that the phase error is always less than 45 degrees. The present invention ensures the continuous and efficient linear growth in the energy inside a high-frequency crystal, and greatly shortens the starting time required for the crystal to reach a stable oscillation amplitude, thereby realizing rapid starting; and on the basis of automatic phase error correction technology.

Abstract: A three-stage differential ring oscillator circuit has a first differential stage, a second differential stage, and a third differential stage and generates six phases (two in each stage) used to form differential in-phase and quadrature-phase clock signals. A cross coupled inverter pair couples the first stage output signals. A second cross coupled inverter pair couples the second stage output signals. A third cross coupled inverter pair couples the third stage output signals. A first interpolator generates a first quadrature-phase clock signal using two phases (one from the positive portion of the second stage and one from the negative portion of the third stage) and a second interpolator generates a second quadrature-phase clock signal using two phases (one from the negative portion of the second stage and one from the positive portion of the third stage). Two phases from the first differential stage form the differential pair of in-phase clock signals.

Abstract: In certain aspects, a voltage controlled oscillator (VCO), a system circuit, and a control method thereof are disclosed. The VCO includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a first inductor. The second oscillator circuit includes a second inductor. The first inductor is embedded inside the second inductor so that a total mutual inductance between the first and second inductors is smaller than or equal to a predetermined threshold.

Abstract: A utility sensor module includes one or more sensors, a communication link, and an electronic processor. The electronic processor is configured to broadcast an advertisement signal associated with a communication protocol for a first transmission time. The advertisement signal is configured to cause an external device to transmit a response message. The electronic processor is further configured to determine whether the response message is received within a predetermined time period, and in response to determining that the response message was not received within the predetermined time period, operating in a modified sleep mode. Operating in the modified sleep mode includes modifying the operation of the communication interface to broadcast the advertisement signal at a periodic interval, such that the advertisement signal is only broadcast at the periodic interval for a second transmission time.

Abstract: A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

Abstract: This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.

Abstract: A non-isolated resonant gate drive circuit includes a PMOS drive network, an NMOS clamping circuit and an inductor. The PMOS drive network and the NMOS clamping circuit are connected in parallel to two terminals of the inductor. Input signals of the PMOS drive network are provided by a function generator connected to a drive chip, drive signals are output via an output port vgsr1 and an output port vgsr2 after the input signals are processed by the PMOS drive network, the NMOS clamping circuit and the inductor, the NMOS clamping circuit is used for controlling the state of the output port vgsr1 and the output port vgsr2 to change, and the inductor forms LC resonance together with a gate capacitor Cgsr1 and a gate capacitor Cgsr2 in the NMOS clamping circuit to recover energy in a process of turning off the drive circuit.

Abstract: This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with reduced phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry. The first cell and the second cell may each include a portion of the CM noise of the VCO. Moreover, gate terminals of switches of the first cell and the second cell may be cross-coupled to drain terminals of the switches of the second cell and the first cell respectively. An interdependency of voltages of the first cell and the second cell may reduce an amplitude of the respective portions of the CM noise on the first cell and the second cell.

Abstract: This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.

Abstract: Techniques and mechanisms for determining calibration information based on tuning of a ring oscillator circuit formed with two integrated circuit (IC) dies. In an embodiment, an oscillator circuit comprises an in-series arrangement of delay circuits including a first one or more delay circuits of a first die, and a second one or more delay circuits of a second die. Respective circuitry of the first die and the second die performs tuning to match an oscillation frequency of the oscillator circuit with a reference frequency. An operational setting of the tuned oscillator circuit is provided to calibrate transmitter circuitry of the first die and the second die. In another embodiment, tuning of the oscillator circuit is further based on tuning of a local oscillator circuit of one of the first die or the second die.

Abstract: A system of free running oscillators synchronized to the lowest frequency running one and following PVT variation generates a system clock. A method is particularly applicable to clock relatively small clock domains within a multi-core chip containing thousands of cores, and where the clock domain encompasses one or more cores and additional logic blocks. The resulting system clock is divided by 2k using latches or flip-flops to achieve a symmetric 50-50 duty cycle of the system clock. Further, such PVT insensitive system clock can be used as a reference for a PLL or DLL generated clock for the domain.

Abstract: Voltage-controlled oscillation circuitry includes multiple cores and multiple mode or gain boosters coupled between the multiple cores. To prevent an undesired operating mode of the voltage-controlled oscillation circuitry from dominating a desired operating mode (e.g., an in-phase operating mode or an out-of-phase operating mode), the mode boosters may increase a desired gain of the desired operating mode and decrease an undesired gain of the undesired operating modes. In particular, mode boosters coupled to terminals of the cores that are associated with the desired operating mode may be enabled, while mode boosters coupled to terminals of the cores that are associated with the undesired operating mode may be disabled.

Abstract: An analog beamformer used for array antenna and an operating method thereof are provided. The analog beamformer used for array antenna includes an intermediate-frequency amplifying circuit, multiple local oscillators, multiple mixers, multiple radio-frequency amplifying circuits, and a frequency locking circuit. The analog beamformer uses a master-oscillator and multiple slave-oscillators which embed a resonant network of frequency-and-phase-locking. The intermediate-frequency amplifying circuit receives a baseband signal to provide an intermediate-frequency signal. Power supplies or grounding ports of different local oscillators are connected together to provide multiple local-oscillating signals with consistent frequency but different phases. The mixers individually receive the intermediate-frequency signal and one of the local-oscillating signals to provide multiple mixed signals.

Abstract: A temperature compensated oscillator circuit includes a first oscillator, a second oscillator, a first divider, a second divider, a frequency ratio circuit, and a temperature compensation circuit. The first divider is coupled to the first oscillator, and is configured to divide a frequency of a first oscillator signal generated by the first oscillator. The second divider is coupled to the second oscillator, and is configured to divide a frequency of a second oscillator signal generated by the second oscillator. The frequency ratio circuit is coupled to the first divider and the second divider, and is configured to determine a frequency ratio of an output of the first divider to an output of the second divider. The temperature compensation circuit is coupled to the frequency ratio circuit and the first oscillator, and is configured to generate a compensated frequency based on the frequency ratio and the first oscillator signal.

Abstract: A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

Abstract: A processing apparatus to melt animal fat, in which an animal raw fat material is transported by a pump, through a microwave chamber and heated, the processing apparatus includes at least one solid-state radio frequency source that is configured to generate microwave energy, one or more sensors, and a control system. The at least one solid-state radio frequency source is configured to generate and transmit the microwave energy to the animal raw fat material, the one or more sensors are configured to measure the microwave energy that is reflected from the animal raw fat material, and the control system is configured to compare the transmitted microwave energy to the reflected microwave energy and then, based on the comparison, the control system is configured to adjust any additional microwave energy that is transmitted by the at least one solid-state radio frequency source to the animal raw fat material.

Abstract: A DLL circuit comprising a delay circuit, a phase detector and a counting control circuit. The delay circuit is configured to receive a reference clock signal, and delay the reference clock signal to output a delayed clock signal. The phase detector is configured to detect a phase difference between the reference clock signal and the delayed clock signal to generate a phase difference signal. The counting control circuit is configured to generate a control delay signal according to the phase difference signal. The delay circuit delays the reference clock signal according to the control delay signal to output the delayed clock signal. When the counting control circuit is in the first mode, the counting control circuit has a first update frequency. When the counting control circuit is in the second mode, the counting control circuit has a second update frequency.

Abstract: Both parallel-type and serial-type dual-mode oscillators employing stress compensated cut resonators having various configurations are disclosed. Both classes of dual-mode oscillators employ multiple tank circuits to pass one frequency of the resonator and block the other frequency. The tank circuits isolate the operation of the two oscillator sub-circuits that form the dual-mode oscillator from one another. The dual-mode oscillators may be implemented with either bipolar or CMOS transistors. The parallel-type dual-mode oscillators employ inverters to provide gain. The serial-type dual-mode oscillators employ a two (or three) stage design including a follower circuit first stage and an inverting amplifier/limiter circuit second stage, with an optional intervening transimpedance amplifier stage.

Abstract: A reference frequency signal generator comprises a plurality of ovenized reference crystal oscillators (OCXOs) having different turn-over-temperatures, a selector logic circuit coupled to outputs of the OCXOs, a temperature sensor, and a controller coupled to an output of the temperature sensor. The selector logic circuit outputs one of the outputs of the OCXOs based on a control signal from the controller. The controller also generates control signals for the OCXOs. In some implementations, the reference frequency signal generator includes a phase-locked loop or a fractional output divider coupled to the output of the selector logic circuit and configured to receive a calibration signal from the controller.

Abstract: An oscillator includes dual resonators mounted in a helium filled coldweld holder. One resonator operates at anti-resonance into a load capacitance of about 20 picofarads, and operates on a third overtone frequency under noncontrolled temperature conditions. The other resonator operates on a fundamental mode at anti-resonance in a load capacitance of about 32 picofarads. Resonator crystals in a dual-crystal resonator may include a theta-angle shift to equalize frequency versus temperature curves at temperature extremes.

Abstract: A device and method for terahertz signal generation are disclosed. Oscillators are arranged in a two-dimensional array, each oscillator connected to a corresponding antenna. Each oscillator is unidirectional connected to its adjacent oscillators by a phase shifter. A method for generating a steerable terahertz signal utilizes an array of oscillators connected by corresponding phase shifters. A terahertz signal having a fundamental frequency is generated using the array. The phase shift of one or more of the phase shifters is varied in order to vary the fundamental frequency and/or steer the signal generated by the array.

Abstract: A quadrature voltage-controlled oscillator circuit with phase shift includes two voltage-controlled oscillators with the same structure, wherein the two voltage-controlled oscillators are connected to each other through input and output ports, and the two voltage-controlled oscillators respectively include a cross-coupled oscillating circuit, an injection locking circuit, a resonant circuit and a voltage-controlled current source circuit which are electrically connected to each other; and signals are injected through the injection locking circuit and coupled with the oscillating circuit, so as to output a quadrature signal. An oscillator is enabled to operate stably in one mode by means of a simple circuit structure, and a good phase shift can be provided for the resonant circuit in a lower frequency band; and meanwhile, a tuning range of the oscillator is improved without increasing phase noise.

Abstract: In one aspect, a bridge includes a first magnetoresistance element that includes a first set of pillars, a second magnetoresistance element that includes a second set of pillars, a third magnetoresistance element that includes a third set of pillars and a fourth magnetoresistance element that includes a fourth set of pillars. The first set of pillars and the fourth set of pillars are disposed in a first matrix and the second set of pillars and the third set of pillars are disposed in a second matrix. The second magnetoresistance element is in series with the first magnetoresistance element, the third magnetoresistance element is in parallel with the first magnetoresistance element and the fourth magnetoresistance element is in series with the third magnetoresistance element.

Abstract: Provided is an oscillator including: a first resonator; a second resonator; a first oscillation circuit generating a first oscillation signal by oscillating the first resonator; a second oscillation circuit generating a second oscillation signal that has frequency-temperature characteristics different from frequency-temperature characteristics of the first oscillation signal by oscillating the second resonator; a clock signal generation circuit generating a clock signal with a frequency that is temperature compensated by temperature compensation data; and a processing circuit performing time digital conversion processing based on the first oscillation signal and the second oscillation signal, and obtaining the temperature compensation data based on measurement data of the time digital conversion processing.

Abstract: Systems and methods are provided for detecting and analyzing changes in a body. For example, a system includes an electric field generator configured to produce an electric field. The system includes an external sensor device configured to detect physical changes in the electric field, where the physical changes affect amplitude and frequency of the electric field. The system includes a quadrature demodulator configured to detect changes of the frequency of the output of the electric field generator. The system includes an amplitude reference source and an amplitude comparison switch configured to detect changes of the amplitude of the output of the electric field generator. The system includes a signal processor configured to analyze the changes of the amplitude and frequency of the output of the electric field generator.

Abstract: Signal recording sensor systems in accordance with embodiments of the invention include sensors capable of sensing and capturing electrophysiological signals in the presence of interference signals, an analog front-end including circuitry configured to record electrophysiological input signals as a voltage, and an analog to digital converter including a voltage-controlled-oscillator configured to convert the recorded analog electrophysiological input signal to a phase output. While such signal recording sensor systems can be used in the recording of biosignals and/or electrophysiological signals generated from living organisms, signal recording sensor systems in accordance with embodiments of the invention are not limited to recording biosignals and/or electrophysiological signals.

Abstract: A free running oscillator (FRO) includes a reference current generator, a current converter, and first and second oscillator cores. The reference current generator generates a first current. The current converter generates a second current based on the first current. The first oscillator core generates a clock signal at a first frequency based on a first value of the second current. The second oscillator core generates a clock signal at a second frequency based on a second value of the second current. The second frequency may be lower than the first frequency, and the second value of the second current lower than the first value of the second current.

Abstract: In described examples, a first die includes a primary LC tank oscillator having a natural frequency of oscillation to induce a forced oscillation in a secondary LC tank oscillator of a separate second die via a magnetic coupling between the primary LC tank oscillator and the secondary LC tank oscillator.

Abstract: According to one embodiment, an electronic circuit includes a first conductive component, a second conductive component, a first current path, and a second current path. The second conductive component is capacitively coupled to the first conductive component. The first current path of a superconductor includes a first portion and a second portion. The first portion is connected to the first conductive component. The second portion is connected to the second conductive component. The first current path includes N first Josephson junctions connected in series and provided between the first and second portions. The second current path of a superconductor includes a third portion and a fourth portion. The third portion is connected to the first conductive component. The fourth portion is connected to the second conductive component. The second current path includes a second Josephson junction connected in series and provided between the third and fourth portions.

Abstract: Methods and systems are disclosed for generating more random data or ensuring more random data than provided by single sources. Entropy is gathered among multiple random or pseudo-random sources at different frequencies. The entropy is pushed, pulled, or otherwise presented to a pseudo-random number generator when there is enough entropy. The determination of enough entropy can be through a modified Hamming distance. The frequencies of polling for entropy from the entropy sources can be jittered by a random amount.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: A signal transmitter includes a modulation circuit, a signal separation circuit, and a signal combining circuit. The modulation circuit modulates a first signal to a modulated signal. The signal separation circuit separates the modulated signal into N separated signals. The N separated signals have different phases. The signal combining circuit combines the N separated signals to eliminate at least one order of harmonic signals of the N separated signals so as to generate an output signal.

Abstract: An oscillator circuit includes first and second oscillators arranged in a series configuration between a supply voltage node and a reference voltage node. The first and second oscillators are configured to receive a synchronizing signal for controlling synchronization in frequency and phase. An electromagnetic network provided to couple the first and the second oscillators includes a transformer with a primary circuit and a secondary circuit. The primary circuit includes a first portion coupled to the first oscillator and second portion coupled to the second oscillator. The first and second portions are connected by a circuit element for reuse of current between the first and second oscillators. The oscillator circuit is fabricated as an integrated circuit device wherein the electromagnetic network is formed in metallization layers of the device. The secondary circuit generates an output power combining power provided from the first and second portions of the primary circuit.

Abstract: A clock system including a ring oscillator having a plurality of cascaded inverters, each of the cascaded inverters having a pair of inputs coupled to outputs of a respectively adjacent inverter stage and having a pair of outputs coupled to inputs of another respectively adjacent inverter stage, each inverter stage having a common mode control circuit provided therein, and a feedback controller adapted to transmit a control signal to the common mode control circuit of at least one of the inverters.

Abstract: Reducing coupling and mismatch in multi-core VCOs, including: arranging a plurality of inductors in a plurality of VCO cores in a parallel differential inductor configuration with shared leads to form a single node, wherein the plurality of inductors includes at least a first inductor and a second inductor; connecting power/ground traces to the first inductor from a first side only; and connecting the power/ground traces to the second inductor from another side different from the first side only to avoid making a current loop.

Abstract: A method, in one embodiment, can include modeling and calibrating two types of sensors that are part of a semiconductor device. In addition, the method can include determining a temperature and voltage based on data received from the two sensors.

Abstract: An oscillation circuit includes: an oscillation unit which includes a first terminal and a second terminal connected to a resonator, a third terminal, a fourth terminal to which at least one of a power supply potential and a signal for inspecting the resonator is applied, a first switching unit which switches modes of electrical connection between the first terminal and the third terminal, and a second switching unit which switches modes of electrical connection between the second terminal and the fourth terminal.

Abstract: A system includes: a phase frequency detector (PFD) having an output switchably connectable and disconnectable to a first signal path via a first switch, and switchably connectable and disconnectable to a second signal path via a second switch; a first filter disposed in the first signal path; a second filter disposed in the second signal path; and, a voltage controlled oscillator (VCO) operatively coupled to the first signal path downstream of the first filter, and operatively coupled to the second signal path downstream of the second filter. The VCO includes: a capacitive device or a current controlling device operatively coupled to the first signal path; and, a bulk terminal operatively coupled to the second signal path.

Abstract: A receiver and a transmitter that copes with interference in a super-regenerative communication system, and a method of using the receiver and the transmitter, are provided. A super-regenerative receiver includes a resonance frequency adjusting unit configured to adjust a resonance frequency associated with a filtering band of a transmission signal that is received from a transmitter. The super-regenerative receiver further includes an oscillation signal generating unit configured to generate an oscillation signal, using a positive feedback amplification, based on the resonance frequency and the transmission signal. The super-regenerative receiver further includes an oscillation characteristic detecting unit configured to detect a characteristic of the oscillation signal. The super-regenerative receiver further includes a determining unit configured to determine whether interference is included in the transmission signal based on the characteristic of the oscillation signal and the resonance frequency.

Abstract: According to one aspect of the present disclosure, there is provided a battery charging system. The battery charging system includes battery charging circuitry configured to provide charging current to a battery. The battery charging system further includes feedback circuitry configured to generate a feedback signal indicative of a battery charging condition, wherein the battery charging system is configured to control the battery charging current based on, at least in part, the feedback signal. The battery charging system further includes feed forward circuitry configured to adjust the feedback signal to decrease battery charging current when a decrease in battery current draw exceeds a threshold, and wherein the feed forward circuitry is configured to decrease the battery charging current faster than the feedback circuitry.

Abstract: A system for signal generation may include a phase-locked-loop including a first oscillator. The system may also include a second oscillator. The first oscillator may be configured to generate a first signal based on a phase-locked-loop control signal generated by the phase-locked-loop. The second oscillator may be configured to generate a second signal based on the phase-locked-loop control signal such that a free-running frequency of the first signal is approximately equal to a free-running frequency of the second signal to obtain injection locking between the first oscillator and the second oscillator when energy from the first oscillator is coupled into the second oscillator.

Abstract: A manufacturing method of an oscillator is a manufacturing method of an oscillator which includes a vibrator and a semiconductor circuit device including an oscillation part connected to the vibrator and a control part to switch an operation mode between a normal mode in which the oscillation part performs an oscillation operation and an inspection mode in which characteristics of the vibrator are inspected, and the manufacturing method includes preparing the semiconductor circuit device in which the operation mode is set to the inspection mode, connecting the semiconductor circuit device and the vibrator electrically, and inspecting the characteristics of the vibrator which is in a state electrically connected to the semiconductor circuit device.

Abstract: There is provided an integrated electronic circuit. The integrated electronic circuit includes a voltage controlled oscillator and a frequency doubler connected to the voltage controlled oscillator. A frequency doubling input of the frequency doubler is load isolated from an output of the voltage controlled oscillator.

Abstract: An electronic oscillator circuit has a first oscillator, for supplying a first oscillation signal, a second oscillator, for supplying a second oscillation signal, a first controller for delivering the first control signal as a function of a phase difference between a first controller input and a second controller input of the first controller; a second controller for delivering the second control signal as a function of a phase difference between a first controller input of the second controller and a second controller input of the second controller; a resonator; at least a second resonance frequency, with a first phase shift dependent on the difference between the frequency of a second exciting signal and the second resonance frequency and processing means, for receiving the first oscillator signal and the second oscillator signal, determining their mutual proportion, looking up a frequency compensation factor in a prestored table and outputting a compensated oscillation signal.

Abstract: Embodiments provide a multi-phase voltage controlled oscillator (VCO) that produces a plurality of output signals having a common frequency and different phases. In one embodiment, the VCO may include a passive conductive structure having a first ring and a plurality of taps spaced around the first ring. The VCO may further include a capacitive load coupled to the passive conductive structure, one or more feedback structures coupled between a pair of opposing taps of the plurality of taps, and one or more current injection devices coupled between a pair of adjacent taps of the plurality of taps.

Abstract: An oscillation signal generator includes a quadrature voltage-controlled oscillator (QVCO), a phase corrector and a frequency adjusting circuit. The QVCO provides multiple oscillation signals having difference phases. The phase corrector selects one of the oscillation signals as a first oscillation signal and outputs the first oscillation signal from a first output terminal, and selects one of the oscillation signals as a second oscillation signal and outputs the second oscillation signal from a second output terminal. A phase difference between the first and second oscillation signals satisfies a predetermined relationship. The frequency adjusting circuit is coupled to the phase corrector, and generates a quadrature signal and an in-phase signal according to the oscillation signals. The frequency of the oscillation signals is a non-integral multiple of the frequencies of the quadrature and in-phase signals.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A method for reducing the phase noise of a oscillator includes monitoring a phase slope of a resonator, and controlling the resonator to operate the resonator at a high phase slope condition, wherein the resonator comprises a piezoelectric material, or piezoelectric quartz.

Abstract: A cascaded oscillator array includes a first oscillator array and a second oscillator array. The first oscillator array includes at least three oscillator elements coupled unidirectionally in a first ring such that the first oscillator array outputs a first oscillating signal. Each of the at least three oscillator elements is coupled to receive a signal from a sensing element. The second oscillator array includes at least three oscillator elements coupled unidirectionally in a second ring such that the second oscillator array outputs a second oscillating signal. A first number of the at least three oscillator elements of the first oscillator array is the same as a second number of the at least three oscillator elements of the second oscillator. Each oscillator element of the at least three oscillator elements of the second oscillator array is coupled to receive an output signal from a single oscillator element of the at least three oscillator elements of the first oscillator.