Abstract: The present disclosure describes systems and devices for gain slope equalization in a radio frequency (RF) amplifier. The RF amplifier may include an input stage for receiving an RF signal. In conjunction with the input stage, the RF amplifier may incorporate an amplification stage to amplify the RF signal. Coupled with the amplification stage may be a transformer including a first winding to receive the amplified RF signal, a second winding providing an RF output signal, and a resonator including a third winding that is coupled to the first and second windings. The resonator may be coupled to a circuit network which may be tuned to affect the resonance frequency and the gain slope of the RF output signal.

Abstract: A power-management scheme where when a system-on-chip (SoC) is in an active state, control and monitoring logic or circuitry turns off all wake logic or circuits for various associated intellectual property (IP) blocks. Based on user defined operating system power manager (OSPM) policies, OSPM kicks off an interrupt to the control and monitoring logic or circuitry to turn off or power gate the wake logic for individual IP blocks in the SoC. As such, wake logic that are idle in active state (e.g., S0 state) and would otherwise draw power in the S0 state are now turned off, thus saving power and/or extending battery life for the system. When the SoC is in a low power state, then the control and monitoring logic or circuitry selectively turns on the wake logic for the associated IP blocks based on detected user presence for the computing system having the SoC.

Abstract: An inductor includes: a magnetic core; a conduction path penetrating the magnetic core; a pedestal portion including a core holding portion that holds the magnetic core, and support portions that support, when placed on a circuit board, electronic components at a height at which the electronic components can be accommodated on the circuit board side with respect to the core holding portion; and a shield portion that is provided on the circuit board side with respect to the magnetic core, and that shields a magnetic field generated by flow of electricity in the conduction path.

Abstract: A clock generator device includes a first clock generator circuit, a second clock generator circuit, a detector circuit and a selection circuit. The first clock generator circuit has a first starting voltage and generates a first clock signal in response to a supply voltage. The second clock generator circuit has a second starting voltage and generates a second clock signal in response to the supply voltage. The detector circuit detects the second clock signal to generate a validation signal. The selection circuit selectively outputs one of the first clock signal and the second clock signal according to the validation signal. The first starting voltage is lower than the second starting voltage.

Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

Abstract: An oscillator is comprising a plurality of resonators and a voltage bias circuit that applies voltages to the plurality of resonators. Each of the plurality of resonators has a negative resistance element. In the oscillator, the plurality of resonators are connected in parallel to the voltage bias circuit respectively via separate inductors.

Abstract: A clock generator includes an oscillator configured to generate an oscillating signal and a signal path configured to provide an output clock signal based on the oscillating signal. In response to a control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations. The neutralization may occur in the signal path. The signal path may be responsive to the control signal to adjust at least one of a duty cycle, a rise time, and a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal. The neutralization may occur in the oscillator. The clock generator may include an auxiliary path configured to provide an auxiliary signal to the oscillator.

Abstract: Embodiments of this invention include a test and measurement instrument and associated methods for acquiring and stitching wide overlapped non-uniform frequency bands so that a user specified band can be efficiently displayed and analyzed. The test and measurement instrument includes a user interface to receive the user specified frequency span. Acquisition circuitry acquires one or more predefined frequency bands having non-uniform overlapping frequency ranges. A frequency band processing section can decimate the acquired frequency bands, mask the acquired frequency bands, and stitch the masked frequency bands together. A display section displays the user specified frequency span using the stitched frequency bands. Due to the overlap configuration of the wide non-uniform bands, any user specified span between 50 kHz and 6 GHz, or thereabout, can be covered by two bands.

Abstract: A method and a circuit for generating a clock signal from a clock integrated circuit are introduced herein. A compensation voltage is generated according to a temperature coefficient of a resistor and a clock period of a clock circuit, where the compensation voltage is resistor-corner independent. The clock period of the clock circuit is determined by the resistor and at least one capacitor of the clock circuit. The temperature dependence of the clock period of the clock circuit is reduced according to the compensation voltage.

Abstract: The present invention provides a spin-transfer torque type injection locking oscillator which improves both power and noise performance by using pair of spin-transfer torque devices. One is optimized for high power and the other is optimized for low noise characteristics. The output signal of the low noise spin-transfer torque device is injected into the high output power spin-transfer torque for phase locking. The present invention has several advantages such as the miniaturization, the high quality and low cost, and the mass production of integrated chips by the nanoscale.

Abstract: A millimeter wave bands semiconductor package includes a metal base body, a circuit board, and a metal cover body. The base body has a first penetration hole and a second penetration hole. The circuit board is disposed on the base body and has an input signal line and an output signal line on a front side surface thereof. The cover body is disposed on the circuit board and has a first non-penetration hole and a second non-penetration hole. The cover body is disposed such that the first non-penetration hole is disposed directly above the first penetration hole of the base body and the second non-penetration hole is disposed directly above the second penetration hole of the base body. Further, the first non-penetration hole and the first penetration hole constitute a first waveguide and the second non-penetration hole and the second penetration hole constitute a second waveguide.

Abstract: A measuring device electronics comprises a processor and two clock signal generators. One clock signal generator serves for producing a working clock signal, and also for producing a reference clock signal which is dependant on the working clock signal. The other clock signal generator, serves for producing a second reference clock signal, which is independent of the working clock signal. Based on the two independent reference clock signals, a frequency difference, can, to the extent that such is present, be ascertained during operation of the measuring device electronics or of the measuring device formed therewith. The frequency difference, represents a difference between the instantaneous clocking frequency of the first reference clock signal and the instantaneous clocking frequency of the second reference clock signal, and, in this respect, represents a measure for a deviation of an instantaneous clocking frequency, from the nominally predetermined clocking frequency, of the working clock signal.

Abstract: In accordance with an embodiment of the disclosure, circuits and methods are provided for using a reconfigurable voltage controlled oscillator to support multi-mode applications. A voltage control oscillator circuit comprises a resonant circuit, a first oscillator circuitry coupled to the resonant circuit, and a second oscillator circuitry coupled to the resonant circuit. The voltage control oscillator circuit further comprises switching circuitry configured to select, based on an operating metric, one of the first oscillator circuitry and the second oscillator circuitry for providing an output voltage.

Abstract: A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.

Abstract: A voltage controlled oscillator (VCO) with low phase noise and a sharp output spectrum is desirable. The present disclosure provides embodiments of LC tank VCOs that generate output signals with less phase noise compared with conventional LC tank VCOs, while at the same time limiting additional cost, size, and/or power. The embodiments of the present disclosure can be used, for example, in wired or wireless communication systems that require low-phase noise oscillator signals for performing up-conversion and/or down-conversion.

Abstract: A phase-modification circuit is described. This phase-modification circuit reduces jitter by injecting a divided reference clock in a phase-locked loop from an auxiliary oscillator and by effectively gradually and completely transferring its phase to a master oscillator. The phase-correction strength in the phase-modification circuit is increased by successively coupling an edge in the divided reference clock over many cycles of a clock in the master oscillator. By increasing the correction strength, the phase error is effectively nulled out, thereby reducing the total absolute peak jitter. Moreover, because the correction is gradual and successive, the phase-modification circuit also significantly reduces the cycle-to-cycle jitter and half-cycle or edge jitter.

Abstract: A frequency tunable signal source (100) with first (105) and a second (115, 315) oscillators, each of which outputs a signal at a fundamental frequency (f1, f2) and at least one signal at a harmonic frequency (f1?, f2?) and a mixer (120) with first (121) and second (122) input ports and an output port (124), and a control unit (110) which controls switches (S1, S2, S3, S4), by means of which two of said signals (f1, f2, f1?, f2?) are switchably connected to the first input port. The other two signals are switchably to the other input port, with one switch (S1, S2, S3, S4) for each signal (f1, f2, f1?, f2?). There is also comprised a third oscillator (125), with an output signal connected to a third input port (123) of the mixer (120). At least one of the oscillators (105, 115, 315, 125) is a VCO, a Voltage Controlled Oscillator.

Abstract: The present invention is directed to an oscillator circuit comprising an oscillator input for providing an input signal, a first integrator circuit comprising a first integrator capacitor and a first integrator output, a comparator, a discharge circuit for discharging said first integrator capacitor once per cycle of said oscillator circuit, and an oscillator output for providing an output signal, wherein said oscillator circuit further comprises a second integrator circuit comprising a second integrator capacitor and a second integrator output, and wherein said oscillator circuit is arranged for allowing said input signal to be subsequently integrated by said first and second integrator circuit in an alternating manner, and for providing said integrated output signal of said first and second integrator circuit subsequently to said comparator in said alternating manner.

Abstract: A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically.

Abstract: The disclosure relates to an oscillator for use in generating frequencies in a frequency synthesizer, comprising: a first inductor element forming a metal trace loop with at least one turn, and a first capacitive circuit arranged to form a first resonance circuit with the first inductor element and being connected to the first inductor element through at least one first connection terminal, wherein the first capacitive circuit comprises at least one capacitive element and an electrical components arrangement arranged to establish and maintain an oscillation.

Abstract: An oscillation circuit includes a plurality of MEMS vibrators each having a first terminal and a second terminal, and having respective resonant frequencies different from each other, an amplifier circuit (an inverting amplifier circuit) having an input terminal and an output terminal, and a connection circuit adapted to connect the first terminal of one of the MEMS vibrators and the input terminal to each other, and the second terminal of the MEMS vibrator and the output terminal to each other to thereby connect the one of the MEMS vibrators and the amplifier circuit (the inverting amplifier circuit) to each other.

Abstract: An oscillator includes: a plurality of MEMS vibrators each having a first terminal and a second terminal, and having respective resonant frequencies different from each other; an amplifier circuit having an input terminal and an output terminal; a connection circuit adapted to connect the first terminal of one of the MEMS vibrators and the input terminal to each other, and the second terminal of the one of the MEMS vibrators and the output terminal to each other; a signal reception terminal adapted to receive a switching signal used to switch a state of the connection circuit; and a switching circuit adapted to make the connection circuit switch the MEMS vibrator to be connected to the amplifier circuit based on the switching signal, wherein the MEMS vibrators are housed in an inside of a cavity, and the signal reception terminal is disposed outside the cavity.

Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.

Abstract: The high-frequency digitally controlled oscillator includes fully digital cells capable of being ported to any CMOS fabrication process. The oscillator has a basic modular architecture comprising a digitally controlled digital ring oscillator (DRO) having a plurality of delay stages, a counter divider and a selection multiplexer. The DRO generates the basic (intrinsic) high frequency range and the counter provides the remaining ranges through division by multiples of two. The multiplexer provides a selection mechanism for the required range of frequencies. Load capacitances to the delay stages are added/removed to control delay via utilization of a unique capacitive cell driven synchronously by two ring oscillators such that the capacitance could be added or removed utilizing the Miller effect. Moreover, multiple capacitive load cells can be added to the same stage.

Abstract: A device is provided having a local oscillator (LO) configured to generate a first signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The device also has a LO error corrector comprising an input, the input configured to receive a second signal comprising at least one of timing information, frequency information, phase information and combinations thereof. The second signal is used for disciplining the LO. The LO error corrector is capable of disciplining the LO using a source that is less accurate than a preferred second signal, if the preferred second signal is unavailable to discipline the LO.

Abstract: A ring oscillator is disclosed. The ring oscillator includes a first tri-path inverter, a second tri-path inverter and a third tri-path inverter. The second tri-path inverter is connected to the first tri-path inverter. The third tri-path inverter is connected to the first and second tri-path inverters to provide feedback for oscillations.

Abstract: In accordance with an embodiment of the disclosure, circuits and methods are provided for using a reconfigurable voltage controlled oscillator to support multi-mode applications. A voltage control oscillator circuit comprises a resonant circuit, a first oscillator circuitry coupled to the resonant circuit, and a second oscillator circuitry coupled to the resonant circuit. The voltage control oscillator circuit further comprises switching circuitry configured to select, based on an operating metric, one of the first oscillator circuitry and the second oscillator circuitry for providing an output voltage.

Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.

Abstract: The invention provides a dual-mode voltage-controlled oscillator (DMVCO), a frequency synthesizer and a wireless receiving device, and pertains to the technical field of integrated circuit of radio frequency wireless receiver. The DMVCO and the frequency synthesizer can operate in a wideband mode and a quadrature mode. When operating in the quadrature mode, a quadrature signal is provided for a Single Sideband Mixer of the frequency synthesizer by a quadrature coupling of a first voltage-controlled oscillator unit and a second voltage-controlled oscillator unit in the DMVCO in the overlapped frequency band so that the frequency synthesizer can cover a higher output frequency band. Therefore, the tuning range of the DMVCO of the invention is wide, and the frequency synthesizer using the DMVCO is low in power consumption, simple in structure and has good frequency spur performance.

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: According to one exemplary embodiment, a voltage controlled oscillator configured to operate in low and high band modes includes a low band section and a high band section. The voltage controlled oscillator further includes a multi-tap inductor having a high inductance portion coupled to the low band section and a low inductance portion coupled to the high band section. The low band section is configured to provide a low frequency band oscillator output in the low band mode and the high band section is configure to provide a high frequency band oscillator output in the high band mode. The low band section is disabled in the high band mode and the high band section is disabled in the low band mode. A center tap of the multi-tap inductor is coupled to a supply voltage.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A switchable inductor-capacitor-inductor (L-C-L) network, which includes an integrated T/R switch, can advantageously bridge a PA and an LNA of a wireless device. The first inductor can function as an RF choke that provides power to the PA. In one embodiment, the first inductor can be advantageously implemented using the bond wires already attached to the PA, thereby requiring no additional inductors to provide the integrated T/R switch and minimizing use of valuable silicon area. The second inductor can function as a source inductor for and cancel an input parasitic capacitance of the LNA. A set of capacitors can act as blocking capacitors to provide DC isolation between the LNA and the PA, thereby protecting the LNA from high voltages. The L-C-L network can also advantageously function as an impedance matching network for at least one of the PA and the LNA.

Abstract: Configurable phase-locked loop circuitry is provided. The phase-locked loop circuitry may include a buffer having a buffer output and a multiplexer having inputs and an output. The phase-locked loop circuitry may include multiple voltage-controlled oscillators. The phase-locked loop circuitry may be configured to switch a desired one of the voltage-controlled oscillators into use. Each voltage-controlled oscillator may be controlled by control signals applied to a control input for that voltage-controlled oscillator. The control input of each voltage-controlled oscillator may be connected to the buffer output. The output of each voltage-controlled oscillator may be connected to a respective one of the multiplexer inputs. Power-down transistors may be used to disable unused voltage-controlled oscillators to conserve power. The power-down transistors and the multiplexer may be controlled by signals from programmable elements.

Abstract: An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.

Abstract: This invention makes it possible to reduce a power consumption of an electronic circuit (microcomputer, for example) while preventing malfunctioning of an oscillator by appropriately setting a power supply impedance of a low frequency oscillator corresponding to an operation mode. A high frequency oscillator, a medium frequency oscillator and a low frequency oscillator are provided as sources of system clocks. In addition, there is provided a quartz oscillator to generate a clock for a timepiece. When the high frequency oscillator is in operation, a power supply impedance of the quartz oscillator is reduced to improve a noise tolerance. In a waiting period during which the high frequency oscillator, the medium frequency oscillator and the low frequency oscillator are halted, on the other hand, the power supply impedance of the quartz oscillator is increased to suppress the power consumption.

Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.

Abstract: An electrical/magnetic current sensing system includes a first collection mechanism configured to convert an electric field into surface charge, a second collection mechanism comprising a magnetic reactive material, and a sensor coupled to the first and second collection mechanisms. The sensor comprises an odd number, greater than or equal to three, of unidirectionally-coupled non-linear over-damped bi-stable elements. Each element comprises a resistive load, an operational transconductance amplifier (OTA) with a bipolar junction transistor differential pair, a cross-coupled OTA, and a non-linear OTA. Each element may comprise fully differential inputs and outputs. The sensor may be contained in a microchip or on a printed circuit board. A resident time difference readout device may be connected to the sensor, and may be configured to perform a power spectral density calculation. The sensor may include a resistance to voltage circuit connected between the second collection mechanism and the elements.

Abstract: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract: The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range.

Abstract: In a voltage-controlled oscillator capable of broadening a variable frequency range while suppressing increase of conversion gain, a converter (12) converts an input voltage to a first physical quantity, a variable converter (13) supplies a second physical quantity that accords with the status of each switch of a switch group (13a). another variable converter (14), when the input voltage is contained within a prescribed voltage range, supplies a third physical quantity that accords with the input voltage and the status of each switch of another switch group (14a), and a variable-frequency oscillator (15) supplies a signal of a frequency that accords with the first physical quantity, the second physical quantity, and the third physical quantity.

Abstract: In a dual-band capable voltage-controlled oscillator (VCO) device at least two voltage-controlled oscillator units (VCO1, VCO2) are coupled via a reactive component (A) and each said at least one voltage-controlled oscillator unit (VCO1, VCO2) further being connected to at least a respective external switching device (B1, B2) adapted to control an operating frequency of the A (VCO) device.

Abstract: A digital frequency synthesizer can be implemented with single source design, a multiplexer design, a fractional divider design, or a frequency multiplier and frequency divider design. Implementations can utilize a controller dithering circuit or a delta-sigma modulator. The frequency synthesizer can be implemented in a CMOS structure and can utilize a clean up phase locked loop (PLL).

Abstract: In a high-frequency oscillator, a first resonance circuit and a second resonance circuit are respectively connected to a first amplifier circuit and a second amplifier circuit. A selection circuit includes a first switch circuit and a second switch circuit which selectively operate one of the first amplifier circuit and the second amplifier circuit. A grounded capacitor is connected to output sides of the first amplifier circuit and the second amplifier circuit. The grounded capacitor is commonly used by both the first amplifier circuit and the second amplifier circuit. An auxiliary grounded capacitor is connected between the first switch circuit and the first amplifier circuit. Accordingly, the grounded capacitor and the auxiliary grounded capacitor are connected to each other in parallel only when the first amplifier circuit is activated.