Abstract: A digital integrated circuit normally operated from an external clock signal and including an internal reference oscillator for providing a reference signal as an internally generated signal backup in the event that the external clock signal is not present or is too low in frequency for safe operation of the integrated circuit. The integrated circuit has a frequency comparator for receiving the external clock signal and the internal reference signal as inputs and producing an output indicative of the state of the external clock signal. A two-way switch is connected to the output of the frequency comparator and selects either the external clock signal or the internal reference signal for transmission to the integrated circuit based upon the output from the frequency comparator.

Abstract: A clock signal switching circuit having input terminals to receive a first clock signal of a first frequency, a second clock signal of a second frequency, and a frequency switching signal and an output terminal to output one of the first clock signal and second clock signal, wherein the output of the clock signal switching circuit is selected to be one of the first and second clock signals by the frequency switching signal.

Abstract: An adjunct chip, usable as a peripheral to a microprocessor, which detects power failure, and which puts the microprocessor into a known state upon power down. In order to reliably and stably put the microprocessor into a known state, several clocks are generated after the reset signal. However, since the power supply is falling, it is possible that the crystal-controlled oscillator may already have become unreliable. Therefore, a simple logic circuit (a ring oscillator, in the presently preferred embodiment) is used to generate the needed additional clocks at power-down. The switch from crystal-controlled oscillator to ring oscillator is stabilized by using a latched multiplexer to switch between the two oscillator inputs. The latch adds hysteresis to the switching characteristic, avoiding any problems of switching jitter.

Abstract: Disclosed is a semiconductor device in which a CPU and an oscillation circuit are driven with the same driving voltage. The oscillation circuit is constituted by a plurality of oscillation invertors having different characteristics respectively corresponding to different reference voltages for driving the CPU. One of the oscillation invertors is selected corresponding to the driving voltage of the CPU so that the oscillation signal of the selected oscillation circuit is sent out as a system clock. It is therefore possible to obtain preferable characteristics that, when the driving voltage of the CPU is changed over in accordance with a program, fluctuation in the driving ability of the oscillation invertors, which has been conventionally generated, is prevented from occurring, so that oscillation easily starts upon turning-on of a power supply, oscillation hardly stops when a source voltage becomes low, and high harmonics oscillation hardly occurs.

Abstract: A high stability oscillator circuit 100 having an output 150 and a multiple of reference oscillators 102, 104, and 106 for enhanced stability and reliability is disclosed. The output signals of these oscillators 108, 110, and 112 are mixed and analyzed for determination of excessive frequency shift including component failure. Additionally a switch 148 decouples the shifted oscillator signal from the output of the circuit 150 and couples another one of the oscillators in its place.

Abstract: Apparatus for allowing low noise and fast frequency switching of a ferri-resonant oscillator, such as YIG, that uses a coil to control output signal frequency by current level. The apparatus positions an active filter in parallel with the oscillator coil, which can be set to one of two impedance levels. A low impedance level provides low pass filtering of the current to the oscillator coil for low noise operation. A second high impedance level allows fast settling of transients during frequency changes. Once current levels have stabilized, the active filter can then be switched to low impedance mode without creating a significant transient. This facilitates fast frequency switching.

Abstract: In order to replace a reference clock s.sub.R, as needed, and without phase shift, with another clock f, the latter clock must be synchronized to the reference clock in frequency and in phase. Since the reference clock can fail or can be disturbed, undesirable synchronizations often occur in such cases. An error-free, phase-wise optimal synchronization of the two clocks is achieved and synchronization is carried out as a rule only when a defined edge of the reference clock appears within a time range defined with reference to the clock f.

Abstract: Method for synchronizing the phase of clock signals of two clock generators in communications networks. Using the present method, the phase relations of clock signals that are derived from oscillator clock signals in two clock generators are synchronized such that the phase relations of the clock signals coincide regardless of the distance between the two clock generators. To this end, one clock generator is defined as a reference clock generator and reference clock signals formed therein are communicated to the other further clock generator. In the latter, the generated further clock signals are synchronized with the incoming reference clock signals and the clock signals synchronized in this fashion are forwarded to the reference clock generator. In the latter, the phase deviation of the internally formed clock signals and of the incoming clock signals is measured and correction information is formed and forwarded to the other further clock generator.

Abstract: A digital controlled clock provides ultra fine resolution for a sampling clock signal for recovering data from a received signal, the phase jump of the sampling clock signal being determined the number of stages in a multiphase clock generator that generates a number of equally-spaced phase clock outputs based on a reference clock signal. Phase selection is performed through a very low overhead phase commutator in response to phase advance/retard inputs. A clock deglitcher matched to the stages of the ring oscillator eliminates spikes generated when the phase commutator switches.

Abstract: A clock signal generator comprising a first oscillator which normally supplies clock pulses to the output of the clock signal generator, a first counter for counting the pulses generated from the first oscillator and producing a carry signal after counting n1 pulses generated from the first oscillator, a second oscillator for producing clock pulses for possible back-up purpose, a second counter for counting the pulses generated from the second oscillator and adapted to produce a carry signal after counting n2 pulses generated from the second oscillator and to be reset by the carry signal from the first counter, n2 being larger than n1, and a control circuit which blocks the output from the second oscillator as long as no carry signal is supplied thereto from the second oscillator.

Abstract: The circuitry of the present invention taps a DS0 data stream and outputs a timing signal to drive terminal multiplexers. Even if the data bit stream is lost, the present invention continues to provide proper clocking signals. A composite clock (bit and byte clock) is provided by the present invention with the bit clock at 64 KHz and the byte clock at 8 KHz in the preferred embodiment. To avoid the problem of phase shift over long distances (limiting cable length) the present invention phase adjusts the digital bit stream clocking signal with a 360 degree delay, giving the appearance of advancing the signal in phase. An additional delay of one frame width is applied to the signal. A negative phase delay equivalent to cable runs from 0-1500 feet in 500 foot increments is also applied. In the preferred embodiment, a shift register is tapped in reverse order to accomplish this phase delay.

Abstract: A connecting structure for connecting two oscillator circuits to an amplifier. The oscillator circuits are provided on one surface of a printed circuit board and include two dielectric resonators. The amplifier circuit is provided on the other surface of the printed circuit board for selectively amplifying oscillatory outputs from the oscillator circuits. The dielectric resonators are fixed to a metal plate mounted on the printed circuit board, and the amplifier circuit is located at a position opposite to the metal plate.

Abstract: A clock control system includes two clock supply units and two data processing units. Each clock supply unit is capable of supplying clock signals at either of two frequencies. The clock control system allows each data processing unit to be supplied with clock signals of either frequency from either clock supply unit. If one clock supply unit becomes defective, any data processing unit being supplied by that one defective clock supply unit can have its clock supply switched to the non-defective clock supply unit, without having to change the frequency of the non-defective clock supply unit.

Abstract: A multiple input clock selector is provided for switching asynchronously from one to another of a plurality of oscillators that generate clock signals having different frequencies. The clock selector has a plurality of sections corresponding to the plurality of oscillators. Each section of the clock selector comprises an initial AND gate, a pair of flip-flops, and a final AND gate all connected in series. The oscillator signal for each section is applied to the final AND gate and to the flip-flops as a clock input. An inverted signal from the second flip-flop of each section is fed back as an input to the initial AND gates of all the other sections. An oscillator select signal is also provided as an input to the initial AND gate of each section. The outputs of all the final AND gates pass through an OR gate that provides the selected clock output.

Abstract: An integrated circuit configuration and a method monitor an integrated oscillator in the circuit. The oscillator has a minimum frequency and furnishes a synchronously controlling clock rate for the functioning of the integrated circuit when excited by an external frequency standard. An integrated reserve oscillator has a maximum frequency below the minimum frequency of the oscillator. An integrated frequency comparator is connected to the reserve oscillator and to the oscillator for comparing the frequency of the reserve oscillator with the frequency of the oscillator.

Abstract: A frequency-changeable microwave signal generator has a plurality of microwave signal oscillators, a plurality of branch lines connected to the microwave signal oscillators, a transmission line connected to the plurality of branch lines and provided with an output port at one end thereof, and a means for selectively operating one of the microwave signal oscillators. The line lengths of the branch lines are set such that the output impedance of the microwave signal oscillator connected thereto, which is measured from a branch point for connecting the transmission line and the branch line, is at maximum when the microwave signal oscillators are inoperative. The relation L=(.lambda./2)(k-1) (k is a natural number) is satisfied where L is a distance along the transmission line between adjacent branch portions of the branch lines connected to the transmission line, and .lambda. is a predetermined operational wavelength.

Abstract: In a signal generator based on Direct Frequency Synthesis, a first reference frequency generator generates a signal of a reference frequency. A plurality of second reference frequency generators, respectively, generates K signals with different frequencies Asin(.omega..sub.1 t+.psi.), Asin(.omega..sub.2 t+.psi.) . . . Asin(.omega..sub.K t+.psi.), which are in phase at time point (t=0), in response to the output signal of the first reference frequency generator. A switching circuit selectively switches the output signals from the plurality of said second reference frequency generators. A timing pulse generator generates timing pulses to operate said switching circuit at time T as given by .vertline..omega..sub.i+1 T-.omega..sub.i T.vertline.=2l.pi. (l:integer) where i=1, 2 . . . K-1.

Abstract: Synchronization facilities are disclosed for maintaining error free timing of a digital system when control of the system timing is switched between a plurality of clock sources. The signal of each source is applied to an associated counter divider whose output is applied to switch facilities which extend the output of only one divider at a time as a reference clock source to the digital system. The dividers for the other sources are forcibly reset each time the divider of the reference source advances from its all 1s to its reset (all 0s) position. This maintains the output signals of all dividers in phase with each other to prevent disturbances to the digital system when its timing is switched between clock sources.

Abstract: There are three oscillator circuits which oscillate at different frequencies, each oscillator circuit including a gate having an input and an output. The output of the first gate is connected to an inverter and the input of the second gate. The output of the inverter is connected to the input of the third gate. The output of the second and third gates is connected across a piezoelectric transducer to produce a warble sound.

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Abstract: A frequency time standard monitoring system includes three highly accurate standards of substantially identical frequency. These three standards are compared in pairs by three monitoring apparatus. Each such apparatus includes a fine window detector for determining the phase relationship between the two applied frequency standard clock signals, and a phase shifter responsive to the fine window detector for shifting the phase of one of the signals until the signals are phase aligned. When this occurs, the fine window detector is disabled and a coarse window detector monitors the two clock signals to ensure that the clocks do not drift beyond tolerable limits. The output signal of the coarse window detector is applied, along with the corresponding signals from the other two monitoring apparatus, to a select logic which determines which standard should be on-line in the event of a fault detection.

Abstract: Between insulative layers (31-37, 41-44), a multilayer substrate comprises at least one dielectric layer (26-29). It is possible to form capacitors (58), resistors (46), and wiring conductors (61, 62) in the substrate. The at least one dielectric layer should be of at least one dielectric composition which has a perovskite structure. Preferably, each insulative layer is of an insulating material which consists essentially of aluminum oxide and lead borosilicate glass. The substrate is convenient in manufacturing a crystal oscillator by mounting a crystal vibrator (71) and a transistor (72) on the principal surface(s). Examples of the dielectric composition are:Pb[(Fe.sub.2/3.W.sub.1/3).sub.0.33 (Fe.sub.1/2.Nb.sub.1/2).sub.0.67 ]O.sub.3,Pb[(Mn.sub.1/3.Nb.sub.2/3).sub.0.01 (Mg.sub.1/2.W.sub.1/2).sub.0.30 (Ni.sub.1/3.Nb.sub.2/3).sub.0.49 Ti.sub.0.20 ]O.sub.3,andPb[(Mg.sub.1/2.W.sub.1/2).sub.0.66 Ti.sub.0.34 ]O.sub.3.

Abstract: A frequency synthesizer is provided that is capable of supplying a plurality of accurate frequencies. The frequency synthesizer comprises a resonator matrix including a plurality of resonators embedded in a single monolithic piece of piezoelectric crystal. The resonators are arranged in rectangular row and column configuration including m rows and n columns. Each of the resonators is separated from its neighboring resonators by distances such that the resonant energies do not overlap. Each of the rows of resonators bears a metallic electrode stripe for that row and each of the columns of resonators bears a metallic electrode stripe for that column, the electrodes row stripes being positioned on the top surface of the crystal and the electrode column stripes being positioned on the bottom surface of the crystal. The areas of overlap of the row and column stripes are registered with the central portions of the embedded resonators.

Abstract: Two oscillators are utilized to convert digital data into an FSK modulated signal. One oscillator is at the mark frequency and the other is at the space frequency. FSK modulation is accomplished by switching between the two frequencies based on the state of the digital data. Phase and frequency shifting techniques are also provided to insure that a desired difference between the mark frequency and space frequency is maintained and to also insure that a proper phase relationship is maintained between the output from the two oscillators.

Abstract: A power oscillator for transmitter equipment operating at hyperfrequencies such as microwave links and radar. A plurality of elementary oscillators are coupled in parallel. Each elementary oscillator comprises a field effect transistor (FET) (11) connected in the common drain configuration with a first microstrip (51) connected to its gate and a second (21) connected to its source. Adjacent gates are interconnected by first resistances (R1) and adjacent sources by second resistances (R2). The resistances serve to balance the oscillators and to suppress parasitic oscillation. The free ends of the gate microstrips (21) are interconnected to synchronize the oscillators and the free ends of the source microstrips (51) are interconnected to constitute the oscillator outlet. The FETs may be disposed in a line or in a ring.

Abstract: In a frequency synthesizer type electronic tuner comprising a plurality of local oscillators operable in frequency ranges different from each other, only one of said local oscillators being operable in accordance with a received frequency band, and the outputs of the local oscillators being connected with a prescaler constituting a PLL station selecting circuit through a coupling circuit which includes series connected circuits of resistors and capacitors, respectively, characterized in that the resistors in said coupling circuit are connected on the side thereof adjacent to the local oscillators, while the capacitors in the coupling circuit are connected on the side thereof adjacent to the prescaler, so that resistors and capacitors are used in a connecting part between the local oscillator circuit and the prescaler of the tuner thereby the separation between VHF and UHF bands is improved.

Abstract: A system for synchronizing remote or colocated oscillators is constructed with redundancy enabling a high degree of fault toleration. In the various embodiments of the system there is no predetermined hierarchy amongst the oscillators in contrast to the prior art master and slave type of synchronization. Averaging is not involved and the system settles to a state in which the oscillators are locked to one master, which is not predetermined. Each oscillator is part of a terminal which includes reconfiguration circuitry, and each, in the absence of faults, is connected to each of the other terminals. The terminals attempt to lock to another oscillator and reconfigure in accordance with an algorithm until stable synchronization is achieved. In one embodiment the properties of a phaselocked loop are utilized in a novel way by incorporating a variable delay in its feed back path.

Abstract: Disclosed is a low noise microwave frequency synthesizer having a plurality of rapidly switchable output frequencies. Two banks of oscillators are selectively mixed to yield a range of output signals of low phase noise and low spurious noise. The first bank of oscillators comprises low noise, highly stable oscillators of a frequency range below the desired synthesized output signal. The second bank of oscillators comprises low noise, highly stable oscillators of a frequency range lower than the first bank. The signal from the second bank of oscillators is frequency multiplied to a desired frequency range by a low multiplication factor and then mixed with the signal from the first bank of oscillators. Multiplied phase noise is reduced by using a low multiplication factor. The upper sideband of the mixed signals is output as the synthesized output signal. Rapid switching between oscillators in both banks provides a frequency range of synthesized output signals which may be rapidly stepped through as desired.

Abstract: A touch control arrangement which employs a touch panel comprising a plurality of touch keys and a network of electrically connected capacitive elements; an oscillator which incorporates the network of capacitive elements in its timing circuit; and a microprocessor coupled to the output of the oscillator and operative to control various appliance operating components as determined by the frequency of the oscillator output signal. The keys of the touch panel are operatively coupled to the network of capacitive elements such that actuation of a key or pad by the user changes the equivalent capacitance of the timing circuit causing the oscillator a generate a control signal at the frequency associated with the actuated key.

Abstract: A frequency memory module responsive to an input relatively short duration RF burst signal of center frequency f for producing an output signal at center frequency f for a relatively long duration includes a narrow band filter tuned to pass frequency f which is receptive of the input signal, an amplifier connected to the output of the filter and feedback means connected from the output of the amplifier to the input of the filter. Because of the feedback the frequency memory module sustains oscillations at frequency f long after the input pulse is removed from the filter.

Abstract: A switching circuit for automatically selecting one of a plurality of normally operable asynchronous oscillators is provided with a selection switch for selecting a new oscillator while the formerly selected oscillator is still producing an output. The switching circuit employs the output of the newly selected oscillator to disable the formerly selected oscillator and to subsequently enable the output of the newly selected oscillator to be coupled to the oscillator output of the switching circuit, thus, preventing switch-over from one oscillator to the other during a metastable period.

Abstract: Electronic switching means for synchronizing a voltage controlled oscillator output with a variable input Baud Rate Clock. A Baud rate counter ratio input to a Phase Lock Loop circuit is selected or electronically switched automatically according to the input signal Baud rate. Binary counters count down a clock during the time an input signal is high, and the result of the count is transferred to an output register which controls, on the basis of the count, the electronic switching of a Baud rate counter to select the appropriate counter ratio output.

Abstract: In a multiband tuner, an input arrangement for selectively applying first and second local oscillator signals to a single input of a prescaler of a phase locked loop tuning system includes a first capacitor connected in series from the output of a first local oscillator to the prescaler input, a second capacitor and inductor connected in series from one output of a second local oscillator to the same prescaler input and a diode switching arrangement for selectively coupling a third capacitor between the junction of the second capacitor and the inductor and signal ground when the first local oscillator is enabled to operate. The first capacitor, inductor and third capacitor comprise a matching network for the output of the first local oscillator. The second capacitor and inductor form a series tuned circuit in the frequency band of the second local oscillator which rejects signals in the frequency band of the first local oscillator.

Abstract: In a microcomputer integrated circuit the option of selecting between an RC oscillator or a crystal oscillator for generating the clock for the microprocessor is made available. By making the selection during the manufacturing process, external pin outs and chip area are minimized.

Abstract: A control circuit for the turn-signal flasher system of an automotive vehicle. The flasher system includes a relay having switch contacts which are serially connected, together with a direction indicator switch, between the vehicle battery and the turn-signal lamps. A measuring or sampling resistor is connected between the battery and the relay contacts. First and second pulse generators are connected between a first voltage indicator and the relay coil, and are selectively gated to interrupt the relay during normal lamp load conditions. The first pulse generator provides a normal mark-to-space ratio whereas the second pulse generator provides a reduced mark-to-space ratio for use during night driving conditions. Third and fourth pulse generators are responsive to corresponding voltage indicators connected to the measuring resistor. The third and fourth generators function to respectively provide different mark-to-space ratios in response to, and indicative of, lamp outage or current-overload conditions.

Abstract: A broadband high frequency signal generator is disclosed having a low and a high frequency swept signal source connected to a YIG tuned frequency multiplier. One end of an output coupling loop for the YIG is connected to ground through a PIN diode, and the low frequency signal source is connected to the junction of the output coupling loop and the PIN diode. When the PIN diode is caused to conduct, signals from the high frequency source are passed through the YIG tuned multiplier to an output in the conventional manner. When the PIN diode is not conducting, signals from the low frequency source are passed to the output through the output coupling loop.

Abstract: Three or more oscillators to be locked in phase with one another are interconnected in a closed ring and have individual feedback loops including respective frequency dividers designed to keep them in step with a synchronizing frequency, equal to a fraction of their own operating frequency, fed in through an associated multiplexer. The multiplexer has a first input receiving the stepped-down feedback frequency of the immediately preceding oscillator, a second input connected to the output of the associated frequency divider, and a third input energizable with an external reference frequency such as a carrier of a PCM of FDM system. Each multiplexer, in the absence of an external switching command which holds it on its third input, stands on its first input unless a control circuit associated with the immediately preceding oscillator detects a disparity between the two frequencies fed to that preceding oscillator via the feedback loop and the multiplexer of the latter.

Abstract: A device for connecting plural oscillators to a single output port without he use of power dividers, switches or multiplexing filters. The plural oscillators produce multiple frequencies with only one oscillator operating at a given time. The oscillators are mounted in shunt waveguide cavities along a central waveguide manifold at distances from the central waveguide manifold and waveguide end so as not to affect the operating oscillator.

Abstract: Apparatus for generating noise is described incorporating means for generating a noise frequency spectrum, a plurality of voltage controlled oscillators and means for coupling the voltage controlled oscillators to an output.The invention overcomes the problem of a single voltage controlled oscillator which could not slue and settle at an appropriate frequency prior to being coupled to an output which resulted in undesired frequencies being generated during this slueing and settling time.

Abstract: A clock signal generator for providing redundant clock signals includes two clock modules that utilize phase-locked loop oscillators for generating clock and reference signals and for diagnosing malfunctions of the generated clock and reference signals. One clock module is selected as the master, and the other clock module is the slave, being phase and frequency locked to the master. Switching the master between the clock modules may be externally initiated by select signals and also is automatically initiated when malfunctions are detected. The master and slave clock modules are always phase and frequency locked to one another, even if both clock modules are malfunctioning. When both clock modules experience simultaneous malfunctions, the master is selected in accordance with the externally generated select signals. Since the master and slave clock modules are always phase and frequency locked, switching the master is transparent to clock signal utilization circuitry.

Abstract: A clock system is disclosed having two identical clocks not synchronized with each other. Each of the clocks includes a circuit for selecting the output of one of the clocks as the present system output. Further, each clock includes logic for detecting errors in the operation of itself, and of the other. When an error is detected in the operation of the clock selected to be the present system output, a switchover sequence control switches the output signal of the nonselected clock to become the new system output. The switchover sequence control includes a feature which ensures that the interval between pulses in the system output is greater than a predetermined period in order to minimize detrimental effects on circuitry utilizing the clock system output.

Abstract: A frequency modulation oscillator is provided having three or more output frequencies corresponding to three or more possible input signals, the output frequency being a phase continuous frequency modulated signal with no discontinuities. For each desired output frequency, there is an input amplifier, responsive to an input binary signal, the output of that amplifier being summed with the outputs of the other amplifiers. For each input amplifier there is an active feedback network containing a delay element which will produce oscillation in the associated amplifier, the active feedback network from each amplifier being isolated from the other amplifiers and feedback networks.

Abstract: A frequency modulation oscillator circuit is provided having three or more output frequencies corresponding to three or more possible input signals, the output frequency being a phase continuous frequency modulated signal with no discontinuities. For each desired output frequency, there is an input amplifier, responsive to an input binary signal, the output of that amplifier being summed with the outputs of the other amplifiers. For each input amplifier there is an active feedback network containing a delay element which will produce oscillation in the associated amplifier, the active feedback network from each amplifier being isolated from the other amplifiers and feedback networks. Input amplifiers comprising differential amplifiers emitter coupled to transistor switches are shown together with common base feedback amplifiers emitter coupled to the collectors of one of the transistors comprising the input differential amplifier.

Abstract: An electrical signal generator comprises an electric wave oscillator for producing oscillations at one or other of two predetermined frequencies, an attenuator device for attenuating oscillations produced by the oscillator in a manner which varies over a period of time, and control means for controlling the oscillator to produce a burst of oscillations at one said predetermined frequency and a subsequent burst of oscillations at the other said predetermined frequency. The control means controls the attenuator device increasingly to attenuate the oscillations over the period of each burst.

Abstract: A plurality of oscillator-modulator combinations is incorporated into a monolithic integrated circuit. A single pole multiple position switch is used to energize a single oscillator at a time, and a filter having a plurality of inputs and a common output is coupled to the modulator outputs. The modulators each have a common modulation input. Using this combination, a very simple switch can be used to control the modulated signal output at different carrier frequencies.

Abstract: A clock output signal is aligned in phase to conicide with the phase of signals derived from a master clock. In the event that there is a malfunction of the master, standby control circuitry modifies the phase of the clock output signal incremental quantities until it is in phase with the phase of signals from a standby clock. The clock output signal is thereafter maintained aligned in phase to coincide with the phase of the signals derived from the standby clock.

Abstract: A plurality of window comparators and voltage controlled oscillators are arranged to receive analog input signals which are converted to output frequencies that are linearly proportional to the analog signals over a substantially infinite amplitude range.

Abstract: A frequency shift keyed (FSK) generator producing an output frequency which is determined by gating through a selected one of a plurality of crystal controlled oscillators. The oscillator output is divided by a digital frequency divider to the operating tone frequency. The square wave output of the divider is filtered to a sinewave by an active tracking bandpass filter which is instantaneously switched to the operating frequency simultaneously with the selection of the appropriate crystal controlled oscillator.

Abstract: A search type tuning device wherein the output signal representing the difference frequency between the output frequency from a voltage-controlled frequency sweep oscillator and a reference frequency is filtered by a low-pass filter; the difference between the output voltage from the low-pass filter and a predetermined driving voltage for sweeping the oscillation frequency of the oscillator is derived from an adder; the output from the adder is integrated by an integrator; and the output voltage from the integrator is applied as a sweep voltage to the oscillator, thereby automatically maintaining the oscillation frequency thereof at a predetermined value. The analysis of the operation of the oscillator may be much facilitated, and when used as an automatic channel selector for a television receiver, a high speed automatic channel selection may be ensured.

Abstract: A clock signal reproducing network for PCM signal reception is capable of reproducing a clock signal even if the clock component is absent in the input digital signal for a prolonged period of time. The network includes a clock signal component extracting circuit and a bandpass filter for extracting and band-limiting the clock signal component in a received digital signal. An envelope detection circuit and a level decision circuit are connected to receive the output of the bandpass filter to provide a control signal to an output switching circuit. When the amplitude of the envelope of the filter output is high, the output of the bandpass filter is used directly as a reproduced clock signal. When the amplitude of the envelope is low, the clock signal obtained immediately before the filter amplitude becomes small is derived repeatedly from a delay circuit as a substituted clock signal.