Abstract: An oscillation circuit includes: n ring oscillators each formed from m delay elements connected annularly, m being an integer equal to or greater than 2, n being an integer equal to or greater than 2; and a phase coupled ring.

Abstract: A Digitally Controlled Oscillator (DCO) including a unit inverter cell whose output frequency linearly varies according to a digital control signal, the unit inverter cell linearly varying a delay response characteristic of an output signal with respect to an input signal supplied from an input terminal, in response to a reference signal and a zeroth control signal, and including a reference cell and a first selecting cell. The reference cell transmits the output signal to an output terminal, wherein the output signal is obtained by reversing a phase of the input signal in response to the reference signal and a reverse reference signal obtained by reversing a phase of the reference signal. The number of transistors forming the reference cell and the first selecting cell and sizes of the transistors are equal.

Abstract: An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.

Abstract: An oscillation circuit and a semiconductor device incorporating same are provided. The oscillation circuit includes an oscillation unit including a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases, when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters, when the control signal is deactivated, and a control unit configured to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node among the plurality of inverters and clock signals of which the phases lead that of a clock signal of the first node, when the oscillation enable signal is deactivated.

Abstract: Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section.

Abstract: A VCO circuit having low jitter and low PSS (power supply sensitivity). The VCO circuit includes a first ring oscillator stage, a second ring oscillator stage coupled to the first ring oscillator stage, and a VCO input coupled to both the first ring oscillator stage and the second ring oscillator stage for receiving a control voltage. Each of the first ring oscillator stage and the second ring oscillator stage further includes a CMOS inverter with a plurality of cross coupled transistors to implement oscillation of the VCO circuit.

Abstract: Multiple multi-stage delay circuits each have n (n is an integer) output terminals. The multi-stage delay circuits each apply delay times to a corresponding input signal, and output, via n output terminals, n delayed signals to which different delay times have been applied. Multiple inverters invert the respective input signals. The multiple multi-stage delay circuits and multiple inverters are alternately connected in the form of a ring.

Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

Abstract: A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.

Abstract: A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator.

Abstract: The invention relates to a semiconductor device comprising a test structure (100) for detecting variations in the structure of the semiconductor device, the test structure (100) comprising a first supply rail (110), a second supply rail (120), a ring oscillator (130) coupled between the first supply rail (110) and second supply rail (120), the ring oscillator (130) having an output (132) for providing a test result signal, and an array (140) of individually controllable transistors (142) coupled in parallel between the first supply rail (110) and the ring oscillator (130). Variations in the current output of the respective transistors (142) in the array (140) lead to variations in the respective output frequencies of the ring oscillator (130). This gives a qualitative indication of the aforementioned structural variations.

Abstract: An oscillator. The oscillator includes a first ring oscillator having a first plurality of inverters, a first plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the first plurality of inverters, a second ring oscillator having a second plurality of inverters, and a second plurality of capacitors each having a first terminal coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the first plurality of capacitors is coupled to an output terminal of a corresponding one of the second plurality of inverters. A second terminal of the second plurality of capacitors is coupled to an output terminal of a corresponding one of the first plurality of inverters. The oscillator is configured to provide as an output a differential clock signal.

Abstract: A current controlled ring oscillator and a method for controlling the same are provided. The current controlled ring oscillator includes a charge pump (CP), a loop filter (LF), a voltage-current (V-I) converter, and an oscillation unit. The CP is used to provide a charging/discharging current. The LF is coupled to the CP, and is used to provide a control voltage. The V-I converter is coupled to the CP, and is used to convert the control voltage to a control current. The oscillation unit includes a plurality of current controlled delay cells serially connected to one another as a ring, and the oscillation unit is coupled to the V-I converter, and controlled by the control current to generate an oscillation signal.

Abstract: The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other.

Abstract: An organic electronic module has a clock generator having n organic switching elements connected in series. The output of the nth organic switching element is connected to the input of the first organic switching element. The outputs of two or more organic switching elements are connected to respective inputs of a first electronic circuit of the electronic module tapping off two or more clock signals such that a first clock signal for a first electronic circuit is tapped from the output of a first one of the switching elements and a second clock signal, phase-shifted with respect to the first clock signal, for the first electronic circuit is tapped from the output of a second switching element different than the first switching element.

Abstract: Frequency synthesizer circuitry employs a delay line. A reference clock signal propagates through successive stages of the delay line, and the currents drawn by output buffers of all of the stages are added at a common node. The common node current is converted to a voltage, which is AC-coupled to an output buffer ring oscillator of the frequency synthesizer. The output buffer ring oscillator includes a plurality of inverters connected in a series. A feedback connection including a resistor is provided from an output node of the last inverter to an input node of the first inverter.

Abstract: An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal.

Abstract: An interrogation circuit for a nanowire sensor array and a method for interrogating a nanowire sensor array are provided. The circuit comprises a switch array connected to the nanowire sensor array for selectively connecting first ends of nanowire sensors of the nanowire sensor array to a reference voltage; an integration amplifier (IA) connected to second ends of the nanowire sensors at a first input of the IA and to the reference voltage at a second input of the IA, for generating an oscillating output signal clamped between first and second voltage values; wherein the switch array is further arranged for switching one of the nanowire sensors to be connected in a closed loop with the IA such that a current through said one nanowire sensor periodically charges and discharges an integration capacitor of the IA for determining a resistance of said one nanowire sensor from a frequency of the periodic charging and discharging.

Abstract: An oscillator of the present invention includes a constant current circuit in which a constant current generated in the constant current circuit varies positively with an on threshold voltage of a transistor included in the constant circuit; and an oscillating circuit in which the oscillating frequency of a clock signal generated in the oscillating circuit varies positively with the constant current supplied from the constant current circuit, and the oscillating frequency of the clock signal generated in the oscillating circuit varies negatively with an on threshold voltage of a transistor included in the oscillating circuit.

Abstract: An oscillator circuit includes an oscillator that generates an oscillation signal and a limiter that limits amplitude of the oscillation signal output from the oscillator.

Abstract: An oscillation circuit including a first transistor, a second transistor, a current source, a first inverter, and an impedance unit is disclosed. The first transistor has a first source receiving a first operation voltage, a first drain, and a first gate coupled to the first drain. The second transistor has a second source receiving the first operation voltage, a second drain, and a second gate coupled to the first gate. The current source is coupled between the first drain and a grounding voltage. The first inverter generates an oscillation signal and has a first input terminal, a first output terminal, and a first power terminal coupled to the second drain. The impedance unit is coupled between the first input terminal and the first output terminal.

Abstract: A method and apparatus for analog smooth switch in VCO loading control, in one technique, receiving an input signal to adjust a frequency of an oscillator; activating one or more switches to control a current source/sink based on the received input signal; applying the current source/sink to a capacitor to adjust a voltage on the capacitor; and applying the voltage on the capacitor to one or more switches, each of the one or more switches connected between a load and a stage of the oscillator.

Abstract: A voltage controlled oscillator and a load cell circuit usable in VCO are provided. The VCO features an internal compensation for process, voltage and temperature using a replica of half of the oscillating stage. The load cell circuit comprises a bias transistor to drain a predetermined current from the oscillating stage, a control transistor to vary resistance offered by it responsive to a control voltage applied and a resistor adapted to provide a clamp resistance.

Abstract: A signal generator, a signal generation method, and a communication system using the same are provided. The signal generator includes a plurality of nonlinear elements which are connected in a ring; and a signal distributor which is arranged in the ring to form a closed loop, feeds part of a signal to one of the plurality of the nonlinear elements, and outputs signal generated by one of the plurality of nonlinear elements. The method includes arranging a plurality of nonlinear elements connected in a ring; inputting a signal to one of the nonlinear elements; amplifying the signal; receiving the amplified signal and generating a harmonic component of a frequency; clipping the signal; and feeding part of the signal back to one of the nonlinear elements and outputting a remainder of the signal. The system includes a chaotic signal generator; a signal distributor; a modulator; and a transmission circuit.

Abstract: A method of generating an output signal from an input signal includes a step of generating a set of n signals, n being an integer greater than or equal to 3, by generating a signal for each integer i such that 0?i?(n?1), each signal within the set having the same frequency and approximately equal amplitude and a phase equal to (360/n)i degrees. The method also includes a step of inputting each of the set of n signals to a gate terminal of a corresponding one of a set of n transistors. Each of the transistors has a source terminal electrically connected to a common voltage drain and each of the transistors has a drain terminal electrically connected to a coupling. The coupling is electrically connected to a common voltage source. The output signal at the coupling has a frequency equal to the frequency of the input signal multiplied by n.

Abstract: A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.

Abstract: A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.

Abstract: With conventional charge pumps, significant noise is present due at least in part to large changes in the supply current. To combat this problem, a charge pump is provided that includes a number of stages. These stages are coupled to receive periodic alternating voltages having a phase shift with respect to each other so that the changes in the supply current are reduced, which reduces noise.

Abstract: A delay circuit includes a MOSFET and bias voltage sources. The bias voltage sources apply a voltage difference between the drain and source of the MOSFET. The bias voltage source supplies a source voltage to a source electrode of the MOSFET. The bias voltage source supplies a drain voltage to a drain electrode of the MOSFET. An input signal to be delayed is propagated through the gate of the MOSFET in the gate width direction (y-axis direction).

Abstract: A ring-based multi-push voltage-controlled oscillator (VCO) with the control voltage to generate the multi-push output signal is disclosed. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by delay cells is to multiply the frequency tuning range.

Abstract: A system and method for observing threshold voltage variations are provided. A ring oscillator circuit comprises a plurality of inverters arranged in a sequential loop, a plurality of test circuits having devices under test, each coupled between a respective one of the inverters and a power supply. Each test circuit has a bypass field effect transistor (FET) having a first channel coupled between the power supply and a respective one of the inverters responsive to an individual enable signal, and a FET device under test having a second channel arranged in parallel to the first channel. A method is described for determining the threshold voltage of the device under test by disabling, for one of the inverters in the ring oscillator, the first FET device such that the device under test is coupled between the power supply and the respective inverter and affects the operating frequency of the ring oscillator.

Abstract: A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract: This disclosure relates to delay cells in a ring oscillator that include sub-cells having a gain that is a function of a variable control signal and sub-cells with a gain that is set by a fixed control signal.

Abstract: Methods and systems to provide digitally controlled crystal oscillators are disclosed. One example method includes determining a state of an oscillator system and selecting a first output of a digitally controlled crystal oscillator or a second output of a second oscillator based on the determination. In an example implementation, the second oscillator is a ring oscillator.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: The present invention provides a current-limited oscillator capable of performing stable operation even when it is driven with a low power-supply voltage, and a charge pump circuit using the oscillator. A current-limited oscillator has a delay section that includes a plurality of series-connected inverters to delay an output pulse on the basis of a current limiting level indication signal, and the oscillator further includes at least one first transistor that limits a first current between the inverters and a high potential power supply and at least one second transistor that limits a second current between the inverters and a low potential power supply, wherein at least one of the plurality of inverters is configured as a first inverter that is connected with the first transistor and is not connected with the second transistor, and at least another of the plurality of inverters is configured as a second inverter that is not connected with the first transistor and is connected with the second transistor.

Abstract: A device has a resonator coupled to input and output nodes, the resonator being characterized by a transducer to drive the output node, and further characterized by a feedthrough capacitance such that portions of the input signal bypass the transducer to allow a spurious signal to reach the output node. The device includes a compensation capacitor coupled to the output node to define a compensation capacitance in accordance with the feedthrough capacitance. A phase inversion circuit is coupled to the compensation capacitance to generate a compensation signal and coupled to the output node such that the spurious signal is offset by the compensation signal. In some cases, a differential amplifier of the phase inversion circuit has the compensation capacitance in a feedback path to offset the feedthrough capacitance. In these and other cases, the compensation capacitance and the feedthrough capacitance may be unmatched to avoid overcompensation.

Abstract: Timing measurement is performed by a digital oscillator, using a calibration value which is calculated after chip fabrication is completed, and automatically loaded into selection logic at powerup.

Abstract: A PLL circuit includes a phase detector, a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares a phase of a signal Fs which is input from outside with a phase of a signal Fo/N which is input from the frequency divider. The loop filter generates a signal Vin by removing alternating current components from a signal input from the phase detector. The voltage-controlled oscillator outputs a signal Fo based on the signal Vin input from the loop filter. The frequency divider converts the signal Fo output from the voltage-controlled oscillator into Fo/N (frequency division by N), and outputs it to the phase detector.

Abstract: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first frequency. The selection circuit is subjected to a second operating condition that is different from the first operating condition and generates a second frequency. A first frequency differential between the first frequency and the second frequency is compared to a predetermined frequency differential to determine if the first frequency differential is about equal to the predetermined frequency differential.

Abstract: Improvements in and relating to electronic pulse generation or oscillation circuitry based on a signal path exhibiting endless electromagnetic continuity and affording signal phase inversion in setting pulse duration or half-cycles of oscillation within time of signal traverse of said signal path, and having active switching means associated with said signal path to set rise and fall times of each said pulse or said half-cycle of oscillation, including for frequency adjustment by selective inductance and power saving without stopping pulse generation or oscillation.

Abstract: A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.

Abstract: An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.

Abstract: A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port.