Abstract: A wideband oscillation circuit outputting oscillation signals (divided signals) of continuous frequencies is disclosed and the wideband oscillation circuit includes an oscillator that outputs an oscillation signal, a filter that filters the oscillation signal output from the oscillator and outputs an injection locked signal, and an injection locked frequency divider that performs a free-run operation and outputs a divided signal of the oscillation signal while its oscillating operation is regulated by the injection locked signal, the division ratio of which varies in accordance with a control signal, wherein the filter generates the injection locked signal by controlling the passing characteristic that caused the oscillation signal to pass with respect to time in accordance with a filter control signal locked with the divided signal.

Abstract: A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.

Abstract: An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors.

Abstract: A voltage-controlled oscillator robust against power supply includes: a regulating unit configured to maintain a virtual power supply of a VCO core circuit in a stable condition with regard to a reference voltage; and a power supply removal unit including second transistors configured to correspond to respective first transistors of the regulating unit, the power supply removal unit being configured to remove power noise of the virtual power supply by using negative feedback through a closed-circuit loop formed by each of the first and second transistors.

Abstract: A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

Abstract: A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block.

Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.

Abstract: A self correcting device includes a first flip-flop to receive data and coupled to a clock input; one or more delayed flip-flops used to detect delay variations; a multiplexer coupled to the output of the first flip-flop and the delayed flip-flops, a metastability detector and error check controller to control the multiplexer to select one flip-flop output; and an adaptive voltage swing link coupled to the multiplexer output to generate a voltage swing on the link based on a selected clock skew.

Abstract: An oscillation circuit includes: n ring oscillators each formed from m delay elements connected annularly, m being an integer equal to or greater than 2, n being an integer equal to or greater than 2; and a phase coupled ring.

Abstract: A voltage controlled oscillator including a control signal adjuster and ring-connected delay cells is disclosed. The control signal adjuster receives a first control signal to generate a second control signal boosted from the first control signal when the first control signal is lower than a transistor threshold voltage. The ring-connected delay cells are controlled by the first and second control signals both to generate an oscillation signal. Each of the delay cells has a first set of current generation transistors and a second set of current generation transistors. Each transistor of the first set of current generation transistors has a control terminal receiving the first control signal while each transistor of the second set of current generation transistors has a control terminal receiving the second control signal. The first and second sets of current generation transistors collectively output an oscillation signal with unchanged frequency of associated input signal.

Abstract: A semiconductor non-linear channelizer device comprises an array of N first order, bi-stable semiconductor circuit cells. The circuit cells are uni-directionally coupled from a first circuit cell to another circuit cell, where N is an integer greater than 1. A signal input trace is coupled to each of the circuit cells and a signal output trace is coupled from each of the circuit cells.

Abstract: A delay cell for use in a ring oscillator and associated method is provided. The delay cell includes a differential amplifier, a switched capacitance bank, and a Kvco equalizer. The differential amplifier comprises a differential pair, a first load and a second load. The differential pair includes a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The first load is coupled to the positive output terminal, and the second load is coupled to the negative output terminal. The switched capacitance bank has a plurality of controlled capacitor paths selectively connecting to the positive output terminal or the negative output terminal according to a capacitance controlling signal. The Kvco equalizer has an adjustable current source for providing a current to the Kvco equalizer according to a current controlling signal to compensate currents flowing through the first load and the second load.

Abstract: A ring oscillator is disclosed. The ring oscillator includes a first tri-path inverter, a second tri-path inverter and a third tri-path inverter. The second tri-path inverter is connected to the first tri-path inverter. The third tri-path inverter is connected to the first and second tri-path inverters to provide feedback for oscillations.

Abstract: A voltage controlled oscillator having a temperature and process controlled output. A VCO in accordance with the present invention comprises a reference current source, a fixed current source, coupled in series with the reference current source, the fixed current source comprising a temperature independent current source, a third current source, coupled in parallel with the combination of the reference current source and the fixed current source, and an oscillator, coupled in series with the third current source, wherein a current used to control the oscillator is based on operating temperatures and processes of the reference current source and the third current source.

Abstract: A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.

Abstract: A semiconductor integrated circuit includes a ring oscillator and a noise canceller. The ring oscillator includes first and second signal generators. The first signal generator is configured to generate a first output signal having a first phase based on an input signal. The second signal generator is configured to generate a second output signal having a second phase different from the first phase based on the input signal. The noise canceller includes first and second amplifiers and an arithmetic module. The first amplifier is configured to amplify the first output signal generated by the first signal generator using a first amplification factor. The second amplifier is configured to amplify the second output signal generated by the second signal generator using a second amplification factor. The arithmetic module is configured to combine the first output signal amplified by the first amplifier with the second output signal amplified by the second amplifier.

Abstract: A high speed linear differential amplifier (HSLDA) having automatic gain adjustment to maximize linearity regardless of manufacturing process, changes in temperature, or swing width change of the input signal. The HSLDA comprises a differential amplifier, and a control signal generator including a replica differential amplifier, a reference voltage generator, and a comparator. The comparator outputs a control signal that automatically adjusts the gain of the high speed linear differential amplifier and of the replica differential amplifier. The replica differential amplifier receives predetermined complementary voltages as input signals and outputs a replica output signal to the comparator. The reference voltage generator outputs a voltage to the comparator at which linearity of the output signal of the differential amplifier is maximized. The control signal equalizes the voltage level of the replica output signal and the reference voltage, and controls the gain of the differential amplifier.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: A ring oscillator has at least one latch connected to the outputs of at least one oscillator stage, where the latch drives the outputs of the oscillator stage to opposite states during startup, and drive strength reduction circuitry to reduce drive strength of the latch after startup when the oscillator is oscillating.

Abstract: The oscillator comprises at least a first series of a multiple of four sub-assemblies each of which comprises an excitation terminal and an output terminal. The sub-assemblies are arranged in series in a closed loop. The output terminal of each sub-assembly is connected to the excitation terminal of the following sub-assembly. The output terminal of one of the sub-assemblies constitutes the output terminal of the oscillator. Each sub-assembly comprises excitation means and a nanowire which constitutes the electromechanical resonator and the piezoresistive detection means of movement of the resonator. A first terminal of the nanowire is connected to a first supply voltage. The second terminal of the nanowire constitutes the output terminal of the sub-assembly which is grounded via a corresponding resistive circuit. An input terminal of the excitation means constitutes the excitation terminal of the sub-assembly.

Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.

Abstract: A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information.

Abstract: A method and system for modulating logic clock oscillator frequency based on voltage supply. The system comprises a logic unit having a logic operation and a device to produce self-adjusting clocks to match the logic operation. The device is configured to use supply voltage as an independent variable to optimize device parameters for voltage variations. The invention is also directed to a design structure on which a circuit resides.

Abstract: The present invention provides an array of tunable, injection-locking oscillators which are scalable to higher frequencies and measure the entire relevant frequency space simultaneously. The scalable, highly-parallelized, adaptive receiver architecture uses arrays of tunable, injection-locking nonlinear oscillator rings for broad spectrum RF analysis. Three separate and different microelectronic circuit configurations, each having a different type of readout, are described. The embodiments are designed to be incorporated as a subsystem in any type of powered system in which a fast image of the broader spectrum is valuable, when no information about the location of signals in the frequency space is predictable or forthcoming.

Abstract: An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.

Abstract: Circuitry for establishing a traveling wave on a rotary traveling wave oscillator is described. The circuitry includes a gain portion that establishes a wave in a preferred direction by degenerating any wave traveling opposite to the preferred direction and regenerating any wave traveling in the preferred direction. If there are two such gain portions, each having opposite preferred directions, then a wave that is presently established in one direction can be degenerated and a new wave can be established in the opposite direction, thereby achieving reversibility of the traveling wave in real time. Each of the gain portions included in a plurality of regeneration/degeneration elements present on the rotary oscillator. Each of the regeneration/degeneration elements is connected to a pair of taps on the oscillator, the taps being separated by a direction dependent phase difference.

Abstract: A ring oscillator including a core circuit and a first adjusting circuit. The core circuit is for outputting a clock signal, and includes a plurality of ring stages. The first adjusting circuit is for receiving a plurality of first control information, and referring to the plurality of first control information to adjust the clock signal. The first adjusting circuit includes a plurality of bias circuits and a plurality of switch elements. The bias circuits are for providing a plurality of currents, and the switches are connected to the bias circuits in series and receive the plurality of first control information, respectively, wherein each switch element is selectively conducting according to a corresponding first control information for determining whether a current provided by a corresponding bias circuit is utilized to bias the core circuit.

Abstract: Disclosed herein is a feed-forward ring oscillator. The feed-forward ring oscillator includes a plurality of delay cells for receiving a first differential input signal pair and a second differential input signal pair, and outputting a differential output signal pair. The delay cells are connected in a ring shape. Each of the delay cells receives a differential output signal pair of a delay cell of a previous stage as a first differential input signal pair and receives a differential output signal pair of a delay cell of a stage before the previous stage as a second differential input signal pair. Each of the delay cells comprises multiple independent gate field-effect transistors.

Abstract: Circuitry for determining timing characteristics, for example, access time, setup time, hold time, recovery time and removal time, of as-manufactured digital circuit elements, such as latches, flip-flops and memory cells. Each element under test is embodied in variable-loop-path ring oscillator circuitry that includes multiple ring-oscillator loop paths, each of which differs from the other(s) in terms of inclusion and exclusion of ones of a data input and a data output of the element under test. Each loop path is caused to oscillate at each of a plurality of frequencies, and data regarding the oscillation frequencies is used to determine one or more timing characteristics of the element under test. The variable-loop-path ring oscillator circuitry can be incorporated into a variety of test systems, including automated testing equipment, and built-in self test structures and can be used in performing model-to-hardware correlation of library cells that include testable as-manufactured digital circuit elements.

Abstract: An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.

Abstract: An integrated circuit 2 is provided with one or more monitoring circuits 14, 16, 18, 20 in the form of ring oscillators 22. These ring oscillators 22 include a plurality of tri-state inverters 24, 26, 28 containing a current-limiting transistor 42 operating in a leakage mode. The leakage current through the transistor 42 is dependent upon an operating parameter of the integrated circuit 2 being monitored. Accordingly, the oscillation frequency Fosc of the ring oscillator 22 varies in dependence upon the operating parameter to be measured.

Abstract: A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, CPAR. Current is measured to both the device under test (DUT) and the de-embedding structure. From these measurements, the frequency dependent capacitance of the DUT is calculated.

Abstract: A semiconductor device includes an antenna circuit for receiving a wireless signal, a power supply circuit generating power by the wireless signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generation circuit includes a ring oscillator which self-oscillates and a frequency divider which adjusts frequency of an output signal of the ring oscillator in an appropriate range. A digital circuit portion is driven by a clock having high frequency accuracy, so that a malfunction such as an incorrect operation or no response is prevented.

Abstract: An oscillating circuit includes N nodes outputting oscillating signals, a main loop circuit including N inverting circuits, and a plurality of auxiliary loop circuits. Each inverting circuit in the auxiliary loop circuits is connected in parallel with even numbers of inverting circuits cascaded in the main loop circuit. The circuits for feeding back signals from outputs to inputs of the respective inverters of the main loop circuit have circuit configurations equivalent to each other. Each inverting circuit in the main loop circuit and the auxiliary loop circuits drives an output line such that a phase of an output signal is inverted with respect to a phase of an input signal and has driving power that becomes lower when the phases of the output signal and the input signal are inverted with respect to each other than when the output signal and the input signal are in phase with each other.

Abstract: One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.

Abstract: A delay line of individually selectable delay elements can operate as an oscillator in an open loop mode to track process variation or drive a clock signal that varies with temperatures and voltages in the system. The delay line oscillator can also operate in a closed loop mode to match a frequency given by a tuner ratio and a reference clock. The delay line can also be used for measuring clock jitter or duty cycle.

Abstract: An apparatus comprising a transconductance control circuit, a boost control circuit, a current computation circuit and an oscillator circuit. The transconductance control circuit may be configured to generate a current control signal in response to (i) a voltage control signal and (ii) a plurality of range control signals. The boost control circuit may be configured to generate a current boost signal in response to a reference current signal and an enable signal. The current computation circuit may be configured to generate a first control signal and a second control signal in response to the current boost signal and the current control signal. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to the first control signal and the second control signal.

Abstract: Described is a compact, lower power gated ring oscillator time-to-digital converter that achieves first order noise shaping of quantization noise using a digital implementation. The gated ring oscillator time-to-digital converter includes a plurality of delay stages configured to enable propagation of a transitioning signal through the delay stages during an enabled state and configured to inhibit propagation of the transitioning signal through the delay stages during a disabled state. Delay stages are interconnected to allow sustained transitions to propagate through the delay stages during the enabled state and to preserve a state of the gated ring oscillator time-to-digital converter during the disabled state. The state represents a time resolution that is finer than the delay of at least one of the delay stages. A measurement module determines the number of transitions of the delay stages.

Abstract: A high-frequency generator circuit comprises a signal generating circuit, a delay unit, a selector, a synthesizer circuit, and a controller. The signal generating circuit generates a signal having the same frequency as an output signal. The delay unit includes a plurality of delay circuits, and delays the signal generated by the signal generating circuit. The selector selects an output signal of the delay circuits. The synthesizer circuit synthesizes the signal selected by the selector, and outputs the output signal. The controller controls the selector based on data for setting a waveform of the output signal and a control signal for setting at least amplitude, phase and frequency of the output signal.

Abstract: A digital apparatus for phase aligning output signals of a silicon device to an applied input clock signal in same device allows synchronization of data transfers between the device and another device such as a controller. It includes a digital or analog oscillator of higher frequencies than the applied clock and in multiples of powers 2n where n=1, 2, 4, etc., with provisions for synchronization and control by the applied input clock. The main oscillator frequency is subdivided to lower frequencies. An internally derived duplicate frequency clock is phase shifted by either 45 or 22.5 degrees. The system measure both a desired coarse delay, and a fine delay to be applied to the path to phase align the output signal to the phase of the applied input clock.

Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.

Abstract: Equal numbers of variable capacitance elements, capacitance values of which are separately controlled according to a logic value of a corresponding bit of a delay control signal that is in a one-to-one relation with an oscillation frequency, are connected in parallel among differential outputs of all delay circuits excluding a differential non-inverting delay circuit at the end, which extracts a frequency signal to the outside. Bits of the delay control signal are connected in a one-to-one relation to the equal numbers of variable capacitance elements arranged on output sides of all the delay circuits, in a relation in which delay control signals continuous in terms of frequency are not connected to the equal number of variable capacitance elements arranged on an output side of one of the delay circuits.

Abstract: In a coupled ring oscillator including q ring oscillators each including p inverter circuits connected together to form a ring shape, and a phase coupling ring including (p×q) phase coupling circuits each of which is configured to couple an output of one of the p inverter circuits of one of the q ring oscillators to an output of one of the p inverter circuits of another one of the q ring oscillators in a predetermined phase relationship, and which are connected together to form a ring shape, for at least one group made up of one of the p inverter circuits in each of the q ring oscillators, outputs of the q inverter circuits belonging to the at least one group are fixed in phase with one another, the q ring oscillators are caused to oscillate in the in-phase fixed state, and then, the outputs of the q inverter circuits are released from the in-phase fixed state.

Abstract: Disclosed is an inverter cell design comprising first and second transistors and first and second resistors. In disclosed embodiments, the first resistor is connected to a source of the first transistor and the second resistor is connected to a source of the second transistor. The first and second resistors are configured for connection to respective first and second voltage potentials. The inverter cells may be configured in a ring oscillator. A crystal oscillator may comprise an inverter cell according to the present disclosure.

Abstract: A novel and useful apparatus and related method for on-chip measurement of the clock to output delay of a latch within an integrated circuit. The delay measurement mechanism enables measuring the time delay from the transition of the clock input to the data output of a latch. The output delay of the on-chip latch is measured by making the latch delay part of a ring oscillator and measuring its frequency of oscillation. A latch based delay stage is used to construct the ring oscillator in which a delayed short pulse derived from the input edge is used as the trigger for the latch. The latched ring oscillator mechanism of the invention can be used to measure the clock to output (C2Q) delay of on-chip latch devices.

Abstract: Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.

Abstract: The invention relates to a method and system and microchip for determining impedance of a variable impedance component. The method comprises tuning a tunable oscillator over a predefined tuning range, the tunable oscillator having the variable impedance component coupled as a load thereof. The frequency response of the tunable oscillator is measured as a function of said tuning. Finally, the measured frequency response is analyzed for determining the impedance of the variable impedance component. The invention makes possible to manufacture smaller and simpler monolithic sensor microchips.

Abstract: A PLL circuit includes a phase detector, a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares a phase of a signal Fs which is input from outside with a phase of a signal Fo/N which is input from the frequency divider. The loop filter generates a signal Vin by removing alternating current components from a signal input from the phase detector. The voltage-controlled oscillator outputs a signal Fo based on the signal Vin input from the loop filter. The frequency divider converts the signal Fo output from the voltage-controlled oscillator into Fo/N (frequency division by N), and outputs it to the phase detector.