Ring Oscillators Patents (Class 331/57)
  • Patent number: 8975974
    Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Sameer Wadhwa
  • Publication number: 20150061782
    Abstract: Structures and methods are provided for fabricating a ring oscillator including a plurality of stages. An example multi-layer structure includes a first device layer, a second device layer, and an inter-level connection structure. The first device layer includes a first transistor structure associated with a first stage of a ring oscillator. The second device layer is formed on the first device layer and includes a second transistor structure associated with a second stage of the ring oscillator. Further, the first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first transistor structure and the second transistor structure.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHAO-CHIEH LI, SHYH-AN CHI, RUEY-BIN SHEEN, CHIH-HSIEN CHANG
  • Patent number: 8970311
    Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 3, 2015
    Inventor: Mohammad Ardehali
  • Patent number: 8970312
    Abstract: There is provided a differential ring oscillation circuit including a differential ring oscillation unit in which delay circuits, to which signals of 2 phases are input, and which delay and output the input signals of 2 phases, are connected at even stages in a ring form, first and second common-mode level detection units that detect that the input signals of 2 phases of one delay circuit at an even stage of the differential ring oscillation unit and the input signals of 2 phases of one delay circuit at an odd stage of the differential ring oscillation unit are at same predetermined levels, respectively, and first and second switches that set, to specific potentials, one of the output signals of 2 phases of the delay circuit delaying the input signals of 2 phases, when the first and second common-mode level detection units detect the same predetermined levels, respectively.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventors: Kenichi Maruko, Masayuki Katakura
  • Patent number: 8963646
    Abstract: The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 24, 2015
    Assignee: Nanya Technology Corporation
    Inventor: Yantao Ma
  • Patent number: 8957736
    Abstract: The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 17, 2015
    Inventor: Akira Takizawa
  • Patent number: 8952760
    Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 10, 2015
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Shing Yu, Chia-Hsiang Chang, Ting-Hao Wang
  • Patent number: 8947168
    Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: February 3, 2015
    Assignee: Analog Devices, Inc.
    Inventor: John Wood
  • Patent number: 8941420
    Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 27, 2015
    Assignee: Rambus Inc.
    Inventors: Jared L. Zerbe, Brian S. Leibowitz, Masum Hossain
  • Patent number: 8941618
    Abstract: It is an object to provide a touch panel which includes an A/D converter circuit and has a function of image shooting with high resolution and high-level gray scale and at high operation speed. A touch panel includes a plurality of pixels each provided with a display element and a photo sensor, an A/D converter to which a first potential is applied from a photo sensor, and a reading circuit. The A/D converter includes an oscillation circuit which changes the oscillating frequency of a first signal to be generated in accordance with the first potential and stops oscillating when a second potential is applied thereto from the reading circuit, and a counter circuit which generates a second signal having a discrete value determined in accordance with the oscillating frequency.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8937512
    Abstract: A voltage-controlled oscillator is disclosed. The voltage-controlled oscillator includes an inverter circuit configured to output an oscillation signal. The first inverter circuit includes a complementary transistor pair and a transistor string. The complementary transistor pair includes a first switch transistor and a second switch transistor. The second switch transistor is connected to the first switch transistor, in which a first terminal of the second switch transistor is connected to a second terminal of the first switch transistor. The first delaying unit includes at least one delaying transistor. A first terminal of the at least one delaying transistor is connected to a control terminal of the second switch transistor. A second terminal of the at least one delaying transistor is connected to a control terminal of the first switch transistor. A control terminal of the at least one delaying transistor is configured to receive a voltage control signal.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Jr Huang, Nan-Hsin Tseng, Wei-Hao Kao, Ping-Han Tsai, Wei-Pin Changchien
  • Patent number: 8937511
    Abstract: A system including a plurality of amplifiers configured to generate a clock signal having a frequency. The clock signal is input to a processor. The amplifiers are connected in series. An output of a last one of the amplifiers is fed back to an input of a first one of the amplifiers. Each of the amplifiers has a transconductance. A frequency adjustment module is configured to adjust, based on an activity level of the processor, the frequency of the clock signal by adjusting the transconductance of the amplifiers.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: January 20, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Pantas Sutardja, Sehat Sutardja
  • Patent number: 8933756
    Abstract: A generator of very short pulses where a cascade of inverters of arbitrary length characterized in that said inverters are adapted to produce pulses on their power supply line instead of their usual output.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: January 13, 2015
    Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)
    Inventors: Edmund James Colli-Vignarelli, Catherine Dehollain, Jean-Yves Le Boudec
  • Publication number: 20150008986
    Abstract: A digital controlled oscillator includes: a delay circuit which includes m elements transmitting a pulse signal with delay; a timing signal generator generating a timing signal corresponding to timing-selection data from passing signals, based on the timing-selection data specifying any of timings which are obtained by dividing a circulation period of the pulse signal by m×n; and an output signal generator which sets the timing-selection data based on control data specifying a period of an output pulse signal and the timing-selection data, and generates the output pulse signal based on the timing-selection data by using the timing signal. The timing signal generator generates the timings obtained by dividing the circulation period by m×n by using pulse edge shift circuits which generate n shift signals whose timings differ by a unit delay from one input signal, the unit delay being 1/n of delay time in the element.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Inventor: Tomohito TERAZAWA
  • Patent number: 8928416
    Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Haibing Zhao
  • Patent number: 8928369
    Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 6, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Kent Jaeger, Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed
  • Patent number: 8912853
    Abstract: A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: James E. Burnette, Greg M. Hess, Shinye Shiu
  • Patent number: 8890626
    Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Iuan Liu
  • Patent number: 8890627
    Abstract: A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 18, 2014
    Assignee: Via Technologies, Inc.
    Inventor: Yeong-Sheng Lee
  • Patent number: 8884707
    Abstract: An oscillator is disclosed that can generate an oscillation signal using a latch and two delay elements. For some embodiments, the oscillator includes an SR latch, a first delay element, and a second delay element. The SR latch has a first input, a second input, a first output, and a second output. The first delay element is coupled between the first output and the first input of the SR latch. The second delay element is coupled between the second output and the second input of the SR latch. For some embodiments, the first and second delay elements include a programmable pull-up circuit that allows the charging current to be adjusted in discrete amounts, and include a programmable capacitor circuit that allows the capacitance value to be adjusted in discrete amounts.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Emmanouil Terrovitis, Abbas Komijani
  • Patent number: 8878616
    Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 4, 2014
    Assignee: Oracle International Corporation
    Inventors: Anand Dixit, Robert P. Masleid
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8873690
    Abstract: A method and system of applying modulated carrier signals to tree networks and processing signals tapped from the tree networks to generate output signals with phase-synchronized carriers are disclosed.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: October 28, 2014
    Assignee: Blue Danube Labs, Inc.
    Inventors: Mihai Banu, Vladimir Ivanov Prodanov
  • Patent number: 8860511
    Abstract: A frequency divider of an injection locked type capable of division by 2, division by 4, and further division by 8 with a simpler configuration is disclosed and the frequency divider includes a ring oscillator including M (M is an even number) delay elements, the tails of two delay elements M/2 delay elements apart from each other are connected to a differential pair and transistors, to the gates of which the input oscillation signal is applied, are connected to the differential pair, and the differential pair is caused to generate a differential signal of the input oscillation signal, which is a divide-by-2 signal of the input oscillation signal, and when dividing the frequency of the input oscillation signal by 8, the portion of the differential pair to be connected to the tail of the delay element is caused to have a two-stage configuration, which is a vertically stacked configuration.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kenichi Okada, Ahmed Magdi Hassan Musa
  • Patent number: 8860513
    Abstract: An apparatus comprises a ring oscillator comprising a plurality of delay cells connected in cascade, a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells and a replica injection apparatus comprising a plurality of replica buffers, wherein the replica buffers receive the reference clock from their inputs and the replica buffers are configured such that the replica buffers are tri-stated and each output is connected to ground when the ring oscillator operates in an injection-locked mode and each output is connected to ground through a capacitor when the ring oscillator operates in a calibration mode.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventor: Euhan Chong
  • Patent number: 8860512
    Abstract: A ring oscillator includes a ring of a plurality of delay elements and a start edge injector for injecting a start edge into the ring. The start edge injector varies an injection point for the start edge in the ring.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: October 14, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventor: Markus Schimper
  • Publication number: 20140292420
    Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Michael M. Green, Xiaoyan Gui
  • Patent number: 8847691
    Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Zhi Zhu, Xiaohua Kong, Nam V. Dang
  • Patent number: 8841974
    Abstract: A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number of inverters connected back-to-back and operable to produce an oscillatory output, and a test structure coupled to provide either an observability chain input or a test input to the ring oscillator and to receive the oscillatory output as a feedback from the ring oscillator.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: September 23, 2014
    Assignee: Silicon Image, Inc.
    Inventors: Chinsong Sul, Hyukyong Kwon, Andy Ng
  • Publication number: 20140266476
    Abstract: A clock system including a ring oscillator having a plurality of cascaded inverters, each of the cascaded inverters having a pair of inputs coupled to outputs of a respectively adjacent inverter stage and having a pair of outputs coupled to inputs of another respectively adjacent inverter stage, each inverter stage having a common mode control circuit provided therein, and a feedback controller adapted to transmit a control signal to the common mode control circuit of at least one of the inverters.
    Type: Application
    Filed: October 31, 2013
    Publication date: September 18, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Shawn S. KUO
  • Publication number: 20140266475
    Abstract: Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jeffrey Mark Hinrichs, Luis Chen
  • Patent number: 8836435
    Abstract: An oscillator circuit includes a circuit loop and multiple current sources. The circuit loop includes an output having the oscillating signal. The multiple current sources are turned on independently of a phase of the oscillating signal. The current sources control magnitudes of both charging current and discharging current at nodes of the circuit loop, including the output. Relative magnitudes of different current sources determine a frequency of the oscillating signal.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 16, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Tien-Yen Wang
  • Publication number: 20140253250
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 11, 2014
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Publication number: 20140240053
    Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: MediaTek Inc.
    Inventors: Yi-Chieh HUANG, Ping-Ying WANG
  • Patent number: 8816778
    Abstract: A method for adjusting an oscillator clock frequency, comprising: providing a first oscillator, applying a first setpoint value to the first oscillator, determining a first oscillator frequency value within a first time frame, providing a second oscillator, applying a second setpoint value to the second oscillator, determining a second oscillator frequency value within a second time frame, determining a new frequency setpoint value from the first and second frequency values, the first and second setpoint values, and a desired frequency value, and applying the new frequency setpoint value to one of the first and second oscillators.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 26, 2014
    Assignee: INSIDE Secure
    Inventors: Gaetan Bracmard, Jean-Pascal Maraninchi, Julien Roche
  • Patent number: 8816782
    Abstract: A voltage controlled oscillator includes a plurality of serially connected composite gain stages. A composite gain stage includes a transconductance stage and a transimpedance stage. The transconductance stage has first and second current paths from a first power supply voltage terminal to a second power supply voltage terminal. A first variable resistance is coupled between the first and second current paths. The transimpedance stage has a first inverter and a second inverter. The first inverter has an input terminal coupled to the output of the first current path and an output terminal. The second inverter has an input terminal coupled to the output of the second current path, and an output terminal. A second variable resistance is coupled between the input terminal and the output terminal of the first inverter, and a third variable resistance is coupled between the input terminal and the output terminal of the second inverter.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: August 26, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Yi Cheng Chang
  • Patent number: 8810323
    Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided that includes: a plurality of differential inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, wherein each transistor in the differential pair couples to a power source through a corresponding switching-capacitor circuit; and a bias circuit configured to generate the bias voltage such that a transconductance for each transistor in the differential pairs is proportional to a factor that is a function of a ratio of transistor widths within the bias circuit.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: August 19, 2014
    Inventor: Mohammad Ardehali
  • Patent number: 8810298
    Abstract: Circuits and circuit elements configured to generate a random delay, a monostable oscillator, circuits configured to broadcasting repetitive messages wireless systems, and methods for forming such circuits, devices, and systems are disclosed. The present invention advantageously provides relatively low cost delay generating circuitry based on TFT technology in wireless electronics applications, particularly in RFID applications. Such novel, technically simplified, low cost TFT-based delay generating circuitry enables novel wireless circuits, devices and systems, and methods for producing such circuits, devices and systems.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: August 19, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Vivek Subramanian, Mingming Mao, Zhigang Wang
  • Patent number: 8811926
    Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 19, 2014
    Assignee: University of Washington Through its Center for Commercialization
    Inventors: Brian Patrick Otis, Jagdish Narayan Pandey
  • Patent number: 8810324
    Abstract: The present invention relates to an oscillating device, which comprises a driving module and an oscillating module. The driving module is used for producing a first driving voltage and a second driving voltage. The oscillating module comprises a first symmetric load circuit, a second symmetric load circuit, and a bias circuit. The first symmetric load circuit and the second symmetric load circuit produce a bias according to the first driving voltage. The bias circuit produces a bias current according to the second driving voltage. The oscillating module produces an oscillating signal according to the first driving voltage and the bias current, where the bias current is proportional to the bias. Thereby, by making the driving signal produced by driving module proportional to the bias of the oscillating module, simple compensation for temperature and process can be performed. Thereby, the frequency can be tuned using a few calibration bits.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 19, 2014
    Assignee: Sitronix Technology Corp.
    Inventors: Chih-Te Hung, Cheng-Chung Yeh
  • Patent number: 8803617
    Abstract: Oscillator circuitry having a switching inverting amplifier arranged in a ring oscillator configuration of at least two stages. A bias generator for supplying the amplifiers of neighboring stages, is responsive to an enable signal to supply the amplifiers only when the enable signal is asserted. A first pair of transistors, coupled to an input of one of the amplifiers and the other coupled to an output of the amplifier, the transistors being driven in common by the enable signal such that when the enable signal is deasserted the transistors of the pair are turned on to impose conflicting levels at the input and the output such that the amplifier is forced to switch.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jin Liang, David Grant, Larry Wofford
  • Patent number: 8804445
    Abstract: The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: August 12, 2014
    Assignee: National Chiao Tung University
    Inventors: Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee
  • Patent number: 8804397
    Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: August 12, 2014
    Assignee: Rambus Inc.
    Inventors: Marko Aleksic, Brian S. Leibowitz
  • Patent number: 8797106
    Abstract: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by a variable delay. The variable delay increases responsive to a rising magnitude of a supply voltage provided to the variable delay circuit stage.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Publication number: 20140210562
    Abstract: A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 31, 2014
    Applicant: Realtek Semiconductor Corp.
    Inventor: Chuan Ping TU
  • Publication number: 20140210561
    Abstract: There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.
    Type: Application
    Filed: December 16, 2013
    Publication date: July 31, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Shinichi MORIWAKI
  • Patent number: 8791763
    Abstract: Tunable injection locked (IL) dividers having enhanced locking range, good phase noise performance, and low power consumption are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes an oscillator and at least one IL divider. The oscillator provides an oscillator signal at a first frequency. The at least one IL divider receives the oscillator signal and provides an output signal at a second frequency, which is related to the first frequency by an overall divider ratio for the IL divider(s). Each IL divider may be calibrated based on a target frequency of that IL divider. Each IL divider may be calibrated (e.g., by tuning at least one adjustable capacitor) to obtain an oscillation frequency within a predetermined tolerance of the target frequency of that IL divider. The oscillator may be calibrated based on a target oscillation frequency of the oscillator.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: July 29, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Mazhareddin Taghivand
  • Patent number: 8791765
    Abstract: A Force-Mode Distributed Wave Oscillator (FMDWO) that provides accurate multiple phases of an oscillation, a Force Mode Distributed Wave Antenna as a radiating element, a Force-Mode Distributed Oscillator Amplifier (FMDOA) and an array of amplifiers capable of operating as a beam forming phased-array antenna driver. Two distinct force mode mechanisms, one delay-based and the other geometry-based, utilizing inverter amplifiers, inject an oscillation on independent conductor loops or rings via transmission lines forming a differential transmission medium for the oscillation wave. Once the oscillation wave is initiated through the forcing mechanisms, the oscillations continue uninterrupted independent of any external triggering.
    Type: Grant
    Filed: December 31, 2010
    Date of Patent: July 29, 2014
    Assignee: Waveworks, Inc.
    Inventors: Ahmed Emira, Ahmet Tekin, Damir Ismailov, Suat Utku Ay
  • Patent number: 8791764
    Abstract: Disclosed is a digitally controlled oscillator which includes a ring oscillator; and a variable resistance bank connected between one power node of the ring oscillator and a power supply terminal and having the resistance value varied according to the number of active bits of a control code. The frequency of an clock signal output by the ring oscillator is changed non-linearly according to the resistance value of the variable resistance bank. The frequency of the output clock signal is changed stepwise linearly according to the number of active bits of the control code.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongshin Shin, JaeHyun Park
  • Patent number: 8786374
    Abstract: An error detection system employs a chain of delay elements connected in an open loop configuration. To determine whether the oscillator is operating within a specified set of parameters, the error detection system applies a start pulse to an input of the open-loop chain of delay elements. The error detection system compares the resulting output signal with the output of the oscillator. If the oscillator has locked onto a harmonic of the intended output frequency, the comparison of the output signals will indicate an error.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jon S. Choy