Abstract: A first ring oscillator outputs a reference clock signal. A table acquirer acquires a control-value table representing a correspondence between time zones in which the first ring oscillator operates and division ratios of the reference clock signal. In accordance with the control-value table, a divider generates an RTC signal by changing a division ratio of the reference clock signal for each time zone in which the first ring oscillator operates. During execution of calibration of the control-value table, a second ring oscillator outputs a measurement clock signal that oscillates more accurately than the reference clock signal. A frequency measurer measures a frequency of the RTC signal based on the measurement clock signal. In a case in which a frequency of the RTC signal exceeds an allowable error, an update determiner updates at least part of division ratios in the control-value table.

Abstract: Methods, systems, and computer products are presented herein for generating a clock signal using an on-chip ultra-low power (ULP) RC oscillator. An on-chip ultra-low power (ULP) RC oscillator comprises a first comparator, a second comparator, and a flip flop. The first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit. Each of the first bias voltage and the second bias voltage directly varies with a thermal voltage. A flip-flop is electrically coupled to the first comparator and the second comparator. The flip-flop is configured to generate a clock signal based on the first and the second comparator output signals.

Abstract: A duty cycle corrector (DCC) includes a first duty cycle correction circuit, a second duty cycle correction circuit, and overshoot prevention circuit connected between the first duty cycle correction circuit and the second duty cycle correction circuit. Each of the duty cycle correction circuits include a capacitor, two inverters, a resister, and two switches.

Abstract: Provided is a circuit device including: an oscillation circuit configured to generate an oscillation signal; a waveform shaping circuit configured to shape the oscillation signal into a clock signal having a rectangular wave; a low-pass filter configured to smooth the clock signal and generate a detection voltage corresponding to a duty of the clock signal; and a differential amplifier configured to output a bias voltage based on a difference between the detection voltage and a reference voltage to an input node of the waveform shaping circuit, in which a unity gain frequency of the differential amplifier is lower than a cutoff frequency of the low-pass filter.

Abstract: An oscillator includes first and second comparators, a first impedance network having a first trim element therein, and a second impedance network having a second trim element therein. The first impedance network is electrically connected to a first input terminal of the first comparator, and the second impedance network is electrically connected to a first input terminal of the second comparator. The first and second impedance networks are configured to cause an improvement in common mode variation within the first and second comparators, in response to trimming of at least one of the first and second trim elements.

Abstract: The disclosed device includes a reference delay circuit for outputting a reference delay circuit output signal from a voltage regulated supply and a noisy delay circuit for outputting a noisy delay circuit output signal from a noisy or droopy supply. The device also includes a phase comparator circuit that is connected to the reference delay circuit and the noisy delay circuit. The phase comparator circuit outputs a phase difference between the reference delay circuit output signal and the noisy delay circuit output signal. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: According to one embodiment, an oscillation circuit includes: a ring oscillator; a first transistor having a gate terminal coupled to an output port of the ring oscillator and a drain terminal coupled to a first node; a second transistor having a drain terminal and a gate terminal that are both coupled to the first node; a third transistor having a gate terminal coupled to the first node and a drain terminal coupled to a second node; a fourth transistor having a gate terminal coupled to the first node and a drain terminal coupled to a third node; a fifth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node; and a voltage buffer having an input port coupled to the second node.

Abstract: A crystal oscillator having a voltage regulator configured to receive a first power supply voltage and output a second power supply voltage; a source follower configured to receive the second power supply voltage and output a third power supply voltage in accordance with a control voltage; a first inverter operating under the third power supply voltage and configured to receive a first oscillatory signal from a first node and output a second oscillatory signal at a second node; a second inverter operating under the third power supply voltage and configured to output a third oscillatory signal; a crystal placed across the first node and a second node; a first shunt capacitor configured to shunt the first node to ground; a second shunt capacitor configured to shunt the second node to ground; and a clocked lowpass filter configured to output the control voltage in accordance with the pulsed signal.

Abstract: A memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. The clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.

Abstract: Some embodiments include apparatuses and methods using a supply node to receive a die voltage; a delay line to stretch and squish a first clock signal in response to changes in the die voltage to generate a second clock signal; a frequency clamp circuit to receive the second clock signal and generate a third clock signal that is clamped below a frequency; and a squash controller to squash the third clock signal when the die voltage crosses at least one of a first threshold and a second threshold.

Abstract: Systems and methods are provided for generating a stable reference current that has low sensitivity to operating temperature and supply voltage variations and is stable across process corners. In an example implementation, an improved reference current generator circuit is provided that includes a first circuit generating a first current that is proportional to absolute temperature and a second circuit generating a second current that is complementary to absolute temperature based on first transistors operating in respective triode regions. The second current compensates for process, voltage, and temperature variations in the first current at a node. According to some examples, the second current is also generated based on second transistors operating in respective saturation regions. The first current may be generated using a forward biased PN junction diode.

Abstract: Methods and apparatus for a desaturation circuit having a temperature compensated voltage threshold for protecting a power transistor, such as a FET. A comparator module has a first input compared to a voltage source associated with current through the FET and a second input coupled to the voltage threshold circuit. As a resistance of the FET changes due to temperature changes, the voltage threshold changes to compensate for the resistance change of the FET.

Abstract: A device including delay cells connected in series and in a feedback loop to provide a ring oscillator. At least one of the delay cells in the ring oscillator is a stacked gate delay cell that includes two or more PMOS transistors having first drain/source paths connected in series to each other and having first gates connected to each other and two or more NMOS transistors having second drain/source paths connected in series to each other and to the first drain/source paths and having second gates connected to each other and to the first gates.

Abstract: An amplitude regulator circuit portion is arranged to supply a current to an inverter in an oscillator circuit. The regulator monitors a voltage at the input terminal of the inverter and varies the current supplied to the inverter in response to the monitored voltage. The amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors and is arranged such that an input node is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of the first NMOS and first PMOS transistors. The amplitude regulator also comprises a back-bias circuit portions arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, to vary a threshold voltage, where the threshold voltage of the second NMOS transistor is lower than that of the first NMOS transistor.

Abstract: A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.

Abstract: An integrated circuit device includes a plurality of integrated circuit chips located on a common substrate, each respective integrated circuit chip from among the plurality of integrated circuit chips including functional circuitry, a clock generator, clock circuitry including clock terminals at an edge of the respective integrated circuit chip, initial clock conductors configured to conduct a clock signal output by the clock generator from the clock generator to the clock terminals, and functional clock conductors configured to conduct the clock signal from the clock terminals to the functional circuitry. Each respective chip is located on the common substrate in an orientation that exposes the clock terminals on the respective chip to face corresponding clock terminals on at least one other chip among the plurality of integrated circuit chips, configured for interconnection of the plurality of integrated circuit chips into a multi-chip module with a common clock.

Abstract: A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

Abstract: A gate driver includes a gate current circuit and a driver logic circuit. The gate current circuit has a gate current circuit output and includes first and second current sources coupled to the gate current circuit output. The driver logic circuit has a capacitor and is configured to: charge and discharge the capacitor to generate a detect voltage across the capacitor; cause the first current from the first current source to flow to the gate current circuit output in response to a voltage on the gate current circuit output being below the detect voltage; and cause the second current from the second current source to flow to the gate current circuit output in response to the voltage on the gate current circuit output being above the detect voltage.

Abstract: A circuit device includes a waveform-shaping circuit that waveform-shapes an oscillation signal and provides an output clock signal based on a clock signal. A bias voltage output circuit of the circuit device provides a bias voltage of the oscillation signal that is input to the waveform-shaping circuit. A comparator of the circuit device compares a DC voltage obtained by smoothing the clock signal with a reference voltage. A logic circuit of the circuit device sets an adjustment value of the bias voltage. In a test mode of the logic circuit, the logic circuit changes the adjustment value to determine a set value of the adjustment value based on output of the comparator when the adjustment value is changed and stores the determined set value in a storage circuit.

Abstract: Various embodiments of the present technology comprise a method and system for induction heating. The system may provide a first induction coil wrapped around a metal cylinder and a second induction coil wrapped around the metal cylinder. The first induction coil may carry a current in a first direction and the second induction coil may carry a current in an opposite, second direction. The currents may be generated in an alternating sequence.

Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.

Abstract: A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

Abstract: An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

Abstract: A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.

Abstract: The invention relates to a radio frequency assembly comprising a radio frequency circuit comprising at least one group of N?2 amplifiers (A1, A2) disposed in series on a substrate (1), said assembly comprising a package (2) wherein the substrate (1) is disposed, each amplifier comprising a local grounding point (b1, b2, b3) and a local feed point (a1, a2, a3), said common grounding points being connected to a common ground (GND) outside the package (2), said common feed points being connected to a common power supply (VDD) outside the package, said assembly comprising at least N?1 parallel LC circuits disposed between the common power supply (VDD) and the local feed point (a2, a3) of an amplifier (A2) so as to attenuate the current loops between two amplifiers in series.

Abstract: This frequency tripler system uses a cascade of integrated transistor circuit differential limiting amplifiers and tunable notch filters that can directly serve one or more outputs, such as a direct clock or local oscillator drive. With this topology, filtering is distributed between two or more stages of differential limiting amplifiers and tunable notch filters. This enables suppression of smaller fundamental tone by the differential limiting amplifiers along with the tunable notch filters and yields a strong third harmonic signal to directly drive high performance mixers and digital-to-analog converters.

Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

Abstract: An apparatus is disclosed for providing frequency stabilization. The apparatus includes a first supply voltage node, a second supply voltage node, an oscillator circuit coupled to the first supply voltage node, at least one clock buffer coupled to the second supply voltage node and an output of the oscillator circuit, and at least one load circuit. The at least one clock buffer is configured to selectively be in a disabled state or an enabled state to pass the clock signal to at least one client of multiple clients. The at least one load circuit includes an input coupled to the output of the oscillator circuit. The at least one load circuit also includes an output configured to be coupled to a ground. The at least one load circuit is configured to be connected to the first supply voltage node for at least a portion of time.

Abstract: Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing.

Abstract: A control circuit includes an oscillator configured to provide, to a digital load, a clock signal having an oscillation period that (i) depends on a supply voltage and (ii) is greater than a critical path delay of the digital load. The control circuit also includes a control module configured to provide the supply voltage to the digital load and the oscillator and adjust the supply voltage based on (i) a degree of a voltage difference between the supply voltage and a reference voltage and (ii) a degree of a phase difference between the clock signal and a reference clock such that the oscillator changes the oscillation period to reduce the degree of the phase difference between the clock signal and the reference clock.

Abstract: A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

Abstract: A compensation module, an oscillation circuit and associated compensation method for reducing an oscillation frequency variation in an output oscillation signal of a voltage-controlled oscillator (VCO) core are provided. The compensation module includes a compensation circuit and a polarity selection circuit. The compensation circuit has a capacitance value related to voltages of a first and a second receiving terminals. The oscillation frequency variation is changed with the capacitance value. The polarity selection circuit conducts a periodic regulated signal to one of the first receiving terminal and the second receiving terminal. The polarity selection circuit conducts a filtered bias signal to the other of the first receiving terminal and the second receiving terminal. The periodic regulated signal is sensitive to a regulated voltage variation, and the filtered bias signal is insensitive to the regulated voltage variation.

Abstract: A digital-to-time converter has an oscillator; and count circuitry that starts counting a number of oscillations of the oscillator when an activation signal is input, and outputs a first delay activation signal obtained by delaying the activation signal during a period from a timing when the activation signal is input to a timing when a counted number of oscillations reaches a reference number set based on a digital input signal.

Abstract: A power transfer device includes an oscillator circuit having a first node, a second node, and a control terminal. The oscillator circuit includes a cascode circuit comprising transistors having a first conductivity type and a first breakdown voltage. The cascode circuit is coupled to the control terminal, the first node, and the second node. The oscillator circuit includes a latch circuit coupled between the cascode circuit and a first power supply node. The latch circuit includes cross-coupled transistors having the first conductivity type and a second breakdown voltage. The first breakdown voltage is greater than the second breakdown voltage. The oscillator circuit may be configured to develop a pseudo-differential signal on the first node and the second node. The pseudo-differential signal may have a peak voltage of at least three times a voltage level of an input DC signal on a second power supply node.

Abstract: In accordance with an embodiment, a voltage controlled oscillator (VCO) includes a VCO core having a plurality of transistors and a varactor circuit that has a first end coupled to emitter terminals of the VCO core and a second end coupled to a tuning terminal. The varactor circuit includes a capacitance that increases with increasing voltage applied to the tuning terminal with respect to the emitter terminals of the VCO core.

Abstract: Aspects of the present disclosure provide a radio frequency (RF) system that may be implemented in a variety of devices. For example, the RF system may include a plurality of first RF-modules, each configured to process RF signals received from a corresponding antenna array to generate intermediate frequency (IF) signals and to process IF signals for transmission via the antenna array, wherein the plurality of first RF modules are coupled to each other via a first interface comprising transmission lines for carrying at least an IF signal, a local oscillator (LO) signal, and a control signals; at least one second RF module; and a baseband module configured to provide IF signals, the LO signal, and the control signals to one of the first RF modules via a second interface and to provide at least IF signals to the second RF module via a third interface.

Abstract: A circuit for reducing inductor magnetic-core loss is disclosed. The circuit includes a switch transistor, a PWM signal source connecting to the switch transistor, an inductor connecting to the switch transistor, a load connecting to the switch transistor, and a frequency adjustment circuit. The frequency adjustment circuit obtains PWM signals from the PWM signal source and modulates the PWM signals to be a new square-wave signals to be outputted to the switch transistor. The switch transistor is configured for setting the frequency of the square-wave signals as the operation frequency so as to control a duration for which the current flowing through the inductor. The operation frequency of the switch transistor may be adjusted by modulating the frequency of the PWM signals. As such, the duration for which the current flowing through the inductor may be controlled so as to decrease the current amount flowing through the inductor.

Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.

Abstract: The RF stacked power amplifier comprises a voltage-dividing circuit, a negative feedback bias circuit, a current source circuit and a stacked amplifying circuit. The voltage-dividing circuit receives a system voltage and divides the system voltage for outputting a first reference partial voltage and a second reference partial voltage. The negative feedback bias circuit receives a negative feedback reference voltage and correspondingly outputs a second bias reference voltage according to a result of comparing the second reference partial voltage and the negative feedback reference voltage. The current source circuit determines a bias reference current according to the first reference partial voltage. The stacked amplifying circuit outputs the negative feedback reference voltage and determines an operation bias point according to a first bias reference voltage and the bias reference current.

Abstract: Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.

Abstract: A diathermy apparatus includes a cylindrical coil (24) defining an opening (42), a pair of capacitors of substantially similar capacitance (20 and 22), each capacitor connected to one end of the coil, an RF signal source (26), and a balun (28) connected between the RF signal source (26) and the pair of capacitors (20 and 22). The balun (28) is operative for converting an unbalanced signal received from the RF signal source (26) into a balanced signal supplied to coil (24) via the pair of capacitors (20 and 22). Desirably, the cylindrical coil is a conical cylindrical (or cone-shaped) spiral coil.

Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.

Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.

Abstract: The present invention is to provide a frequency jitter circuit and a method for generating frequency jitter. The frequency jitter circuit, comprising: an oscillating circuit, configured to generate an oscillating frequency output signal; a decoding circuit, configured to be controlled by said oscillating frequency output signal for generating several pulse output signals; a delay circuit, through which said oscillating frequency output signal is passed for generating a frequency jitter output signal that is delayed a period of time compared to said oscillating frequency output signal. Application of the invention into switched-mode power supply might reduce EMI average noise in the switched-mode power supply, and smooth energy spectrum density.

Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: An improved local oscillator (LO) driver circuit for a mixer, the LO driver circuit includes a gain circuit responsive to LO input signals at a predetermined LO frequency range. At least a first pair of a parallel combination of a resistor and a capacitor is coupled to the gain circuit and to LO inputs of the mixer. The resistor configured to increase impedance at low frequencies of the frequency range and the capacitor is configured to reduce the impedance of the first parallel combination at high frequencies of the frequency range to reduce resistive impendence of the resistor. At least a second pair of a parallel combination of a low quality factor inductor and a high quality factor inductor is connected to the first pair. The second pair in serial combination with the first pair is tuned to provide a constant desired load impedance and a constant desired voltage swing at the LO inputs of the mixer over the predetermined LO frequency range.

Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.

Abstract: A clock supplying device for supplying a clock signal to be used in an operation of a communication apparatus, includes an oscillator for generating the clock signal; a measurement unit for acquiring a reference clock signal extracted from a transmission line connected to the communication apparatus, and measuring a frequency difference between the clock signal and the reference clock signal; and a determiner for determining whether a warm-up operation of the oscillator unit has been completed or not, in accordance with measurement results of the frequency difference and a status of power supplying.

Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.