Combined With Particular Output Coupling Network Patents (Class 331/74)
  • Patent number: 9525439
    Abstract: Aspects of the present disclosure provide a radio frequency (RF) system that may be implemented in a variety of devices. For example, the RF system may include a plurality of first RF-modules, each configured to process RF signals received from a corresponding antenna array to generate intermediate frequency (IF) signals and to process IF signals for transmission via the antenna array, wherein the plurality of first RF modules are coupled to each other via a first interface comprising transmission lines for carrying at least an IF signal, a local oscillator (LO) signal, and a control signals; at least one second RF module; and a baseband module configured to provide IF signals, the LO signal, and the control signals to one of the first RF modules via a second interface and to provide at least IF signals to the second RF module via a third interface.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 20, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventor: Alon Yehezkely
  • Patent number: 9438111
    Abstract: A circuit for reducing inductor magnetic-core loss is disclosed. The circuit includes a switch transistor, a PWM signal source connecting to the switch transistor, an inductor connecting to the switch transistor, a load connecting to the switch transistor, and a frequency adjustment circuit. The frequency adjustment circuit obtains PWM signals from the PWM signal source and modulates the PWM signals to be a new square-wave signals to be outputted to the switch transistor. The switch transistor is configured for setting the frequency of the square-wave signals as the operation frequency so as to control a duration for which the current flowing through the inductor. The operation frequency of the switch transistor may be adjusted by modulating the frequency of the PWM signals. As such, the duration for which the current flowing through the inductor may be controlled so as to decrease the current amount flowing through the inductor.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: September 6, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Fei Li
  • Patent number: 9153303
    Abstract: Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eric Becker
  • Patent number: 9148088
    Abstract: The RF stacked power amplifier comprises a voltage-dividing circuit, a negative feedback bias circuit, a current source circuit and a stacked amplifying circuit. The voltage-dividing circuit receives a system voltage and divides the system voltage for outputting a first reference partial voltage and a second reference partial voltage. The negative feedback bias circuit receives a negative feedback reference voltage and correspondingly outputs a second bias reference voltage according to a result of comparing the second reference partial voltage and the negative feedback reference voltage. The current source circuit determines a bias reference current according to the first reference partial voltage. The stacked amplifying circuit outputs the negative feedback reference voltage and determines an operation bias point according to a first bias reference voltage and the bias reference current.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: September 29, 2015
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Jaw-Ming Ding
  • Patent number: 9077348
    Abstract: Various embodiments of the invention allow the generation of an output clock signal that comprises a frequency that is a fractional frequency of an input clock signal and is adjusted with respect to an input signal. A fractional clock generator that has high performance output, low power consumption, small area, and good jitter performance is presented.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Haichen Liu
  • Patent number: 9050166
    Abstract: A diathermy apparatus includes a cylindrical coil (24) defining an opening (42), a pair of capacitors of substantially similar capacitance (20 and 22), each capacitor connected to one end of the coil, an RF signal source (26), and a balun (28) connected between the RF signal source (26) and the pair of capacitors (20 and 22). The balun (28) is operative for converting an unbalanced signal received from the RF signal source (26) into a balanced signal supplied to coil (24) via the pair of capacitors (20 and 22). Desirably, the cylindrical coil is a conical cylindrical (or cone-shaped) spiral coil.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: June 9, 2015
    Assignee: ReGear Life Sciences, Inc.
    Inventor: Robert M. Unetich
  • Patent number: 9007135
    Abstract: A slew rate enhancing system includes a first input configured to receive a first complementary signal of a differential pair and a second input configured to receive a second complementary signal of the differential pair. The slew rate enhancing system further includes a first switch configured to selectively connect the first input to an output in response to a voltage of the second input being greater than a first predetermined voltage. The slew rate enhancing system further includes a second switch configured to selectively connect the first input to the output in response to the voltage of the second input being less than a second predetermined voltage.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: April 14, 2015
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8994462
    Abstract: The present invention is to provide a frequency jitter circuit and a method for generating frequency jitter. The frequency jitter circuit, comprising: an oscillating circuit, configured to generate an oscillating frequency output signal; a decoding circuit, configured to be controlled by said oscillating frequency output signal for generating several pulse output signals; a delay circuit, through which said oscillating frequency output signal is passed for generating a frequency jitter output signal that is delayed a period of time compared to said oscillating frequency output signal. Application of the invention into switched-mode power supply might reduce EMI average noise in the switched-mode power supply, and smooth energy spectrum density.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: March 31, 2015
    Assignee: Hangzhou Silan Microelectronics Co., Ltd.
    Inventors: Weijiang Zhou, Yunlong Yao
  • Patent number: 8994458
    Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: March 31, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Martin Saint-Laurent
  • Patent number: 8981854
    Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8975975
    Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 10, 2015
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, William Dawson Kesling, Alexander Lalexan Lyakhov, Maynard C. Falconer, Harry G. Skinner
  • Patent number: 8937514
    Abstract: An improved local oscillator (LO) driver circuit for a mixer, the LO driver circuit includes a gain circuit responsive to LO input signals at a predetermined LO frequency range. At least a first pair of a parallel combination of a resistor and a capacitor is coupled to the gain circuit and to LO inputs of the mixer. The resistor configured to increase impedance at low frequencies of the frequency range and the capacitor is configured to reduce the impedance of the first parallel combination at high frequencies of the frequency range to reduce resistive impendence of the resistor. At least a second pair of a parallel combination of a low quality factor inductor and a high quality factor inductor is connected to the first pair. The second pair in serial combination with the first pair is tuned to provide a constant desired load impedance and a constant desired voltage swing at the LO inputs of the mixer over the predetermined LO frequency range.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: January 20, 2015
    Assignee: Hittite Microwave Corporation
    Inventors: B. Tarik Cavus, Abdullah Celebi
  • Patent number: 8928369
    Abstract: An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 6, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Kent Jaeger, Lawrence E. Connell, Daniel P. McCarthy, Brian T. Creed
  • Patent number: 8907688
    Abstract: A clock supplying device for supplying a clock signal to be used in an operation of a communication apparatus, includes an oscillator for generating the clock signal; a measurement unit for acquiring a reference clock signal extracted from a transmission line connected to the communication apparatus, and measuring a frequency difference between the clock signal and the reference clock signal; and a determiner for determining whether a warm-up operation of the oscillator unit has been completed or not, in accordance with measurement results of the frequency difference and a status of power supplying.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Limited
    Inventor: Hiroyoshi Yoda
  • Patent number: 8902007
    Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8866557
    Abstract: Resistor bias circuitry is included in components of an XTAL oscillator system to reduce 1/f noise. An XTAL oscillator includes a resistor bias circuit attached to the XTAL core. A common mode feedback OP amp connected to the XTAL core also includes a resistor bias circuit. An XTAL oscillator chain includes an XTAL core, common mode feedback OP amp, common mode logic buffer (CML BF), and differential to CMOS converter (D2C) each with resistor bias circuitry.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Broadcom Corporation
    Inventors: Chang-Hyeon Lee, Lindel Kabalican
  • Patent number: 8860514
    Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
  • Patent number: 8854145
    Abstract: Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Yuyu Chang, John Leete, Walid Ahmed, Wei Luo
  • Publication number: 20140292425
    Abstract: An output circuit includes a first circuit that generates a first output voltage based on a resistance ratio, on the basis of a reference voltage, a second circuit that compares the first output voltage with a source voltage of a second transistor that sets a second output voltage of the output signal, and generates an output gate voltage for causing the first transistor to output the second output voltage, and a third circuit that controls a timing at which the output gate voltage is applied to the first transistor, on the basis of an input control signal.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 2, 2014
    Applicant: Seiko Epson Corporation
    Inventor: Minoru Kozaki
  • Patent number: 8818317
    Abstract: The present invention is applied to a frequency converter used for a receiver. The frequency converter according to the present invention includes an LO signal generator (11) that generates an LO signal and outputs the LO signal; and a mixer (10) that multiplies a received signal that has been band-limited in a usable bandwidth of said receiver by the LO signal so as to convert the frequency of the received signal and outputs the resultant signal, wherein said LO signal generator is capable of varying a phase resolution, and said frequency converter is capable of varying a signal gain for each phase value of the LO signal.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 26, 2014
    Assignee: NEC Corporation
    Inventor: Masaki Kitsunezuka
  • Patent number: 8797110
    Abstract: A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 5, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Fan, Yiwu Tang, Kevin Hsi Huai Wang
  • Publication number: 20140211560
    Abstract: A semiconductor integrated circuit according to an embodiment includes an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state. The semiconductor integrated circuit includes a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad. The semiconductor integrated circuit includes a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage.
    Type: Application
    Filed: July 30, 2013
    Publication date: July 31, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiharu HIRATA
  • Patent number: 8779863
    Abstract: A method of generating a first oscillator signal having a desired frequency in a first frequency range comprises generating in a voltage controlled oscillator unit a second oscillator signal having a frequency in a second frequency range of at least one octave. The method further comprises selecting said second continuous frequency range to have a lower endpoint in said first frequency range and an upper endpoint above said range; and selectively using the oscillator signal unchanged or dividing it by a division ratio selected from integer powers of the number 2 to obtain said first oscillator signal. By centering the VCO higher than otherwise required and using an additional divider, so that the VCO signal can selectively be used unchanged or divided, a sufficient margin below as well as above the desired range for e.g. drift and tolerances of the VCO is achieved. It also simplifies the VCO design.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: July 15, 2014
    Assignee: Ericsson Modems SA
    Inventor: Magnus Nilsson
  • Publication number: 20140182361
    Abstract: A sensor for detecting analytes, a method of making the sensor, and a method of using the sensor. In one embodiment, the present invention comprises at least one array comprising a plurality of resonators. The resonators can be arranged in a plurality of rows and a plurality of columns, and can be connected in a combined series-parallel configuration. The resonators can be adapted to vibrate independently at about the same resonance frequency and about the same phase. The sensor can also comprise an actuator and a signal detector electrically coupled to the array. The sensor can also further comprise an analyte delivery system and can be functionalized for detection of at least one analyte.
    Type: Application
    Filed: January 25, 2013
    Publication date: July 3, 2014
    Applicant: California Institute of Technology
    Inventors: Igor Bargatin, John Sequoyah Aldridge, Edward Myers, Michael L. Roukes
  • Patent number: 8723607
    Abstract: A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: May 13, 2014
    Assignee: Cambridge Silicon Radio Limited
    Inventors: Michael Story, Nicolas Sornin
  • Patent number: 8710932
    Abstract: A signal processing device includes a signal processing chip and a conducting path. The signal processing chip includes: a first port capable of receiving a first oscillating signal; a second port capable of outputting a second oscillating signal derived from the first oscillating signal; and a third port. The conducting path is external to the signal processing chip and coupled to the second port and the third port, and the conducting path is capable of transmitting the second oscillating signal outputted from the second port to the third port.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 29, 2014
    Assignee: Mediatek Inc.
    Inventors: Hao-Jung Li, Tung-Yi Wang
  • Patent number: 8710933
    Abstract: A disclosed oscillation circuit includes a constant-voltage generation circuit, an oscillation generation circuit configured to generate an oscillation output, an output circuit including a plurality of parallelly arranged MOSFET circuits, to which a constant voltage generated by the constant-voltage generation circuit is supplied as a supply voltage, output points of the plurality of MOSFET circuits being mutually connected, and a drive circuit configured to drive a selected MOSFET circuit selected in response to a selection input among the plurality of MOSFET circuits by the oscillation output, wherein an output from an unselected MOSFET circuit among the plurality of MOSFET circuits other than the selected MOSFET circuits has a high impedance.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Takayuki Nakamura, Minoru Sakai
  • Patent number: 8704604
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 22, 2014
    Assignee: Sand 9, Inc.
    Inventors: Klaus Juergen Schoepf, Reimund Rebel, Jan H. Kuypers
  • Publication number: 20140097909
    Abstract: A high-frequency power source generation device includes switching element groups having a configuration in which a plurality of switching elements turned on/off cyclically are connected in parallel. One parallel connection terminal of the switching element group is connected to a positive electrode terminal of a DC power source, and one parallel connection terminal of the switching element group is connected to a negative electrode terminal of the DC power source. Respective other parallel connection terminals of the switching element groups are connected via a reactor. A pulse voltage that appears at opposite ends of the reactor due to a cyclic on/off operation of the switching element groups is applied to a load through a coaxial cable and a matching circuit.
    Type: Application
    Filed: May 21, 2012
    Publication date: April 10, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takashi Hashimoto, Junichi Shibata, Yoshikazu Ukai
  • Patent number: 8686801
    Abstract: In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: April 1, 2014
    Inventors: Ralf Beier, Gerhard Osterloh, Michael Gattung
  • Patent number: 8686800
    Abstract: A system for generating a frequency reference signal comprising an oscillator, a direct digital synthesizer coupled to the oscillator and configured to receive a signal output from the oscillator, a digital to analog converter coupled to the direct digital synthesizer and configured to receive a sampled signal from the direct digital synthesizer and to convert the sampled signal to an analog waveform, and a bandpass filter coupled to the digital to analog converter and configured to select an aliased output signal from the digital to analog converter at a Nyquist zone other than a first Nyquist zone and to output the frequency reference signal.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: April 1, 2014
    Assignee: Comtech EF Data Corp.
    Inventors: Cris Mamaril, Tiberiu Artzi, Terry Richmond
  • Patent number: 8674606
    Abstract: Systems, methods and apparatus for reducing instabilities in a plasma-based processing system are disclosed. An exemplary method includes applying power to a plasma with a power amplifier; determining whether low frequency instability oscillations are present or high frequency instability oscillations are present in the plasma; and altering, based upon whether high or low frequency instability oscillations are present, an impedance of a load that is experienced by the power amplifier, the load experienced by the power amplifier including at least an impedance of the plasma.
    Type: Grant
    Filed: April 25, 2010
    Date of Patent: March 18, 2014
    Assignee: Advanced Energy Industries, Inc.
    Inventors: Daniel Carter, Victor Brouk, Jeff Roberg
  • Patent number: 8669820
    Abstract: An oscillator circuit includes a clock oscillator which outputs a main clock signal having an oscillating frequency switched between a high frequency and a low frequency in response to a frequency selection signal, and a frequency divider circuit which outputs a sub-clock signal having a divided frequency equivalent to a frequency division ratio of the oscillating frequency of the main clock signal, the frequency division ratio being switched in response to the frequency selection signal. The divided frequency of the sub-clock signal is predetermined for each of the high frequency and the low frequency to which the oscillating frequency is switched in response to the frequency selection signal.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: March 11, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Makio Abe, Fumihiro Inoue, Junichi Kimura
  • Patent number: 8670322
    Abstract: A millimeter-wave radio frequency (RF) system, and method thereof for transferring multiple signals over a single transmission line connected between modules of a millimeter-wave RF system. The system comprises a single transmission line for connecting a first part of the RF system and a second part of the RF system, the single transmission line transfers a multiplexed signal between the first part and second part, wherein the multiplexed signal includes intermediate frequency (IF) signal, a local oscillator (LO) signal, a control signal, and a power signal; the first part includes a baseband module and a chip-to-line interface module for interfacing between the baseband module and the single transmission line; and the second part includes a RF module and a line-to-chip interface module for interfacing between the RF module and the single transmission line, wherein the first part and the second part are located away from each other.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 11, 2014
    Assignee: Wilocity, Ltd.
    Inventors: Alon Yehezkely, Ori Sasson
  • Publication number: 20140043105
    Abstract: Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
    Type: Application
    Filed: April 18, 2012
    Publication date: February 13, 2014
    Applicant: Rambus Inc.
    Inventors: Jared L. Zerbe, Barry W. Daly, Dustin T. Dunwell, Anthony C. Carusone, John C. Eble, III
  • Patent number: 8638176
    Abstract: A slew rate enhancing system includes first and second modules. The first module is configured to generate a first output signal in response to complementary first and second input signals. The second module is configured to generate a second output signal in response to the first and second input signals. The first module is configured to switch between tracking the first input signal and not tracking the first input signal during each half cycle of the first input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the first module. The second module is configured to switch between tracking the first input signal and not tracking the second input signal during each half-cycle of the second input signal based on values of the first input signal, the second input signal, and a predetermined threshold of the second module.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 28, 2014
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8624680
    Abstract: In one embodiment, there is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: January 7, 2014
    Inventors: Steven T. Stoiber, Stuart Siu
  • Patent number: 8618891
    Abstract: Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function; thereby providing two simultaneous operations being determined in place of the one differential function.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: December 31, 2013
    Assignee: Tensorcom, Inc.
    Inventor: Syed Enam Rehman
  • Patent number: 8610509
    Abstract: A method for generating an oscillator signal uses a multiphase oscillator having a plurality of input stages and a reference stage. Each input stage produces an input stage voltage that represents a phase for the oscillator. The input stage voltages produced by each of the input stages are compared to a reference voltage produced by the reference stage. An input stage having a maximum input stage voltage is selected and an output of the selected input stage having the maximum input stage voltage is changed. A current need of the oscillator is detected with a negative feedback loop coupled to the reference stage. An appropriate supply current is provided to each input stage with the negative feedback loop.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: December 17, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Behzad Mohtashemi, Allen Chang
  • Patent number: 8610511
    Abstract: The high-frequency digitally controlled oscillator includes fully digital cells capable of being ported to any CMOS fabrication process. The oscillator has a basic modular architecture comprising a digitally controlled digital ring oscillator (DRO) having a plurality of delay stages, a counter divider and a selection multiplexer. The DRO generates the basic (intrinsic) high frequency range and the counter provides the remaining ranges through division by multiples of two. The multiplexer provides a selection mechanism for the required range of frequencies. Load capacitances to the delay stages are added/removed to control delay via utilization of a unique capacitive cell driven synchronously by two ring oscillators such that the capacitance could be added or removed utilizing the Miller effect. Moreover, multiple capacitive load cells can be added to the same stage.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 17, 2013
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventor: Muhammad E. S. Elrabaa
  • Patent number: 8604644
    Abstract: A load impedance decision device, a wireless power transmission device, and a wireless power transmission method are provided. At least one of a distance and an angle between two resonators may be measured. A load impedance may be determined based on at least one of the measured distance and the measured angle. When the distance between the two resonators changes, a high power transfer efficiency may be maintained without using a separate matching circuit. Where the load impedance is determined, a test power may be transmitted. Depending on a power transfer efficiency of the test power, the load impedance may be controlled and power may be wirelessly transmitted from the source resonator to the target resonator.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Seok Park, Sang Wook Kwon, Young-tack Hong
  • Patent number: 8604890
    Abstract: A method and a circuit for increasing a resolution of a digitally controlled oscillator include controlling the oscillator so that an output signal of the oscillator varies between semi-periods having a first frequency and semi-periods having a second frequency. The method and circuit further include applying the output signal of the oscillator as an input to a divider to obtain a divided signal. A frequency of at least one semi-period of the divided signal is a function of both an oscillator semi-period having the first frequency and an oscillator semi-period having the second frequency.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 10, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Alberto Marinas, Jose Ibanez Climent, Roberto Munoz, Pedro Lopez Canova
  • Patent number: 8570108
    Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ashwin Ragunathan, Marzio Pedrali-Noy, Sameer Wadhwa
  • Publication number: 20130278345
    Abstract: An adaptor for a solid-state oscillator and related microwave adaptors includes an input segment of a conductive material, a first coaxial portion that includes a first inner conductor coupled to the input segment and a first outer shielding segment, and a capping portion coupled to the first coaxial portion to electrically couple the first inner conductor and the first outer shielding segment.
    Type: Application
    Filed: September 9, 2012
    Publication date: October 24, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Tiefeng Shi, Jun Li
  • Patent number: 8564377
    Abstract: A piezoresistive MEMS oscillator uses an output circuit to control the voltage across the resonator body. This results in a DC bias of the resonator. A current path is provided between the output of the output circuit and the resonator body, such that changes in current through or voltage across the resonator body, resulting from changes in resistance of the resonator body, are coupled to the output. This arrangement uses the bias current flowing through the resonator to derive the output. In this way, the same DC current is used to provide the required DC resonator bias and to drive the output circuit to its DC operating point.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 22, 2013
    Assignee: NXP B.V.
    Inventors: Petrus Antonius Thomas Marinus Vermeeren, Jozef Thomas Martinus van Beek
  • Patent number: 8558626
    Abstract: An integrated circuit comprising oscillator circuitry is arranged to generate a clock signal for functional logic module of the integrated circuit. The oscillator circuitry comprises a plurality of propagation paths, and is arranged to apply a transition signal to inputs of the plurality of propagation paths, and to cause the output clock signal to transition based on a propagation of the transition signal through a determined set of the propagation paths.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: October 15, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Amir Zaltzman
  • Patent number: 8536951
    Abstract: A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: September 17, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Puneet Sareen
  • Patent number: 8531246
    Abstract: A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Silicon Laboratories Inc.
    Inventor: Yunteng Huang
  • Patent number: 8508307
    Abstract: An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: August 13, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazuhiro Mitsuda, Koji Okada, Suguru Tachibana
  • Patent number: 8476982
    Abstract: A method and device for managing a reference oscillator within a wireless device is presented. The method includes selecting reference oscillator parameters associated with the lowest reference oscillator error, where the selection is based upon reference oscillator parameters derived using different technologies within a wireless device, acquiring a satellite based upon the selected reference parameters, determining the quality of the satellite-based position fix, and updating the reference oscillator parameters based upon the quality of the satellite-based position fix.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: July 2, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Emilija M. Simic, Dominic Gerard Farmer, Borislav Ristic, Ashok Bhatia