Abstract: A voltage controlled current source outputs oscillator drive current and oscillator equivalent current. A signal oscillator outputs first source oscillation signal and second source oscillation signal. A differential amplifier outputs first amplification oscillation signal and second amplification oscillation signal. First switch circuit and second switch circuit output first current oscillation signal and second current oscillation signal, respectively. A first current value converter-amplifier circuit converts a value of the first current oscillation signal whereas a second current value converter-amplifier circuit converts a value of the second current oscillation signal, so that the thus converted values become output current finally. An adder outputs to the differential amplifier a differential amplifier drive current in which equivalent current for use with conversion is added up with the oscillator equivalent current outputted from the voltage controlled current source.

Abstract: An integrated circuit has an internal oscillator circuit for being connected to an external frequency source such as a crystal or a ceramic resonator. The internal oscillator circuit has an inverting amplifier across the frequency source terminals to establish an oscillation there. One terminal of the frequency source is coupled to one input of the comparator and to a second input of the comparator through a low pass filter. Coupling the output of the low pass filter to the second input of the comparator is for preventing a DC offset from developing between the two inputs of the comparator. The other terminal of the frequency source is coupled to the second input of the comparator through a high pass filter. The high pass filter provides the comparator with a larger voltage differential to increase noise margin. Noise margin is further improved by allowing an increase in hysteresis in the comparator.

Abstract: The invention discloses an oscillator circuit (100, 200, 300, 400), comprising an oscillating element (110, 210, 310, 410) and output means (115, 215, 315, 415) for outputting an oscillation frequency from the oscillating circuit. The circuit further comprises a signal delay means (120, 220, 320, 420) which is arranged in series with the oscillating element and feeds the output signal back to the oscillating element. The delay means is (120, 220, 320, 420) tuneable with respect to the delay it provides. The oscillating element can be an amplifier or a VCO, and the delay means can be a Delay Locked Loop or a tuneable delay line, depending on the embodiment of the invention.

Abstract: An integrated circuit device comprising a configurable reference clock output to a peripheral function connection of the integrated circuit device provides a system clock or a frequency divided clock from the system clock as a clock source to a peripheral function on a peripheral function connection of the integrated circuit device. The clock function may be used to generate all necessary clocks for a plurality of integrated circuit devices and may be able to supply a system clock or frequency divided clock from the system clock, either from an external clock oscillator source or from an internally generated system clock, with the option of using a crystal for more accuracy and greater frequency stability. The external clock and/or internal clock may be made available for peripheral devices even when internal logic of the integrated circuit device may be in a standby/sleep mode.

Abstract: Network aware oscillator synchronization via a computer network. A correction processor connected to an oscillator uses precision timing signals propagated over a digital network to generate an error signal. IEEE-1588 time synchronization protocols produce precision time signals which are converted to precision interval signals. In one embodiment a correction processor uses the precision interval signals to count pulses of the oscillator. A correction circuit compares the counter output with a predetermined value and generates an error signal. The error signal may be used to correct the oscillator, as in a voltage controlled oscillator. Or, the error signal may be propagated to consumers of the oscillator. This error signal, for example, may be used to correct an instrument display. An arbitrary reference oscillator may be used to generate the precision timing signals propagated on the network, slaving other oscillators to it.

Abstract: System and method for adjusting supply voltage to VCO to minimize affects of circuit noise on VCO. Method includes obtaining a number of data points each by incrementing a counter by the number of VCO periods during a phase of a local oscillator, changing the supply voltage, decrementing the counter by the number of VCO periods during another phase of the local oscillator, and then storing the net count. Then among the saved data points a data point is selected that is the point at or near where the VCO is least sensitive to supply changes and the VCO is set to operate at the supply voltage corresponding to this data point. A system includes a controller, up/down counter, local oscillator, and VCO. The counter counts the oscillations of the VCO and a stored net counts provide information as to where the VCO is least sensitive to the supply voltage.

Abstract: A transmission oscillator of differential output configuration is incorporated into a high frequency IC. Further, an equivalent impedance having an impedance equivalent to the impedance connected with a regular output terminal is provided. Or, a dummy external terminal for outputting transmit signals in opposite phase is provided. One of the differential outputs of the transmission oscillator is inputted to the power amplifier through the regular output terminal. The other of the differential outputs is connected to the equivalent impedance or the dummy external terminal.

Abstract: A glitch free controlled ring oscillator may comprise a programmable delay chain connected to a gating and inverter stage or means. A latch or latching means may be provided between the delay chain and the gating and inverter stage or means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to the registered clock state.

Abstract: A crystal oscillator operates at the third overtone of the crystal's fundamental frequency. A value of a shunt resistor between the two phase-shift leg nodes is chosen so that the absolute value of the product gm×(Xc1)×(Xc2) is greater than the effective reactance of the crystal, where gm is the gain of the amplifier attached to the phase-shift legs, and Xc1 and Xc2 are the effective capacitive reactances of phase-shift legs at nodes X1 and X2. The third overtone is doubled by a multiplier and the final output filtered to remove the third overtone and select a frequency six times the fundamental frequency. A pair of Colpitts or Pierce amplifier half circuits is attached to the phase-shift leg nodes. The leg nodes can be capacitively isolated from Pierce-amplifier circuit nodes to improve start-up. Frequency doubling can be performed by summing currents from the two oscillator half circuits.

Abstract: A programmable reference-less oscillator provides a wide range of programmable output frequencies. The programmable reference-less oscillator is implemented on an integrated circuit that includes a free running controllable oscillator circuit such as a voltage controlled oscillator (VCO), a programmable divider circuit coupled to divide an output of the controllable oscillator circuit according to a programmable divide value. A non-volatile storage stores the programmed divide value and a control word that controls the output of the controllable oscillator circuit. The control word provides a calibration capability to achieve a desired output frequency in conjunction with the programmable divider circuit. Open loop temperature compensation is achieved by adjusting the control word according to a temperature detected by a temperature sensor on the integrated circuit. Additional clock accuracy may be achieved by adjusting the control word for process as well as temperature.

Abstract: One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the integrated circuit can be altered based on the process corner of the integrated circuit as fabricated.

Abstract: A device for operating an oscillatable unit of a vibration resonator, including a piezodrive, which is connected with the oscillatable unit, and feedback electronics. The feedback electronics excites the piezodrive to oscillate by means of a periodic exciter signal having rising and falling edges. The response signal of the piezodrive is fed back to the feedback electronics. Present additionally is at least one peak compensation unit, which removes from the response signal at least one interference signal, which results from the charge-reversal process of the piezodrive. Provided in the peak compensation unit, is at least one suppression unit having at least one switch element. The suppression unit is controlled by the exciter signal of the feedback electronics in such a manner that the piezodrive is connected conductively to ground during the rising and/or during the falling edges of the exciter signal.

Abstract: An oscillator circuit includes first and second transistors forming a differential pair, an output combiner connected to first terminal sides of the first and second transistors, and a current source connected to second terminal sides of the first and second transistors.

Abstract: A method, circuit, and system are disclosed. In one embodiment, the method comprises receiving a differential clock signal from two clock signal lines into a first differential pair of transistors of a first size, receiving the differential clock signal from the two clock signal lines into a second differential pair of transistors of a size smaller than the first size, converting the differential clock signal into a single-ended clock signal, outputting the single-ended clock signal through an inverter, and synchronizing any differential clock phase error by controlling the transconductance between the first differential pair of transistors and the second differential pair of transistors.

Abstract: A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay locked loop. The delays are a small fraction of the clock period, thus providing resolution greater than that of the circuit clock.

Abstract: The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.

Abstract: An oscillation circuit for generating two oscillation signals having a phase difference of 90° by using an LC oscillator has a disadvantage for integration. Therefore, a differential type ring oscillator comprising interpolation type delay circuits of four stages is used as an original oscillator without using any LC oscillator. The oscillation frequency of the original oscillator is set to f/2. Intermediate signals S(k) having a phase difference of 45(k?1)° with respect to a reference phase are obtained as the outputs of the respective stages of the original oscillator. A multiplying circuit 22 generates the product signal of S(2) and S(4) in mixers. This product signal is vibrated at cos (ft/2), and the output signal Vout1 is generated on the basis of the product signal. A multiplying circuit generates the product signal of S(1) and S(3) in mixers. This product signal is vibrated at cos(ft/2+?/2), and the output signal Vout2 is generated on the basis of the product signal.

Abstract: A semiconductor integrated circuit includes a reference-voltage circuit configured to produce a predetermined reference voltage at an output node thereof, a comparator, coupled to a node to which an oscillating signal is supplied and to the output node of the reference-voltage circuit, to produce a result of comparison at an output node thereof, the result of comparison being made by comparing a voltage of the oscillating signal with the predetermined reference voltage, and a detection circuit coupled to the output node of the comparator to produce, in response to the result of comparison, a stable-state-detection signal indicating that the oscillating signal has an amplitude larger than the reference voltage.

Abstract: An oscillation frequency control circuit comprises a frequency counter that counts to measure a frequency of an oscillating signal outputted from an oscillation circuit which produces the oscillating signal of the frequency corresponding to analog control voltages inputted, a plurality of D/A converters that produce the analog control voltages respectively corresponding to digital values inputted, a digital value generator that generates the digital values according to control signals inputted, and an operation circuit that compares the frequency measured by the frequency counter with a reference frequency and produces the control signals, which are inputted to the digital value generator, corresponding to the comparing result.

Abstract: The oscillator circuit comprises a capacitor and first to fourth constant current supplies and switches are connected to the capacitor. Both terminals of the capacitor are used for charges and discharges. One period comprises four steps; charging the first terminal of the capacitor, discharging the second terminal, charging the first terminal, and discharging the second terminal.

Abstract: Provided is a multi-mode open-loop type clock extraction apparatus. In the apparatus, a power divider block divides an input data signal into two data signals. A first band-pass filter block and a second band-pass filter block extract a first clock frequency component or a second clock frequency component contained in the data signal output from the power divider. A first amplifier block and a second amplifier block amplify the first clock frequency component and the second clock frequency component respectively. Accordingly, it is possible to extract the respective clock signals corresponding to N data rates from the N data signals with various data rates using a single clock extraction apparatus.

Abstract: A voltage comparing circuit activates a first voltage comparison signal when a control voltage is lower than a first reference voltage and a second voltage comparison signal when the control voltage is higher than a second reference voltage. In synchronization with a count clock, a counter decrements a counter value during activation of the first voltage comparison signal and increments the counter value during activation of the second voltage comparison signal. An oscillating circuit selects one of oscillation frequency bands by the counter value and regulates an oscillation frequency according to the control voltage within the selected oscillation frequency band to output an output clock. This makes it possible to secure a wide oscillation frequency range in response to variance in operating conditions or a reduction in a range of the control voltage and to regulate the oscillation frequency of the voltage controlled oscillator by the control voltage alone.

Abstract: Disclosed herein is a method and apparatus used to create an idealized voltage controlled oscillator (VCO) which allows very high modulation rates without the expected phase noise (jitter) which nominally comes from wide bandwidth VCOs. In this fashion, high quality VCOs that typically offer pure signals at the cost of small tuning bandwidths can be enhanced to create idealized VCOs that offer both high quality (low jitter) and high tuning bandwidths. A high-frequency phase modulator and control voltage processing is used in conjunction with a natural VCO to create a method and apparatus in accordance with the invention. The control voltage processing includes separation of frequency components of the controlling voltage and electrical integration of high-frequency control voltage components directed to the phase modulator to create the overall voltage-to-frequency transfer function for the ideal VCO.

Abstract: A timer circuit that has a normal mode and a test mode is disclosed. The test mode includes a power-up phase and a power-down phase. The timer circuit includes an oscillator and a first timer circuit portion coupled to the oscillator. The first timer circuit portion includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the first timer circuit portion is taken from the output associated with the first timer circuit portion in the power-up phase. The timer circuit further includes a second timer circuit portion coupled to the first timer circuit portion and the oscillator. The second timer circuit portion also includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the second timer circuit portion is taken from the output associated with the second timer circuit portion in the power-down phase.

Abstract: A clock anomaly detection circuit includes: a dividing unit configured to output a divided target clock by dividing frequency of a target clock; a first time width measurement unit configured to obtain values of the divided target clock using rising edges of a monitoring clock that is synchronized with the target clock, and to measure an H level time with and an L level time width; a second time width measurement unit configured to obtain values of the divided target clock using falling edges of the monitoring clock, and to measure an H level time with and an L level time width; and an anomaly determination unit configured to determine that the target clock is abnormal when an anomaly is detected in the H level time width or the L level time width measured in the first time width measurement unit and when an anomaly is detected in the H level time width or the L level time width measured in the second time width measurement unit.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: Circuits, methods, and apparatus that provide low-noise, high-stability crystal oscillators having controlled-amplitude differential output signals and DC level control. A crystal oscillator circuit has two feedback loops, one for setting the DC level of its signals, the other for adjusting the amplitude of those signals. The DC level feedback loop can set the DC component of the oscillator signals to a voltage midway between two supply voltages. The amplitude control loop sets the amplitude of the output of the crystal oscillator signal to be within a range. The amplitude can be set to provide a maximum swing without clipping the supply voltages in order to provide high-stability and minimal jitter. The amplitude control circuit can also be digital for improved noise performance. The time constants of these two loops can be separated such that instabilities are avoided.

Abstract: A method and system for scaling a phase lock loop (PLL) based clock, includes: selecting a clock frequency; selecting a reference frequency, multipliers, and an output divider for an output frequency of a PLL, where the output frequency is higher than the clock frequency; applying the multipliers and the output divider to the reference frequency to generate the output frequency, outputted to a programmable logic chip; and applying a counter factor to the output frequency by the programmable logic chip to generate the clock frequency. By scaling the reference frequency in more than one step, the middle ranges of the multipliers are widened, allowing for a greater granularity of control over the increments by which the reference frequency can be adjusted. Smaller frequency errors result. The printer emulator utilizing the present invention has a set of more exactly generated clock frequencies that emulate a variety of printer speeds and resolutions.

Abstract: A voltage-controlled oscillator for generating differential output is disclosed. The voltage-controlled oscillator comprises a Colpitts oscillator having a first inductor and a capacitive divider having at least two capacitors connected in series. A varactor is connected in series with the capacitive divider and to a reference voltage, and a second inductor is mutually coupled to the first inductor for providing the differential output. A second inductor is substantially centrally tapped and connected to the reference voltage for providing a substantially balanced output. The operating frequency of the voltage-controlled oscillator is dependent on an applicable potential difference across the varactor.

Abstract: A circuit controls the pulse width of an output signal from a voltage controlled oscillator. The voltage controlled oscillator includes a ring oscillator comprising a plurality of series-connected inverters. In one embodiment a selector selects at least one output signal from an inverter in the plurality of series-connected inverters. An output circuit receives the selected output signal and a reference signal to provide a final output signal having a time duration proportional to the number of inverters between the inverters providing the reference signal and the output signal to the selection circuit.

Abstract: An oscillator according to the present invention reduces power consumption by enlarging the pulsewidth of an oscillator output pulse. Since this pulse disables an oscillator current source, the enlarged pulsewidth reduces the time the current source is enabled. When a first capacitor charges to at least a reference voltage, a differential amplifier produces a low level signal that is provided to a latch generating the output pulse. The low level signal controls the latch to produce and maintain a high level signal until the latch is triggered. The latch signal disables the current source, while enabling a transistor to transfer charge from the first capacitor to a second capacitor. When the second capacitor attains a sufficient voltage, the latch is triggered to produce a low level signal, thereby enlarging the pulsewidth of the output pulse. The low level signal enables the current source and facilitates discharge of the second capacitor.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=1/4*(f4) causing a coarse frequency adjustment and a signal A=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.

Abstract: A frequency generation apparatus and a method are provided. The frequency generation apparatus for generating a plurality of center frequencies for use in multi-band hopping communication, includes: an oscillator generating an oscillation frequency; a reference frequency generator multiplying the oscillation frequency by a first multiplication rate to generate a reference frequency; a compensation frequency generator multiplying the oscillation frequency by a second multiplication rate to generate a compensation frequency for compensating for the influence of a frequency offset of the oscillation frequency; and a center frequency generator generating the plurality of center frequencies using the reference frequency and the compensation frequency. Therefore, by compensating for the influence of a frequency offset of an oscillation frequency on the generation of center frequencies, it is possible to generate stable center frequencies.

Abstract: The disclosure relates to an automatic level control technique for RF amplifiers in a communication system, such as a wireless communication system. The invention provides an automatic level control technique to compensate for variations in the gain of an RF amplifier, which may be a transmitter amplifier or a receiver amplifier. In accordance with the invention, the gain of the RF amplifier can be controlled as a function of the output of a voltage controlled oscillator (VCO) circuit provided in the communication system. A VCO typically includes a buffer amplifier with a structure similar to that of the RF amplifier used in the transmit or receive side of the RF front-end. By tracking changes in the output of the VCO buffer amplifier, an automatic level control (ALC) input to the RF amplifier can be adjusted to compensate for process- and temperature-based variations in amplifier gain.

Abstract: An automatic gain control (AGC) circuit is applied to control a margin voltage of an oscillator. The margin voltage is the voltage difference between a high-level output and a low-level output of the oscillator. The AGC circuit of the present invention includes a comparator and a processing unit. Wherein, the comparator compares the margin voltage of the oscillator and a reference voltage. Based on the output of the comparator, the processing unit outputs a ripple code to determine the value of a driving current output from a current generator. The oscillator generates an oscillation output to the comparator based on the driving current.

Abstract: Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means and characterized in that the modulator means are coupled to amplifier means via an adder for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (V.sub.T) provided to the modulator means.

Abstract: An example embodiment is directed to shifting the common mode voltage of an analog oscillation stage toward a center line between the upper and lower power-supply rails of a first digital circuit. The first digital circuit has a digital input port adapted to respond to signal transitions defined between the supply rails, and the analog oscillation stage generates an oscillating analog signal that has a common-mode voltage that is not centered between the upper and lower power-supply rails. The oscillating analog signal, which drives the digital input port, changes alternately with the phases of the oscillating analog signal. To shift the common mode voltage of an analog oscillation stage toward the center line between the rails, a feedback circuit generates a contending digital signal that drives the digital input port with alternating states as defined by opposite phases.

Abstract: A synchronous signal generator according to the present invention outputs a pulse with low jitter by setting the sine wave output of a crystal oscillator close to an ideal sine wave, and converting it into a pulse signal. By passing the sine wave output from the crystal oscillator of an oscillation frequency f through a filter unit having an equal center frequency f0, inputting output of a filter unit into a pulse converter, and converting the result into a pulse of a rectangular waveform, thereby obtaining an output signal. By configuring the filter unit by the crystal filter and setting it equal to the crystal oscillator in frequency-temperature characteristic, an output signal can be obtained with low jitter although the temperature changes.

Abstract: A detection device for detecting an oscillator is provided. The detection device includes an oscillator control circuit, a frequency-decreasing circuit and a display circuit. The oscillator control circuit is used for outputting the oscillator signal of the oscillator. The frequency-decreasing circuit is connected to the output of the oscillator control circuit and has a capacitor suitable for charging and discharging and a resistor, which can adjust the time constant of the oscillator signal. The display circuit is connected to the frequency-decreasing circuit for showing the output signal of the frequency-decreasing circuit. The detection device can decide whether the oscillator is normal or broken by observing a component of the display circuit, for example, the twinkling of a light emitting diode of the display circuit.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A given length of an input signal can be detected with small power consumption. A real time clock apparatus has an oscillating module which outputs an original oscillating clock signal having a predetermined frequency, a plurality of dividing modules which divides the original oscillating clock signal outputted from the oscillating module to generate clock signals having a period different from each other, a clock selecting circuit which outputs a clock signal having a given period outputted from the dividing module based on the supplied selection signal, and a signal detecting circuit which is connected to an external switch and which detects a length of an inputted signal by a clock signal outputted from the clock selecting circuit and senses whether the inputted signal is an input signal from the switch.

Abstract: The invention relates to a device, especially an active backscatter transponder, for generating an oscillator signal based on a base signal. It comprises an oscillator for actively constructing the oscillator signal by oscillations, an input for the base signal and an output for the oscillator signal produced. The oscillator can be induced by the base signal to generate oscillator signal in a quasi-coherent manner to the base signal. For the transmission of data, the device further has a data insertion device for inserting data or a data signal into the oscillator signal. A corresponding suitable receiver receives and processes the received signal that was generated and transmitted by such a device as a quasi-coherent signal. A separation device removes the signal portions of the oscillator from the received signal via the base signal of a receiver-side oscillator, with a data retrieval device for retrieving the inserted data.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs) adapted to be connected in a loop; a state machine coupled to the plurality of DLEs and operative to provide state data for the plurality of DLEs; a start oscillation signal receiving circuit coupled to the loop and operative to trigger the loop in response to receipt of a start oscillation signal; and a calibration circuit coupled to the loop and operative to acquire calibration data for the plurality of DLEs.

Abstract: A clock signal generating circuit is provided. The clock signal generating circuit includes a clock signal generator and a filter circuit. The clock signal generator generates a clock signal of a predetermined frequency. The filter circuit is electronically connected to the clock signal generator to receive the clock signal. The filter circuit has a resonance frequency equaling the predetermined frequency for eliminating harmonic components of the clock signal having a higher frequency than the predetermined frequency, and outputs a filtered clock signal.

Abstract: A circuit and corresponding method for doubling the frequency of an input signal, even when the input signal is of low frequency or a square wave. The input signal is applied to a phase-shifting circuit that produces a pair of output signals that are theoretically 90° apart in phase, but may lack the desired form if the original input signal is of low frequency. The waveforms of the two output signals are enhanced in latching hysteresis buffers that produce more uniformly squared waves, with zero crossings corrected to be more exactly 90° apart and with desirably steep state transitions. The enhanced-waveform output signals are coupled to an exclusive OR (XOR) gate to produce a double-frequency output.

Abstract: The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.

Abstract: A divider for a local oscillator (LO) generator system of a phase locked loop (PLL) in a transceiver chip. The divider includes at least one divider unit. Each divider unit includes a frequency divider unit for receiving an input signal having an input frequency and for outputting an output signal having an output frequency which is approximately one half of the input frequency. Each divider unit also includes a resistor bank coupled between a voltage source and the frequency divider unit, and a current stirring unit for supplying current to the frequency divider unit. The resistance of the resistor bank and a magnitude of the current supplied by the current stirring unit are variable depending on the input frequency.

Abstract: An open-loop switching amplifier achieves synchronous operation using a ring oscillator based upon a tapped delay line. A counter is clocked from the ring oscillator, periodically comparing incoming more significant data to the value of the counter to form a pulsewidth modulated output waveform. Modulating the effective width of the output waveform in incremental delay line taps is equivalent to incoming less significant data. This technique then effects time-period summation of coarse and fine resolution clocked data.

Abstract: A local oscillator (LO) generator for driving a bank of mixers that provides precise phase relationship between multi-phase LO outputs comprises a shift register using slave-master-slave flip-flop elements. The LO generator can be used over a wide operating frequency range. The LO generator is suitable for driving a multi-phase LO clock input to a harmonic suppression mixer. A pattern generator produces a pattern signal and a reclocking signal that determines the frequency of the LO signals and the phase delay between the LO output phases.