Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A phase locked loop circuit includes a phase/frequency detector which uses a divider circuit and feedback from a clock distribution tree to generate INC and DEC pulses which have no "dead zone". A pair of charge pumps receives the INC and DEC pulses. One charge pump is a differential pump and has voltage controlled common mode feedback circuit to maintain a common mode controlled voltage. A differential current is outputted to a loop filter capacitor by this charge pump. The other charge pump is a single-ended output pump which supplies current to a current controlled oscillator which also receives input from a voltage to current converter. The current controlled oscillator includes a variable resistance load which varies inversely with the magnitude of the input current. A jitter control circuit is provided which reduces jitter in the current controlled oscillator output in the locked phase.

Abstract: A phase-locked loop (PLL) frequency synthesizer is connected in reverse to a reference signal and a controlled oscillator loop including a low pass filter and a voltage-controlled oscillator (VCO). Rather than receiving a reference signal through a reference oscillator input and a VCO output signal through a VCO input, the PLL frequency synthesizer receives a reference signal through the VCO input and receives the VCO output signal through the reference oscillator input. Additionally, the output of the PLL is taken from the buffered reference output, thereby eliminating the need for an external buffer. Accordingly, the data loaded into the PLL frequency synthesizer accommodates the reversed input scheme by altering the divide ratios and inverting the phase detector output signal.

Abstract: A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

Abstract: A bit synchronizing circuit is provided with both analog and digital devices in an enhanced bit synchronizing circuit system. There is provided a digital phase detector and a digital lock detector which are compatible with analog circuity. The output of the digital phase detector is coupled to an analog summing circuit having an output which is coupled to a low pass filter (LPF). The analog output of the LPF is coupled to the input of a voltage controlled oscillator (VCO) which produces a data rate clock. The output of the digital lock detector is coupled to an analog summing circuit having an output coupled to a low pass filter (LPF). The output of the LPF is coupled to a comparator for generating a lock indication signal output. The output of the comparator is also coupled to a sweep circuit which is coupled to an input of the voltage controlled oscillator for resolving frequency uncertainties in the bit synchronizing circuit.

Abstract: A lock detection circuit (112) includes a first sampler (113) which samples an input signal (102) at a rate of an output signal (109) to provide a sampled input signal. A second sampler (114) which samples a feedback signal (111) at the rate of the output signal (109) to provide a sampled feedback signal. The sampled input signal is subsequently sampled by a third sampler (115) at the rate of the feedback signal. The sampled feedback signal is subsequently sampled by a fourth sampler (116) at the rate of the input signal. The second sampled input signal and the second sampled feedback signal are subsequently compared (117) and when they substantially match, an indication (122) is set to indicate that phase and/or frequency lock has been obtained.

Abstract: A received carrier containing pseudonoise-modulation and with additive noise is correlated with a local pseudonoise signal having the same binary sequence but an unknown time delay. A second correlation is performed using a signal derived from the local pseudonoise signal (in a preferred embodiment, its time derivative). The bandpass filtered outputs of the two correlators are used as inputs to a third correlator, whose low-pass filtered output controls the time delay of the local pseudonoise signal to form a delay lock loop in which the delay may be measured and low-frequency modulation extracted from the signal. This delay lock loop has improved noise rejection as compared to prior art loops, and does not experience the "cycle slip" effects observed in coherent delay lock loops of conventional design.

Abstract: A pro-capture circuit for a phase locked loop detects when the phase locked loop is operating outside of its operating range, and then forces the phase locked loop back into the proper range. The principle of detection is general and may be adapted to work in distinct phase locked loop designs. More particularly, the pro-capture circuit is used in a phase locked loop having a normal operating range in which an output signal of the phase locked loop varies between a minimum normal value and a maximum normal value. The pro-capture circuit includes circuitry for sensing when the output signal is outside the normal operating range and circuitry for forcing the output signal to reenter the normal operating range.

Abstract: According to an output from a voltage-controlled oscillator, there are generated by a fractional divider a high-frequency division signal and a low-frequency division number. A phase comparison is conducted between the high-frequency division signal and a high-frequency reference signal by a phase comparator. A phase comparison is carried out between the low-frequency division signal and a low-frequency reference signal by a phase comparator. Either one of the outputs from the phase comparators is selected by a selector to be fed to a filter, thereby producing a control voltage for the voltage-controlled oscillator. A high-resolution division is achieved by the fractional division; consequently, disturbance of the oscillation frequency due to a change-over of the selector is suppressed. There is obtained a PLL frequency synthesizer developing a high-speed lock-up and a highly stable oscillation.

Abstract: A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal.

Abstract: An automatic sweep acquisition circuit for a phase-locked-loop using a positive feedback network coupled between a non-inverting input of an operational amplifier and an output of the operational amplifier is provided. The operational amplifier serves as a loop filter for the PLL and has a negative feedback network configured as a lead-lag integrator. The positive feedback network forms a Wein-bridge oscillator that automatically oscillates at a predetermined frequency when phase lock does not exist. A negative feedback path also supplies a portion of the phase shift required to activate the Wein bridge oscillator in order to provide sweep acquisition. When the circuit operates within the bandwidth of the PLL or within the lock-in range of the PLL the positive feedback network provides minimal feedback and thus creates no oscillation or sweeping voltage. The locked-in range of the PLL is increased to the pull-in range of the voltage controlled oscillator used in the phase-locked loop.

Abstract: An AM stereo receiver in which a synchronous in-phase signal is determined comprises a low pass filter circuit for determining an average DC value of the synchronous in-phase signal, a reference voltage supply for providing a reference voltage indicative of a predetermined portion of the DC value of the synchronous in-phase signal occurring during a 100% IF signal level condition, a comparison circuit for comparing the average DC value of the synchronous in-phase signal to the predetermined reference, and an output circuit outputting a signal indicative of an out-of-lock condition when the average DC value of the synchronous in-phase signal falls below the predetermined reference.

Abstract: A phase locked loop (PLL) is disclosed, which produces a source clock signal which has a frequency twice that of a reference clock signal fed from the outside and is in synchronism with a reference clock signal. A timer counts pulses of a reference clock signal in order to measure time corresponding to the lock-in time of the PLL and delivers a count completion signal when the value of counting reaches a predetermined value. A start controller is in control of a clock buffer so that, after a count completion signal is delivered, the clock buffer starts feeding a source clock signal to a load circuit as an internal clock signal, in synchronism with a reference clock signal. A stop controller is also in control of the clock buffer so that, when a clock stop request signal becomes asserted, the clock buffer stops feeding an internal clock signal, in synchronism with a reference clock signal.

Abstract: A synchronous AM detector and processor requiring a reduced number of external components and fewer integrated circuit pins comprises an audio processor having a first filter operation controlled by a control voltage and an AM stereo decoder including a lock detector and a phase locked loop having a second filter operation controlled by the control voltage. A single control node is coupled to the audio processor and the phase locked loop, the control node providing the control voltage for the audio processor and the phase locked loop. The voltage at the control node is biased normally high, capable of being pulled low by the audio processing circuit and capable of being pulled low by the lock detector. An RC circuit decays the rise time of the control voltage at the control node after the control voltage has been pulled low. Circuitry is added to control the first filter operation of the audio processing circuitry responsive to the control voltage at the control node.

Abstract: An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.

Abstract: A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal.

Abstract: A low noise frequency synthesizer 10 that uses uses frequency dividers 13, 15, at least one of which(divider 15) is incrementable and decrementable in half integer steps, and analog gain compensation in a phase/frequency detector 14 to achieve lower noise, lower spurious levels and faster switching speed than traditional methods of frequency synthesis. The key features of the present invention are its half integer dividers 13, 15 and the ability to adjust the phase detector gain to compensate the loop for varying divide numbers. The synthesizer 10 comprises two dividers 13, 15 that provide two reference frequency signals that are a function of an input signal and an output signal of the synthesizer 10. A voltage controlled oscillator (VCO) 18 provides the output signal (f.sub.O) of the frequency synthesizer 10. A phase/frequency detector 14 compares the reference frequency signals and provides a phase error output signal that drives the VCO 18.

Abstract: A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1, . . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n<m. A first down counter (F1, F2) counts consecutive output DOWN signals in the absence of an output UP signal. A second up counter (F3, F4) counts consecutive output UP signals in the absence of an output DOWN signal.

Abstract: A circuit (10) for providing recovery of a phase locked loop circuit when lock has been lost has been provided. The circuit includes a lock indicator circuit (24) for detecting when the phase locked loop circuit has lost lock on an input reference signal. When such loss has occurred, an override circuit (28) is rendered operative to decrease the voltage appearing at the input of a VCO within the phase locked loop thereby slowing down the frequency of the VCO and allowing the phase locked loop circuit to recover lock. Further, a logic circuit (30) detects when the voltage appearing at the input of the VCO has fallen below a predetermined threshold voltage and renders the override circuit non-operative.

Abstract: This invention aims at providing a PLL synthesizer circuit that can shorten lock-up time while sufficiently securing a time constant of a low-pass filter, and has a structure wherein a phase comparator 3 outputs output signals .phi.R and .phi.P on the basis of a reference signal fr output from a reference frequency divider 2, and a comparison signal fp output from a comparison frequency divider 4; the output signals .phi.R and .phi.P are negatively fed back to the comparison frequency divider 4 through a charge pump 5, a low-pass filter 6 and a voltage controlled oscillator 7, and a lock detection circuit 8 outputs a lock signal LD when in a locked state.

Abstract: A method of starting up a system clock that has been generated by a phase-locked loop, and circuitry for accomplishing that method. A low frequency master clock signal is distributed to circuits that generate high frequency local clock signals. These circuits generate the high frequency local clock signals using phase-locked loops in a frequency multiplier configuration. Lock indicator circuitry determines when the phase-locked loop has locked onto the master clock signal and then enables output buffers that then provide the high frequency clock signals to components in the system which need those local clocks.

Abstract: Arrangement including a phase-locked loop whose signal path incorporates a phase detector, a loop filter and a controlled oscillator, a pilot generator for generating a local auxiliary pilot which is applied to the controlled oscillator, and a pilot detector an input of which is coupled to the signal path of the loop and an output of which is coupled to a level detector via a filter member. In order to render an accurate and unambiguous locking indication possible in a simple manner, the frequency of the local auxiliary pilot is located within the passband of the loop and the pilot detector includes a synchronous detector having first and second inputs, the first input of which is coupled to the signal path of the loop between the phase detector and the controlled oscillator and the second input is coupled to the output of the pilot generator, an output of the synchronous detector being coupled to the low-pass filter.

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signals are applied to a lock detection circuit for providing a lock detection signal when the first and second digital input signals have a first logic state at a first transition of a control signal and a second logic state at a second transition of the control signal. One false lock triggers an out-of-phase status indicator. The lock detection signal must return to a valid state for a predetermined number of periods before the phase lock status indicates a valid lock condition. The first and second digital input signals may operate with a non-50% duty cycle.

Abstract: A method for controlling the operating mode of a digital phase-locked loop including a counter controlling incrementing or decrementing of the frequency of a digital clock signal internal to the loop is such that, the input signal of the loop being present intermittently, with random phase from one appearance to the next, the control method comprises, in this order, the following steps:detecting the appearance of the input signal,selecting a relatively low capacity of the counter to enable relatively fast synchronization of the loop,detecting synchronization of the loop,selecting a relatively high capacity of the counter to filter relatively strongly any phase variations of the input signal occurring while it is present, this latter adjustment being retained until the next detection of the appearance of the input signal.

Abstract: A circuit for detecting locking of a digital phase locked loop for locking the phase of a digital outgoing signal as provided by the loop to the phase of a digital incoming signal received by the loop, wherein the phase locked loop includes a detector for detecting the phase difference between the incoming signal and the outgoing signal, and the output signal from the phase difference detector has transitions of a first type in coincidence with transitions of a given type in the outgoing signal, and transitions of a second type in coincidence with transitions of a given type in the incoming signal, the circuit including locking detection means for detecting locking, the locking detection means themselves including means for sampling the output signal from the phase detector by those transitions in the outgoing signal that are of type opposite to the given type, means for storing groups of consecutive samples, comprising not less than three consecutive samples, and means for detecting the instant at which, for

Abstract: A phase lock loop monitors a first digital signal and generates a second digital signal operating substantially at frequency and in-phase with the first digital signal. The first and second digital signal are applied to a lock detection circuit for generating a first digital output signal having a first logic state from a mutually exclusive combination of the first and second digital signals. The first logic state of the first digital output signal is compared with a time slot window formed by a control signal for generating a true lock detection signal when the first logic state of the first digital output signal occurs within the time slot window and a false lock detection signal when the first logic state of the first digital output signal occurs outside the time slot window.

Abstract: Biomedical information is directly digitally telemetered from the patient through a frequency modulated transmitter to a remote receiver and computer station. A phase-lock-loop circuit in the digital transmitter compensates for DC data bias by averaging and generating a scaled measure of the DC content of the digital data fed into the phase-lock-loop circuit. The average signal is then provided as a control signal to a first voltage controlled crystal oscillator, the output of which is then used as a reference frequency for the phase-lock-loop circuit. Frequency modulation of the digital data is provided by coupling the digital data directly into the voltage control input of the voltage controlled oscillator which generates the output frequency. Further control of the phase-lock-loop circuit in the transmitter is achieved by prepositioning the operating frequency of the voltage controlled oscillator by means of a microcontroller.

Abstract: The present invention is a constant current source whose magnitude is proportional to capacitor values, reference voltage and input frequency. A frequency divider provides a plurality of signals to one of a plurality of capacitor switches located within a charge generator. The outputs of the capacitor switches are combined to provide a known charge Q.sub.i to an output generator at regular intervals, t.sub.0 =1/F.sub.in. The output generator produces an output current I.sub.out =Q.sub.i /t.sub.0 =C.sub.i *V.sub.bg *F.sub.in, where C.sub.i is a capacitor value, V.sub.bg is a reference voltage, and F.sub.in is the input frequency. A controller provides a control signal to the output generator to limit variations in the output current I.sub.out. The preferred embodiment may be used in conjunction with process invariant circuits in a variety of semiconductor technologies: CMOS, Bipolar, BiCMOS and GAS. In one embodiment, the present invention is used in conjuction with a timer/delay circuit.

Abstract: A phase locked loop circuit may be utilized as a low jitter clock regenerator in order to generate an extremely stable low jitter signal which is to a large extent immune from input phase and frequency noise. The slaving clock generates an output at a fixed phase relationship to a reference input. The clock regenerator is advantageously implemented by a logic gate type phase detector connected to a multi-stage loop filter. The loop filter output is connected to a phase correction circuit whose output is mixed with the loop filter output to provide a control input to a voltage controlled oscillator. The voltage controlled oscillator output may be provided directly, or through a frequency divider, to a feed-back input of the phase detector.

Abstract: A Loss of Lock Detector and Re-lock Control function using digital techniques to detect a programmable difference in frequencies over a programmable range. Once Loss of Lock is detected, the Re-lock sequence is initiated and PLLIS, PLLMS & PLLGS are stepped through a programmable sequence. The invention detects the frequency difference by counting down two counters and evaluating the value left in one when the other reaches terminal count using a programmable tolerance of frequency differences before Loss of Lock is declared. The complexity and cost of implementation of the invention is reduced by multiple use of a single down counter. Other features of the invention are disclosed.

Abstract: A dual loop phase locked circuit is disclosed in which a first loop includes a phase detector, a filter, and a VCO; as a second loop includes a sweep voltage generator, a compensation circuit, and the filter of the first loop. Due to the compensation circuit, the VCO accurately tracks a signal from the sweep voltage generator, even though the filter has an electrical parameter that drifts with time and/or age and/or component selection.

Abstract: A phase-locked loop demodulator comprises a mixer and a loop filter between an input and an output. A voltage-controlled oscillator is connected between its output and an input of the mixer. The demodulator further comprises a lock-on detector circuit whose output signal is adapted to increase the static loop gain after lock-on by modifying the characteristics of the filter.

Abstract: In a second PLL circuit 200, a phase comparator 13 compares the phase of a clock B' from a frequency divider 11 with the phase of a clock A' from a first PLL circuit 100 to transmit a comparison result to low pass filters X and Y in a filter circuit 14. A phase shift detector 12 detects a phase shift between the clocks A' and B' to output a detection signal E corresponding to the phase shift. A selector 15 selectively outputs an output of either the low pass filter X or Y in response to the detection signal E to input it to a VCXO 10. When the phase shift between the clocks A' and B' exceeds a predetermined value, the low pass filter Y having a high cut-off frequency is selected, whereby the second PLL circuit 200 responds rapidly, and the clock B' follows the clock A' quickly.

Abstract: A PLL synthesizer circuit includes a reference frequency generator for generating a reference frequency signal and a reference clock signal, a phase comparator for comparing a phase of the reference frequency signal with an output signal and for outputting a phase difference signal having a pulse form, and a voltage-controlled oscillation device for generating the output signal having a frequency dependent on the phase difference signal. The PLL synthesizer circuit also includes a phase lock detecting circuit for determining whether or not the phase difference signal has a pulse width in which the reference clock signal successively changes n times (n is numeral equal to or greater than 2) and for outputting a phase lock detection signal representing that the PLL synthesizer circuit is in a phase-locked state when it is determined that the reference clock signal does not successively change n times in the pulse width of the phase difference signal.

Abstract: A out-of-lock detector is described which provides a first series of pulses that are compared to a data stream of pulses. Second and third series of pulses are also created by the present invention. These lead and lag pulses are provided to represent particular logical relationships between the data stream and a clock signal. The sequential relationship between the lead pulses and the lag pulses are compared to determine whether or not the clock pulses and the data pulses are in a phase lock condition or, alternatively, are in an out-of-lock condition. A sequence comparator provides a logically low output pulse if an out-of-lock event is detected. A counter compares the number of out-of-lock events which occur in a predetermined period of time to a preset and programmable value. If an out-of-lock condition is detected, some external means for providing corrective action can then be implemented to bring the phase locked loop into a condition where it can again achieve a locked state.

Abstract: An improved NRZ clock and data recovery system lends itself to integration, includes a NRZ phase detector, an NRZ frequency detector and a lock detector, and provides automatic centering of the clock edge within the bit interval in a manner that is independent of analog delays and process and temperature variations. NRZ data is applied to one side of an exclusive-OR gate and a twice delayed version of the NRZ data is applied to the other side. The output of the XOR gate, a "blivet" signal, is applied to a NRZ phase detector comprising two AND gates, one of which has as its other input a recovered clock signal output of a VCO and the other of which has as its other input an inverted version of the recovered clock signal. The "up" and "down" outputs of the AND gates indicate which direction a frequency control signal should change the VCO frequency. A data holding flip-flop whose input is a once delayed version of the NRZ data is clocked with the recovered clock signal.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.

Abstract: A bandpass filter is used, which closely matches the characteristics of a closed phase lock loop (PLL) so as to provide an acquisition detector output in a PLL being swept. This detector is not activated by noise generated in the loop due to data or other perturbations. This filter includes a differentiator to exacerbate the filtered output and thus, more clearly define the condition being detected. The phase lock acquisition sweep is disabled when the detector output exceeds a predetermined absolute value. The detection scheme works equally well in approaching the lock frequency from above or below actual lock and a latch circuit ensures that the sweep approach always alternates to compensate for an erratic phase detector in the PLL.

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked.

Abstract: A phase lock detector circuit for detecting the lock state of a phase locked loop (PLL) such that it is known when a synthesized clock has achieved a stable phase relationship with its reference clock signal. The PLL includes an input for receiving the reference signal, a digital phase detector, a voltage controlled oscillator, and a frequency divider. The phase lock detector of the present invention includes a loss of lock detector (LOLD) connected to the frequency divider, the phase detector and the input. The LOLD detects the occurrence of a selected phase difference between the reference signal and an output of the frequency divider for a selected number of cycles. Also included is a gain of lock detector (GOLD) connected to the frequency divider and the input. The GOLD detects the occurrence of the reference signal within a selected phase difference of an output of the frequency divider for a second selected number of cycles.

Abstract: An adaptive oscillator control system for use in television receivers or monitors includes a phase locked loop together with a static phase error correction system which responds to long term error signals of significant magnitude within the phase locked loop. An oscillator range control includes a processor establishing a plurality of oscillator frequency ranges identified by oscillator range code numbers. First and second frequency approximations are provided using the oscillator range code number. A confidence circuit examines the consistency of oscillator frequency maintenance within the appropriate frequency range and upon establishing the desired confidence level enables the phase locked loop to provide synchronization. Thereafter, a lock detector responds to the occurrence of frequency and phase lock by the phase lock loop to enable the static phase error corrector and deactivate the oscillator range control system.

Abstract: A synthesizer including a voltage-controlled oscillator, a phase-frequency comparator, a variable-rank frequency divider, a command device to control the oscillation frequency of the voltage-controlled oscillator on a frequency which is a multiple of the frequency of the reference signal as a function of the rank of division of the variable-rank frequency divider. The phase-frequency comparator circuit sends a first series and a second series of pulses as a function of the phase advance or delay respectively of the signals applied to its first and second inputs, to charge or discharge an integration capacitor and provide a signal commanding the advance or delay of the frequency and phase of the oscillator as a function of the voltage developed at the terminals of the capacitor.

Abstract: A lock detector circuit (60) for demodulators of UQPSK signals I and Q has signal processing circuits for forming the signals:A=6I.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4 ;B=4(I.sup.2 -Q.sup.2).A switch (19) is provided for coupling either signal A or signal B to the output (20) of the detector circuit, depending on the value of the signal ratio Q/I. In an alternative embodiment, a summing circuit adds signal A and signal B, and directs the sum to the detector output (20). The resulting output signal is constant under lock conditions, and oscillates when the demodulator is unlocked. This output signal is directed through a comparator (49) to the sweep circuit (43) controlling demodulator VCO (42), and causes the demodulator to remain in the locked condition. The lock detector circuit is effective for any value of Q/I, and utilizes only three analog multiplier circuits.

Abstract: A phase locked loop (PLL) frequency synthesizer capable of switching the output frequency thereof at high speed. The frequency synthesizer has a second phase/frequency comparator and a second variable frequency divider in addition to a first phase/frequency comparator which is included in a PLL. The synthesizer switches over the time constant of a loop filter by the output of the second phase/frequency comparator, i.e., independently of the PLL which is responsive to the output of the first phase/frequency comparator. As a result, the time constant of the loop filter is switched over at an advanced timing to thereby reduce PLL tuning time.

Abstract: A voltage controlled reference oscillator with a high Q and narrow tunability bandwidth produces an output oscillator frequency which is frequency divided by four alternative constants to produce four different clock frequencies for four different digital video standards, D1 component at 270 MHz, NTSC D2 composite at 143 MHz, PAL D2 composite at 177 MHz, and a proposed new composite video standard that is to operate at a 360 MHz clock rate. Automatic identification of which serial digital video is present is accomplished by having the clock generator produce a clock signal at the frequency required by one of the video formats while a phase lock loop attempts to lock onto the incoming signals at that frequency. If no lock occurs within a predetermined time interval, the clock generator is made to produce a clock signal at the frequency required by a different one of the video formats and the phase lock is attempted again. This is repeated until a lock is attained.

Abstract: A designated burst signal specified in a designated frequency is detected from an all-inclusive signal specified in a plurality of frequencies, by multiplying a frequency of the all-inclusive signal by a multiplying factor so as to produce a multiplied output signal, performing a phase-lock loop operation between the multiplied output signal and an oscillated signal produced for performing the phase-lock loop operation and specified in a multiplied frequency of the designated frequency by the multiplying factor, so as to produce a phase-lock output signal and comparing the multiplied output signal and the phase-lock output signal for producing a detected output signal representing whether the designated burst signal is in the all-inclusive signal.

Abstract: The invention relates to a phase-locked oscillator for communication apparatus and the like, and provides a phase lock detection circuit which can positively perform the phase lock detection. In order to accomplish this object, the output of a loop filter (2) is supplied to a first level detector (5) and also to an amplitude detector (6). The output of the amplitude detector (6) is supplied to a second level detector (7). A switching means (8) performs the switching operation in accordance with the output of the second level detector (7) to select an output from the first level detector (5) or a LOW level, and the selected one is output as a phase lock detection signal.

Abstract: A phase lock loop for use in gate array applications with fixed transistors geometries maintains a predetermined phase delay between an input signal and an output signal. The phase comparison cycle operates over multiple periods of the input signal for increasing the operating frequency and simplifying timing considerations throughout the phase lock loop. A phase detector circuit detects a predetermined phase difference between the input signal and the output signal and provides a control signal and a clock signal at different transitions of the input signal. An up/down counter provides a count value migrating within a range of values in response to the control signal at the occurrence of the clock signal. The counter value selects a tap point of a delay line having single inverter resolution for delaying the input signal and maintaining the predetermined phase relationship between the input signal and the output signal of the phase lock loop.

Abstract: A method for a phase-locked loop, which circuit includes, in a preferred embodiment, a resistor to unbalance phase detector outputs to an operational amplifier to cause the voltage output of the operational amplifier to sweep and thus cause the frequency output of a voltage controlled oscillator to sweep. Simple circuitry detects correct lock and terminates sweeping; or, if lock is not achieved, causes the output of the operational amplifier to remain at a low level until the operational amplifier is reset and then permits resweep. Very little auxiliary circuitry is required.

Abstract: The present invention comprises a communication system including a number of independently operating equipment modules in which the operations of these modules are referenced to a common external signal and thereby phase synchronized in order to reduce intra-system interference. The system includes a number of phase lock loop type processing circuits one of which is associated with each equipment module for tracking the external reference signal and generating a base reference for use by module with which each processing circuit is associated. The system takes advantage of the inherent capabilities of phase lock loop circuits to provide a base reference for each equipment module which is characterized by a frequency spectrum having a reduced level of spurious signals and noise. The preferred embodiment includes components for automatically switching between internally and externally generated reference signals and for automatically converting an external reference signal to a standard frequency.