Abstract: A high frequency generator including a frequency generator and a multiplier, the multiplier including a diode, which multiplies the output frequency of the frequency generator, and shuts off or reduces an output by suspending or suppressing the multiplying operation through the control of a bias voltage applied to the diode used in the multiplier. The system for cutting off the output by controlling the multiplier is very effective for simplifying the circuit structure and reliably turning off the output.

Abstract: A phase locked loop having a second controllable oscillator connected to mix with the input signal to alter the frequency thereof toward phase lock and a pair of comparators with predetermined upper and lower limits therein connected to the control signal of the phase locked loop and controlling the controllable oscillator whenever the control signal is outside of the predetermined limits.

Abstract: A phase-locked loop circuit comprises an oscillator, a phase comparator which compares the phase of an input signal with the phase of an oscillator signal, a detector which detects when the phase-locked loop circuit is locked within a predetermined frequency range and produces a corresponding lock detecting signal, and a filter circuit including a variable current source which produces a variable current in response to a change of state of the lock detecting signal to control the bandwidth of the filter circuit, a filter element which receives the variable current, a differential amplifier which receives the phase-compared signal, a current mirror circuit which receives the variable current from the variable current source, and a buffer circuit connected to the filter element which supplies an output signal to the oscillator to lock the frequency of the oscillator signal to the frequency of the input signal.

Abstract: An improved PLL frequency synthesizer for producing a signal of frequency f.sub.T -f.sub.IF or f.sub.T +f.sub.IF is provided with a detection-control circuit which detects from the voltage applied to a voltage controlled oscillator (VCO) in the PLL that the VCO frequency reaches an upper or lower limit frequency and upon the detection forces the VCO to fall into the capture range. The improved PLL frequency synthesizer can acquire lock even if it has been thrown out of the capture range.

Abstract: To be able to recover from modes in which the oscillation of the voltage-controlled oscillator (V0) stops, the phase/frequency control circuit includes an RS flip-flop (RS) connected via two AND gates (U3, U3) to the two outputs (A1, A2) of the phase discriminator (P), which provide pulses for raising and lowering, respectively, the frequency of the voltage-controlled oscillator (V0). When the frequency/phase control circuit is out of lock, a pulse is generated with two monostable multivibrators (M1, M2) which passes through a signal selection circuit (S1) associated with the Q output of the RS flip-flop or through a signal selection circuit (S2) associated with the Q output of this flip-flop and controls the constant-current source (Q1) charging the smoothing device (G) or the constant-current source (Q2) discharging this device in such a way that the unwanted mode can be stopped by changing the control voltage of the oscillator (V0).

Abstract: A phase-locked loop comprises a reference source that produces a signal at a fixed frequency that is applied to a phase detector. That signal is compared in the phase detector with a divided quotient signal that is proportional to the output of a voltage-controlled oscillator. Comparison of the phase difference between the two signals creates an output voltage that is taken to an adaptive filter. The adaptive filter is controlled by an external logic circuit that selects a narrow bandwidth when phase lock is detected and a wider bandwidth when the absence of phase lock is detected. The divisor of the divider in the loop is also changed in response to a signal based on the phase difference. The output of the adaptive filter is taken to a summer which adds a modulating signal to form a combined controlled voltage for the VCO.

Abstract: A phase lock circuit including a phase/frequency detector, a plurality of selectable filters, and a plurality of variable frequency signal generators connected in a loop to lock an output signal to an input signal. An out-of-frequency-range condition detector is provided to facilitate automatic selection of an appropriate in-range combination of filter and signal generator to cause lock to occur.

Abstract: Control signals for switching the bandwidth of a filter in a phase locked loop are provided by comparator circuits having time delays at their inputs that vary as a function of the magnitude of changes in the outputs from a phase comparator. These variable time delays permit the comparator circuits to produce an output having a duration of the proper length in order to permit the filter to have a large bandwidth for a long enough time to permit the phase locked loop to become locked.

Abstract: A phase locked loop is frequency modulated by means of a modulation signal pplied to the loop filter thereof. The circuit is designed with two time constants, one of which determines the square wave modulation response thereof and the other the loop settling time. Each of these time constants is chosen to optimize the loop modulation response and the loop settling time.

Abstract: An alarm circuit operatively associated with a phase-locked loop provides an error indication when the phases of the referenced signal and voltage controlled oscillator signal lose synchronization for times less than one millisecond. The alarm circuit includes an amplifier connected to receive the phase detector error signal, and an impedance connected to conduct the phase detector error signal to the amplifier. The impedance and amplifier have a frequency response corresponding to a frequency response of an associated receiver circuit, so that short duration deviations in the reference signal frequency which the receiver circuit cannot track produce an error indication and long duration deviations which can be tracked by the receiver circuit do not produce an error indication.

Abstract: In an FSK demodulator, the output of the phase detector of a phase locked loop (PLL) is capacitively coupled to one input of an FSK voltage comparator, the capacitive coupling blocking d.c. and d.c. being restored at the comparator input by diodes connected between the two comparator inputs. The other input of the comparator is supplied with a reference voltage corresponding to a nominal center frequency of the FSK signals. A buffer amplifier permits rapid charging of the coupling capacitor, which is set to a determined state when there is no phase lock of the PLL. The arrangement facilitates demodulation of narrow-band FSK signals whose center frequency is subject to change.

Abstract: A PLL detection circuit for use in an AM-PM type AM stereo receiver in which unwanted AC signal components included in the output of a phase comparator are suppressed by switching the frequency response characteristic of a loop filter in the PLL detection circuit as locking is reached so that only the DC signal component, corresponding to the phase difference of the input signal and a reference signal, is outputted. A changeover circuit, including a switching circuit composed of a pair of parallel-connected transistors, is connected in parallel with an element of the loop filter, the component value of which affects or is at least partially determinative of the frequency response characteristic of the loop filter. The changeover circuit is activated by a control signal indicative of the locking state of the PLL detection circuit.

Abstract: First and second frequency signals are frequency converted by a frequency converter and the frequency-converted output and the output from a variable frequency oscillating means are phase compared by a digital phase comparator. The phase-compared output controls the variable frequency oscillating means, constituting a first phase lock loop of a wide capture range. The output from the variable frequency oscillating means is frequency converted by the first frequency signal and the converted output and the second frequency signal are phase compared by an analog phase comparator. By the phase-compared output is controlled the variable frequency oscillating means, constituting a second phase lock loop of a narrow capture range but a large loop gain. The output frequency of the variable frequency oscillating means is varied by changing the setting of the frequencies of the first and second frequency signals.

Abstract: An improvement in a phase locked loop comprising a VCO for generating a signal S.sub.VCO of frequency f.sub.VCO, a divider for dividing f.sub.VCO to produce a signal S.sub.N of frequency f.sub.N, a reference signal generator for generating a reference signal S.sub.R of frequency f.sub.R, and with said VCO responsive to a particular value E.sub.c of a variable control signal e.sub.c to cause f.sub.N =f.sub.R for a given value of N, the improvement consisting of a phase/frequency detector for detecting and correcting frequency and phase differences between S.sub.N and S.sub.R to cause f.sub.N =f.sub.R and comprising a three stage left/right shift register responsive to one of signals S.sub.N or S.sub.R to shift binary O's into the first stage thereof in the right direction and responsive to the other of signals S.sub.N or S.sub.R to shift binary 1's into the third stage thereof in the left direction.

Abstract: A phase-locked loop circuit comprising a reference oscillator (1), a reference frequency divider (2) for dividing the output signal of the reference oscillator, a programmable frequency divider (3), a phase comparator (4) for monitoring the difference in phase between the output signal of the two frequency dividers, a lock detector (11) for generating a first signal which is pulse-shaped or rectangular when the above-mentioned difference in phase is generated, and a digital signal maintaining circuit (100) for converting the first signal into a second directed current signal.

Abstract: An improved presettable integrator circuit is disposed in a fast frequency changing phase lock loop for presetting the voltage-controlled oscillator thereof as governed by a preset signal and a pulsed signal generated by a frequency controller. One input of the integrator circuit is coupled to the preset signal, another input is coupled to an integrator control signal, and the output is coupled to the voltage-controlled oscillator for use as a tuning signal thereof. A switch is included in the integrator circuit and is governed in a first state by the pulsed signal to cause the integrator circuit to respond rapidly to an applied preset signal to preset the output signal thereof. In a second state, the switch renders the integrator circuit responsive to an integrator control signal which is selected by a phase lock condition of the loop from either a reference signal or a filtered phase error signal, being coupled to the other input of the integrator circuit.

Abstract: A time constant resistor in a phase lock loop filter is short-circuited by a plurality of diodes which are activated in response to a detection output indicating that the filter output is within a desired locking range.

Abstract: A sidelock avoidance scheme for preventing sidelock in a PSK demodulator's carrier recovery loop contains augmenting sweep control circuitry, including a frequency discriminator and an associated window comparator. The output of the frequency discriminator, which is low pass filtered to remove noise, is applied to the window comparator which compares any differential between the true carrier and the output of a carrier recovery loop to a preset reference threshold representative of a frequency error condition that may approach sidelock. When the output of the frequency discriminator is greater that this preset reference threshold, an augmented frequency control voltage is applied to the voltage control oscillator of the loop to drive the oscillator away from a possible sidelock condition and toward the true carrier. The augmented frequency control voltage may be derived from a frequency sweep generator or from the output of the frequency discriminator, depending upon a selected strapping option.

Abstract: A variable voltage control oscillator can have its output frequency varied over a wide range of frequencies with a high degree of accuracy at each frequency and a rapid tune time is achieved when there is a reference signal source that runs at a constant frequency and is held to a high degree of accuracy and a counter for normalizing the output frequency of the VCO and a coincidence detector which compares the reference frequency to the normalized output frequency and provides an error correcting signal that adjusts the VCO to change the frequency very rapidly without having a frequency overshoot.

Abstract: An out of lock detector for a sample and hold phase locked loop which provides very accurate resolution and can detect that the loop is converging while in the linear range of the phase detector. The circuit is composed of an AC coupled amplifier which receives signals from the phase locked loop sample and hold phase detector and provides a signal to a comparator network. The comparator network is comprised of two amplifiers whose outputs are in a wired AND configuration. The comparator amplifiers are referenced for the degree of lock required such that a voltage from the input amplifier which exceeds either the upper or lower reference voltage will produce a negative going pulse at the wired AND output circuit indicative of an out of lock condition.

Abstract: A phase locked loop synthesizer including a phase locked loop (PLL) having a first characteristic loop bandwidth, for generating a synthesized signal, the PLL including a signal controlled oscillator (SCO) having first and second control inputs for controlling the frequency of the SCO, the first control input receiving a signal from the PLL, and a subsidiary frequency compression loop (FCL) having a second characteristic bandwidth wider than said first characteristic bandwidth, the FCL having an output coupled to the second control input of the SCO whereby said SCO is subject to frequency control by both the PLL and the FCL.

Abstract: A bit synchronizer for digital data signals capable of tracking phase errors of up to .+-.180.degree. without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. The flip-flops cause the input data to be shifted 0.degree. and 180.degree., respectively, with reference to the clock signal. The flip-flops are cross-coupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180.degree. as the phase error traverses the 0.degree. point.

Abstract: An elastic surface wave recursive filter comprising: at least one delay line formed by two elastic surface wave transducers, such line being looped on itself externally by an amplifier, a means for introducing an elastic surface wave into such line, such means being connected to an input of the filter, and a third transducer having the form of a transversal filter, the transducer being coupled to said line and connected to an output of the filter. The transfer function of the filter is the form P(z)/Q(z), the numerator and the denominator being independant.

Abstract: A system for minimizing synchronization errors in a phase-locked loop having a sequential phase detector for determining the phase difference between the output of the VCO of the phase-locked loop and a periodic control signal. Control circuitry is provided so that the control signal is enabled as an input to said sequential phase detector for a relatively short time window which comprises a small fraction of the control signal cycle period beginning just before a control signal is anticipated and the signal is disabled for the remainder of said control signal cycle period. Provision is made for the phase detector to process only the first control signal in any given enable time window. Additional circuitry is provided to disable the control circuitry when the phase locked loop is detected to be out of lock.

Abstract: A loss-of-phase-lock indicator circuit is described which detects an out-limit voltage, whether steady or transitory. A pair of comparators, one for the high limit and the other for the low limit, are inserted in series between the tuning voltage and the sweep feedback amplifier, and are dc-coupled to the peak detector in the failure circuit. Additionally, a "dither" voltage is added in series with the phase detector, which ac voltage is large enough to swing the tuning voltage between limits at the loop amplifier output, but small enough to produce little effect on the output during phase lock.

Abstract: A tuner comprises a local oscillator including a variable capacitance diode. The output signal of the local oscillator is frequency divided by a prescaler and the frequency divided output is applied to a phase locked loop. The phase locked loop is structured such that the phases of the output signal of the prescaler and a reference frequency signal are compared and the signal associated with the phase difference is smoothed by a low pass filter and the smoothed output is applied to the variable capacitance diode as a tuning voltage. The low pass filter includes a smoothing capacitor. A tuning unlocked state is detected when the terminal voltage of the smoothing capacitor is stabilized at the source voltage or is stabilized at 0V.

Abstract: The automatic sweep and acquisition circuit for a phase locked loop includes a first circuit to detect when the error signal into the voltage controlled oscillator of an unlocked phase locked loop drifts to a DC voltage of a predetermined magnitude which represents an out-of-lock condition for the loop and this detected predetermined value is used to start the sweep waveform so as to regain a locked condition. Simultaneously with the start of the sweep waveform a dither tone is introduced into the loop filter which will not be fed back into the loop filter until the loop is locked. This fed back tone is detected and used to turn off or disconnect the sweep voltage and the dither tone.

Abstract: A phase-locked loop circuit, having an oscillator controlled by a voltage related to the phase difference between a reference signal and a loop signal, is stabilized by a crystal oscillator. The voltage controlled oscillator signal is frequency-subtracted from the crystal oscillator signal frequency to provide an input signal to a frequency-arithmetic synthesizer which provides a loop signal to the phase detector for comparison with the coming reference signal. Use of a frequency-adder circuit between the voltage controlled oscillator and the frequency-subtractor, and receiving an addition frequency derived from the frequency-arithmetic synthesizing circuit, is utilized to decrease the loop gain and provide enhanced characteristics.

Abstract: A carrier recovery apparatus for phase modulated waves including phase-locked loops is operable to prevent false locks. The apparatus includes a clock recovery circuit which generates a signal in response to a modulated carrier, a first phase comparator responsive to the modulated carrier and the output of a VCO, a second phase comparator responsive to the first phase comparator and the clock signal, and a control device for superimposing the low frequency component of the output of the second phase comparator on the output of the first phase comparator or a loop filter which controls the VCO.

Abstract: A digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source is in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.

Abstract: The out-of-lock condition of a digital phase locked loop is detected during a plurality of states such that single bit discrepancies, such as a noise pulse, are ignored, and thus the tolerable range of phase detection error is broadened. The present invention is adaptable for use with typical applications of digital phase locked loops, and can be used to control the phase detector of the digital phase locked loop such that error voltages will be introduced into the loop only during selected states.

Abstract: A clock signal generator for providing redundant clock signals includes two clock modules that utilize phase-locked loop oscillators for generating clock and reference signals and for diagnosing malfunctions of the generated clock and reference signals. One clock module is selected as the master, and the other clock module is the slave, being phase and frequency locked to the master. Switching the master between the clock modules may be externally initiated by select signals and also is automatically initiated when malfunctions are detected. The master and slave clock modules are always phase and frequency locked to one another, even if both clock modules are malfunctioning. When both clock modules experience simultaneous malfunctions, the master is selected in accordance with the externally generated select signals. Since the master and slave clock modules are always phase and frequency locked, switching the master is transparent to clock signal utilization circuitry.

Abstract: In a delay-lock one-delta (.+-.1/2 chip) dithered PN code tracking loop, an indication of lock in the PN code tracking loop is provided by delaying the dithered local PN code by a half chip to produce a +0, -1 dithered PN code that is then multiplied with the received PN-spread IF signal to produce a signal proportional to the correlation of this dithered code offset from the received code. The correlation signal is bandpass filtered, amplified with AGC control, and square-law detected to obtain a DC signal proportional to the degree of correlation. The DC signal is multiplied by the dithering control signal to effectively subtract noise voltage from the lock correlation signal which is then compared with a PN lock status signal.

Abstract: In a muting arrangement of a radio receiver using a phase-locked loop frequency synthesizer as a local osicillator, a detector detects an in-lock or out-of-lock state of the phase-locked loop through an output state of a phase comparator included in a feedback loop of the phase-locked loop frequency synthesizer, and a mute gate provided in a signal transmission path of the receiver is operated to mute an audio output when the phase-locked loop is out of lock. An indicator may be provided for visually indicating that the phase-locked loop is in lock.

Abstract: Disclosed is a phase-locked loop which comprises a voltage controlled variable frequency oscillator (1), a phase comparator (2) having a cosine characteristic and receiving a reference oscillation as well as that supplied by the oscillator (1), and a low-pass filter (3) connected between the output of the phase comparator (2) and a frequency control input of the oscillator (1).The transfer function of the low-pass filter (3) is switchable between two characteristics depending on the instantaneous phase difference between the reference oscillation and that supplied by the oscillator. The first low-pass filter transfer function is adapted to the phase-locked operation of the loop, while the second transfer function is adapted for frequency capture.

Abstract: A lock detecting circuit of a phase locked loop, comprising a phase comparator for receiving a reference frequency signal and a signal being compared with the reference frequency signal, a charging/discharging circuit which is charge/discharge controlled responsive to the output of the phase comparator and either of the above described two signals, and a delay flip-flop responsive to the output of the charging/discharging circuit and in synchronism with the signal applied to the charging/discharging circuit for assuming one storing state for providing an output representative of the phase difference between the above described two signals.