Abstract: A frequency synthesizer phase locked loop includes a voltage controlled oscillator (VCO) providing a variable frequency signal, a reference frequency oscillator providing a reference frequency signal, a phase comparison circuit for comparing the phases of the variable frequency and reference frequency signals and providing an output signal to a loop filter, the output of the loop filter providing a frequency control signal to the VCO. The phase comparison circuit includes a digital phase detector providing an output signal on an output line coupled to a charge pump for providing a first output signal to the loop filter; and an analog phase detector including a sample and hold circuit, and a control circuit responsive to the variable and reference frequency signals for providing a signal for sampling to the sample and hold circuit, the sample and hold circuit providing a second output signal to the loop filter.

Abstract: A search oscillator (12) is disclosed for use with a closed-loop system (10) to sense when the system is out of lock and enhance the system's pull-in capabilities. The oscillator includes a loop filter (22) and a sensing circuit (24), composed of a positive limit sensor (26) and negative limit sensor (28). When the system is out of lock, the output V.sub.out of the oscillator slews positive or negative in an effort to restore the system to lock. The positive and negative limit sensors monitor the output and reset it when predetermined thresholds are reached, allowing the search or sweep operation to continue until lock is achieved.

Abstract: A Phase Locked Loop including a monolithic Phase Locked Loop component. The monolithic component has an internal amplifier stage and an internal VCO. An external phase detector compares the phase of a reference signal to the phase of the output of the internal VCO to provide a signal which is a measure of the phase differences. The signal is filtered by an external filter, amplified by the internal amplifier stage and input to the internal VCO.

Abstract: A phase-locked loop system having as input a stable refernce clock signal and outputting a master clock signal. The phase of the stable reference clock signal is compared to that of the pre-scaled master clock signal and the difference represented by an analog error signal which is converted to a digital signal by an A/D converter (116). The digital signal is then transformed into an analog control signal by a D/A converter (120) and applied to a VCO (128) which generates the master clock signal, If the stable reference clock signal has degraded or is lost the A/D converter (116), which receives its sampling clock in part from the stable reference clock signal, stops sampling and thus stops producing digital signals. The last good digital signal is maintained, the last good analog control signal is maintained and thus the master clock signal is maintained.

Abstract: A frequency synthesized, microwave signal generator is disclosed that provides multiple channel frequency selection capability with rapid channel change time and low levels of spurious signals and noise. The generator uses a microwave harmonic phase locked loop to lock a microwave VCO to a programmable harmonic of a VHF reference crystal oscillator to provide coarse frequency control in steps equal to that reference frequency. The phase lock loop includes an offset mixer for injecting an offset signal frequency to achieve fine frequency control. A harmonic detection and counting scheme is used to rapidly sweep the harmonic loop and obtain phase lock at the desired harmonic.

Abstract: A PLL lock indicator circuit for indicating when a phase-lock-loop circuit is in lock includes a gate circuit coupled to the phase/frequency detector of the phase-lock-loop circuit for providing an output logic signal that is responsive to output logic signals from the phase/frequency detector being in a predetermined state. A counter circuit is enabled by the output logic signal of the gate circuit for providing an output logic signal when the counter circuit has reached a predetermined count. A latch circuit is responsive to the output logic signal of the counter circuit for providing a lock signal at an output terminal of the circuit, the lock signal being indicative of when the PLL circuit is in phase lock.

Abstract: A clock signal having a predetermined frequency output from a clock generator and a signal output from a voltage controlled oscillator (VCO) and supplied through a frequency divider are supplied to a phase detector. An output from the phase detector is supplied to a loop filter. The loop filter supplies a voltage in accordance with an output from the phase detector to a first control voltage terminal of the VCO and to a phase lock-in circuit. The phase lock-in circuit supplies a voltage in accordance with an output voltage from the loop filter to a second control voltage terminal of the VCO. In the VCO, the sensitivity of the first control voltage terminal is lower than that of the second control voltage terminal, i.e., a rate of change in ouput frequency with respect to a change in second control voltage is higher than that of the first control voltage. A phase lock detector for detecting whether or not the PLL apparatus is set in a phase-locked state is also connected to the phase lock-in circuit.

Abstract: A carrier lock detector for a quadrature amplitude modulation system includes Exclusive-OR gating circuits for determining when detected signal points occur within first areas centered on signal point positions in a phase plane diagram or second areas between the signal point positions, and for producing corresponding output signals. An integrated difference between these output signals is produced by an integrator and compared with a threshold level to provide a carrier lock detection signal. The arrangement is such that the integrated difference is substantially zero when the carrier is unlocked, so that the threshold level can be set to a low value to enable reliable operation of the detector at low signal-to-noise ratios.

Abstract: A PLL frequency synthesizer IC chip having a sample frequency input terminal, data and address lines and a plurality of different output devices, and a mode control circuit for turning off any selected ones of the different output devices. The mode control circuit comprises a plurality of inputs connected to at least one of the data and address lines for determining different modes of operation, and a plurality of outputs connected to the plurality of different output devices for selecting ones of the plurality of different output devices to allow outputting therefrom and shutting off outputs from all of the remaining different output devices, based on the determined mode of operation.

Abstract: A receiver circuit for data in NRZ1 coding transmitted at high data rates along optical fiber links, wherein in order to overcome problems of phase jitter in the incoming signal, a clock circuit is included comprising a phase locked loop with voltage controlled oscillator for generating a clock signal locked in phase to the incoming data signal, a phase detector for comparing the clock signal with the incoming data signal, a phase frequency detector for comparing the clock signal with a reference clock signal, a multiplexer for switching the phase locked loop to respond either to the output of the phase detector or the phase freqency detector, and a digital counting system for comparing the number of clock pulses generated in a reference period determined by the reference clock, the digital counting system controlling the multiplexer to switch to the output of the phase detector when it is determined that the clock signal is accurately following the reference clock signal.

Abstract: A phase lock recovery apparatus for a phase locked loop circuit having a voltage controlled oscillator. The apparatus includes a detection circuit coupled to the phase locked loop circuit for detecting a phase unlocked state occurred in the phase locked loop circuit and a sweep signal generator responsive to the detection circuit for sweeping the frequency of the voltage controlled oscillator to come within the lock range of the frequency of the input signal when the phase unlocked state is detected.

Abstract: A circuit for detecting a lock of a phase locked loop comprising a phase comparator receiving a first signal and a second signal for generating a phase difference signal, a waveform shaping circuit connected to receive the phase difference signal for generating an output signal when the phase difference signal indicates a phase difference exceeding a predetermined value, and a multi-stage counter having a frequency division function and having a reset input connected to receive the output signal of the waveform shaping circuit. An input control circuit is connected to receive the first signal and an output of the multi-stage counter and has an output connected to an input of the multi-stage counter for allowing the first signal to be applied to the multi-stage counter only when the output of the multi-stage counter is at a predetermined logic level. The output of the counter provides an lock output.

Abstract: A timing recovery apparatus for a burst mode communication receiver. The apparatus provides for optimum sampling and digitizing of received data at a plurality of data rates. In particular, a VCO is phase-locked to a local frequency reference prior to data being received. A reference timing preamble transmitted prior to the data is filtered and fed to the VCO causing it to injection lock such that the VCO becomes phase aligned with the preamble. The VCO is then permitted to "free run" during data transmission and continues to operate at substantially the same frequency. A synchronous divider and multiplexer, responsive to the VCO, allows selection of sampling clocks for the plurality of data rates. The divider is forced to a known state during VCO injection locking, to assure that the sampling clocks have maintained the proper phase for optimal sampling at the corresponding data rate. Further, means is provided to monitor the frequency of the VCO.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: The present invention provides a high frequency lock detecting circuit for generating a signal indicative of a locked or a not locked phase tracking condition in a phase locked loop circuit. The lock detector comprises a plurality of high speed function generators two of which are coupled to the modulated data streams for indicating the phase data streams and a third high speed function generator is coupled to the voltage error signal of the phase locked loop for indicating the absence or presence of a voltage error signal. The analog outputs of the function generators are summed together in a summing circuit and applied to a differential amplifier which removes the complex modulated data products from the output of the function generators and provides a signal which is equal to the absolute value of the data signals applied to the first function generators minus the absolute value of the error signal applied by the third function generator.

Abstract: This disclosure concerns digital correction of oscillator drift by providing phase alignment between two clock signals running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths of a variable delay path formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator. The product of phase comparison controls a digital delay selector to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signals. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal.

Abstract: Apparatus and method for verifying the lock state or lock condition of a phase locked loop that includes a phase detector, a loop filter and a voltage controlled oscillator. The apparatus comprises a second oscillator that provides a signal of predetermined frequency to the loop filter and a second phase detector providing an output signal indicative of phase lock status. According to the method a signal of predetermined frequency is input to the loop filter and to a second phase detector. The presence of signals to the predetermined frequency is detected at the output of the loop phase detector by inputing the output from the loop phase detector to the second phase detector.

Abstract: A frequency synthesizer including an oscillator (1) whose frequency is controlled by a tuning signal (TS), a phase detector (4) and a phase lock loop circuit (5, 6). A tuning indicator (7) has a tolerance on the phase difference between the tuning frequency signal and the reference frequency signal. The phase detector produces a first (PS1) and a second (PS2) phase signal upon leading and lagging, respectively, of the phase between the tuning frequency signal (F.sub.T) and a reference frequency signal (F.sub.R). The tuning indicator includes delay circuits provided at the input of AND-gates in such manner as to cancel the phase signals (PS1) and (PS2) of a duration less than a predetermined duration, and a register producing a confirmed tuning indication signal (IS) only when the phase signals (PS1) and (PS2) indicate stable tuning during at least two consecutive periods of the reference frequency (F.sub.R).

Abstract: A phase lock loop for use in carrier acquisition employing a predetection filter and a loop filter switchable between a constant phase margin and second order characteristic. In the acquisition mode, the constant phase margin characteristic is employed to acquire the carrier and the second order characteristic is thereafter employed to track the carrier. The second order characteristic retains only the pole at the origin and the lowest frequency zero of the constant phase margin characteristic. The filter parameters are selected to minimize the mean square deviation of a phase margin expression which includes contributions from the predetection filter pole and from positive poles generated by the loop's voltage controlled oscillator. The loop filter is further provided with gain coefficients selected to maximize the probability of carrier acquistion at a plurality of frequencies and carrier to noise density ratios.

Abstract: In a phase controlled demodulator, a modulated digital input signal is demodulated into quadrature signals with a carrier recovered by a voltage controlled oscillator. A phase difference between the quadrature signals is detected by a phase detector of Costas loop and applied through a loop filter to the voltage controlled oscillator to control the frequency and phase of the recovered carrier when the frequency deviation between the received and recovered carriers is within a phase control range. When the frequency deviation exceeds the phase control range, the output of the phase detector is a beat of the two carriers and a frequency sweep control voltage is applied to the VCO to search for the missing carrier. The magnitude of the beat is detected and compared with a predetermined threshold value.

Abstract: A structural member having a piezoelectric transmitter film and a piezoelectric receiver film adhered thereto. The transmitter film produces a vibration upon activation by a voltage controlled oscillator which forms part of a phase-lock loop circuit. The vibrations of the structural member generate electric signals on the receiver film, which feed into a phase comparator. The other input of the phase comparator is the output signal of the voltage controlled oscillator. The phase comparator will output a dc signal proportional to the difference in phase between the two signals. When the structural member becomes damped, the phase comparator will go into saturation, thereby producing a voltage which can activate an alarm signal or other device.

Abstract: The present invention is a demodulator for demodulating an unsymmetrical QPSK signal (1), i.e., one in which the amplitudes of the I and Q channels are different, and the I and Q channels have been modulated by signals having differnt bit rates. Analog versions of the I and Q modulating baseband signals are first extracted from the carrier. Each baseband signal is then subjected to a bit-rate-matched low pass filter (23, 13). The channel having the higher bit rate is subjected to a delay (32) to time-align the two baseband signals. The time-aligned filtered signals are then amplified by amplifiers (22, 12) having unequal gains that are preselected to substantially equalize the amplifier (22, 12) outputs. The amplified time-aligned filtered signals are then subjected to a phase error (E) generating means (15, 25, 16, 26, 34). The phase error (E) is passed through a loop integrator (38) and a VCO (30) and back to the baseband signal extracting means to complete a phase lock loop.

Abstract: In a method for compensating for differences in a first clock signal's rate and a second clock signal's rate, transmitting voice samples from a first location synchronized to the first clock signal are received at a second location having a second clock for generating the second clock signal. The first clock signal and the second clock signal are compared to determine when a slip of one cycle has occured and it is determined which of the first and second clock rates is greatest. At the second location, the process includes adding a received voice sample for each predetermined number of slips which occur if the second clock is running too fast relative to the first clock, and discard an additional voice sample for each predetermined number of slips which occur if the second clock is running too slow relative to the first clock.

Abstract: A lock detect circuit (FIG. 3) for use in a synthesiser of the type comprising a phase comparator (5), a reference frequency source (11, 13, 15) a variable frequency oscillator (1), a variable divider (3) and a loop amplifier (7). The circuit includes logic gates (31, 33, . . . 41) to monitor the frequency `up` and frequency `down` error signals (C.sub.U, C.sub.D) produced by the comparator (5) and provides an `in-lock` indication (S) when frequency `up` or frequency `down` signals exclusively are detected in a predetermined period ( .sub.D). Accordingly this circuit may comprise a variable delay (31) an inverter (33) an AND-gate (35) and an OR-gate (39) for generating a comparison signal:f'.sub.E =F.sub.N .multidot.C.sub.D +C.sub.Uwhere f.sub.N is the signal from the inverter time delay pair derived from the divider output. This signal is fed to a series of flip-flops (37) clocked by the frequency down signal.

Abstract: This phase and frequency detector, receiving two logic input signals R and V, comprises a set of 2k+2 memory cells, cascade arranged and linked in twos by 2K+1 control cells, capable especially of transferring the information contained in the changes of state of the signals R and V, from the end memory cells to which they are respectively applied, and by each of the directions respectively, to a memory cell MU.sub.n or MD.sub.n (depending on whether the signal R is ahead or delayed with respect to the signal V), this cell then giving square waves the duty factor of which is proportionate to the instantaneous phase shift .DELTA..phi. between the signals R and V, when (2.pi.-1)n<.vertline..DELTA..phi..vertline.<.pi..

Abstract: A PLL comprising a phase comparator circuit for detecting the phase of a pulse signal based upon the input signal and the phase of a pulse signal based upon the output signal, a smoothing filter for smoothing the output of the phase comparator circuit, a loop filter for controlling the oscillation frequency on the basis of the smoothing filter, and a voltage controlled oscillator circuit for sending out the output signal having a frequency corresponding to the voltage based upon the output of the loop filter. Since the smoothing filter is separated from the loop filter, time constants of the smoothing filter and the loop filter can be set independently and with precision. If the time constant of the smoothing filter is chosen to be extremely small, for example, the time constant of the phase-locked loop is defined by the time constant of the loop filter. It is thus possible to define the time constant of the phase-locked loop by only selecting the time constant of the loop filter.

Abstract: For use in a radio synthesizer (110), a digital phase detector (118) indicates the phase error between a reference signal provided by a reference oscillator (117) and an output frequency signal (114) provided by a voltage controlled oscillator (112). The digital phase detector (118) includes four flip/flops (310, 312, 314 and 316) which receive the frequency signals (116 and 120) provided by the oscillators (117 and 112) to generate steering signals (126) which optimally indicate the phase error between the frequency signals (116 and 120) as well as providing optimal (maximum) frequency steering when a frequency difference between the frequency signals (116 and 120) exists. Responsive to the flip/flops, digital logic circuitry (306) is used to provide a non-integrated level-type indication when the frequency signals (116 and 120) are phase locked.

Abstract: The method consists in using a sawtooth signal at the output from a lowpass filter of a phase lock loop, in multiplying it by a low frequency squarewave signal, in integrating the resulting multiplied signal in order to obtain a sweep signal, and in controlling a voltage controlled oscillator of the phase lock loop by means of the sweep signal. The apparatus comprises a multiplier (7) and a low frequency generator (8). It may also include, prior to the multiplier, a hysteresis comparator (5) and a highpass filter (6). The output (S7) of the multiplier (7) is connected to a loop filter (3) in said phase lock loop in order to integrate the multiplied signal.

Abstract: An intelligent phase-locked loop performs adaptive transfer function parameter selection and fault tolerant self-monitoring within the phase error filtering algorithm. The algorithm includes a capture mode, at least one align mode and an operate mode. The capture mode shifts to the align mode if the phase error limit is not exceeded at the end of a first period of time. The align mode switches back to the capture mode if a reverse phase error relation is met during the mode. At the end of the align mode, the algorithm switches to the operate mode if a forward phase error relation is met. The operate mode continues indefinitely. However, a switchback to the align mode is made if an out of lock phase error limit is exceeded for the operate mode. The bandwidths of the transfer function of the loop are adapted for each of the modes so that the capture mode is the broadest bandwidth, the align mode is an intermediate bandwidth and the operate mode is a narrow bandwidth.

Abstract: A voltage controlled oscillator is provided which includes a pair of gain stages constituting a positive feedback path, a pair of buffer stages in cross connection with the gain stages, a pair of loads connected with the corresponding gain stages, each having a parallel connection of an active device resistor and a clamping diode, and a pair of voltage controlled current sources connected with the corresponding gain stages, for supplying constant currents to the gain stages. A timing capacitor is connected with the input sides of both voltage controlled current sources, and is charged or discharged by the constant currents from the current sources.

Abstract: A phase-locked-loop (PLL) circuit comprising a phase comparator, a current-variable charge pump, a voltage-controlled oscillator, a low-pass filter, and frequency dividers. The charge pump drive current is controlled in steps or continuously depending on the operating mode.

Abstract: A phase-lock loop system incorporates a normally "transparent" oscillator used in detecting whether or not the system is in a locked condition. It is essential that the oscillator, a portion of which is serially involved in the phase-lock loop, have a long time constant, so as to minimally affect the closed loop's transfer function during phase-locked conditions. It is desirable, however, that when the phase-lock loop loses lock that the time constants of the transparent oscillator change to much smaller values for quick response of the oscillator and operation at a high frequency for detection purposes and quick extinction when phase-lock is acquired. The detection of oscillation of the transparent oscillator initiates the application of a low speed sweep signal being applied to the voltage controlled oscillator portion of the phase-lock loop to reestablish phase-locked conditions and eventually return of the transparent oscillator to its long time constant values.

Abstract: An embedded circuit is placed in a phase-locked loop having the normal phase detector and voltage-controlled oscillator. The embedded circuit is transparent to phase-locked conditions of the loop and becomes operative in an oscillatory mode only when the loop loses its lock. An oscillatory detector is used to detect the oscillatory condition of the embedded circuit and causes the application of a sweep signal to the voltage-controlled oscillator to reestablish phase-locked conditions in the overall phase-locked apparatus.

Abstract: A BPSK Costas-type PLL circuit in which the circuit is positively prevented from falsely locking on to the input signal and in which the need for a complex lock detector is eliminated. The output levels of both the 0.degree. and 90.degree. sub-loops of the circuit are detected and a difference formed between the detected outputs. When the difference exceeds a predetermined reference level, it is determined that true locking has occurred, whereupon a sweep generator, used in achieving initial lock, is decoupled from the PLL circuit.

Abstract: An adaptive phase locked loop being particularly useful with low frequency input signals, the adaptive phase locked loop including a phase comparison unit (12) for comparing a component of the input signal with the reference signal having an average phase, a polarity detection unit (14) for providing a polarity indication signal dependent upon the polarity of the output signal, and a reference signal unit (13) for providing a reference signal having an average phase to the phase comparison unit (12). In response to the polarity indication signal, the reference signal unit (13) can vary the rate at which the average phase of the reference signal can be changed at either of two rates, with the first rate representing a relatively slow rate and the second rate representing a relatively fast rate.

Abstract: An image signal of the input and/or the output side is (are) multiplied by a shading compensation signal obtained from the output signal of a low-pass filter employed in a PLL circuit or a greating signal multiplying means.

Abstract: A lock detector (12) used in conjunction with a bit synchronizer (14) for determining when a random binary input signal (2) is in lock with a clock (7) generated by the bit synchronizer (14). A window comparator (3, 5; or 23, 25, 27) determines whether the amplitude of the input signal (2) is within or without an amplitude window, and generates a signal (33) as a result of said determination. This signal (33) is sampled at periodic sampling points (X, Y). The set of X sampling points and set of Y sampling points are interleaved and usually separated by half a bit period. The X samples and Y samples are averaged and compared. Means (19) are provided for declaring a lock condition when the X average exceeds the Y average by a preselected threshold (V.sub.REF), which occurs when the X points are positioned near mid-points of data bits (35) and the Y points are positioned near data transitions (39). The circuit (12) will not lock on false sidebands and can operate at very low signal-to-noise ratios.

Abstract: A phase-lock loop system with particular use in radar tracking systems is disclosed. From a number of input signals of varying frequencies such as a carrier frequency and several side band frequencies the system can lock into phase and frequency with the input which has the largest amplitude by sweeping across a predetermined range of frequencies and allowing the phase-lock loop to operate only when a predetermined amplitude is exceeded.

Abstract: A dual conversion variable bandwidth telemetry receiver employs a phase locked loop which controls the second local oscillator to maintain lock on the carrier frequency; the phase locked loop employing a loop filter with a variable time constant integrator, the time constant of which can be varied as a function of receiver bandwidth and the integrator with its associated capacitor and resistor banks being employed in a sweep, i.e. search, oscillator circuit enabled when the carrier signal is lost. A coherent double-balanced mixer is employed to detect carrier lock and if lock is lost but the carrier is still detected, a rapid response anti-sideband circuit in the phase detector of the phase locked loop is employed to suppress the sidebands and greatly increase the probability of relocking on the carrier. A synchronous AM detector employs quadrature IF and reference signals at the same frequency to produce a dc signal when phase lock occurs; the signal falling rapidly upon loss of lock.

Abstract: A digital lock detector for a phase-locked loop accumulates out-of-lock pulses which are derived from a high frequency clock signal. The out-of-lock pulses are gated by an out-of-phase indicator signal and a pulse centered around the phase-locked loop output cycles to reduce the effect of relative phase jitter between the input and output signals of the phase-locked loop. The digital lock detector utilizes two counters in series which are reset independently to provide resistance to fading signal conditions. In addition, the lock detector circuit requires several consecutive long out-of-lock indications before an out-of-lock condition is indicated.

Abstract: A phase locking circuit for effecting pull-in of a phase locked loop to a desired frequency component even in the presence of spurious signals includes a phase locked loop, a scanning circuit and a control circuit. The scanning circuit generates a scanning current to the phase locked loop which activates a voltage controlled oscillator (VCO) therein, the VCO output being phase locked to an input signal by operation of the phase locked loop. The control circuit produces a periodic scanning restart signal causing the scanning circuit to periodically generate a second scanning current independent of the phase lock status of the phase locked loop until a phase lock to the desired frequency component is realized. The second scanning current functions to unlock a VCO output locked to a spurious signal.

Abstract: A tracking phase locked loop circuit in which the frequency of an oscillator portion thereof is varied over a range of frequencies in search of an incoming carrier is disclosed. The varying frequency occurs at two different sweep rates. A faster rate is used until the frequency of the phase locked loop's oscillator nears the frequency of the incoming carrier, and a slower rate is used until the circuit locks onto the carrier. A filter couples between mixer and sweep control circuit portions of the phase locked loop to provide information concerning the difference between oscillator frequency and incoming carrier frequency. The sweep control circuit distinguishes between the carrier and noise and switches rates accordingly.

Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.

Abstract: An all digital circuit which operates with an electronic oscillator of the type that receives an input signal and synchronizes its oscillations to transitions in the input signal, comprises: a pulse-generating circuit 20 coupled to the oscillator for digitally forming periodic pulses in synchronization with selected oscillations of the oscillator; a detecting circuit 30 coupled to receive the pulses and the input signal for digitally detecting whether a transition occurs in the input signal in the absence of a pulse; and a counting circuit 40 coupled to the detecting circuit for digitally counting so long as the detecting circuit fails to detect a transition in the absence of a pulse and for indicating the oscillator is synchronized when the count reaches a predetermined number.

Abstract: A frequency time standard monitoring system includes three highly accurate standards of substantially identical frequency. These three standards are compared in pairs by three monitoring apparatus. Each such apparatus includes a fine window detector for determining the phase relationship between the two applied frequency standard clock signals, and a phase shifter responsive to the fine window detector for shifting the phase of one of the signals until the signals are phase aligned. When this occurs, the fine window detector is disabled and a coarse window detector monitors the two clock signals to ensure that the clocks do not drift beyond tolerable limits. The output signal of the coarse window detector is applied, along with the corresponding signals from the other two monitoring apparatus, to a select logic which determines which standard should be on-line in the event of a fault detection.

Abstract: The output of a phase comparator in the PLL of the data reproduction unit is filtered to remove low frequency components which may be due to record eccentricity. The filtered output is then rectified and integrated, with the level of the integrated signal determining whether the PLL should be operated in a broad or narrow band state.

Abstract: The present invention discloses a phase lock loop circuit which recovers a carrier for demodulating a PSK signal wherein a sweep signal is suspended when a decision signal indicates the phase-locked state. The level of the sweep signal is held and applied to the phase lock loop at the time the circuit becomes phase-locked, thereby an unwanted sweep signal component is no longer generated when the sweep stops. Thus stable phase-locked operation can be realized.

Abstract: An improved adaptive loop filter for modulatable frequency synthesizers containing digital phase comparators is described. The unique adaptive loop filter provides a wide bandwidth during a signal acquisition mode and a narrow bandwidth during a signal tracking mode. The adaptive loop filter includes a current limiter coupled to the error signal from the digital phase comparator for generating a current-limited output signal; a filter coupled by a resistor to the current limiter output signal and including a series-coupled resistor and capacitor for filtering the current limiter output signal to provide a steering line voltage; an amplifier coupled to the junction between the filter resistor and capacitor for generating a feedback signal; a resistor for coupling the feedback signal to the current limiter output signal for substantially reducing the duration of voltage transients; and a reference filter for coupling the steering line voltage to the steering input of a voltage-controlled oscillator.

Abstract: A phase locked loop provides limited phase correction when in lock in order to minimize the effects of noise in the periodic input signal to which the loop is locked. The phase locked loop includes a voltage controlled oscillator (VCO), a timing generation divider, a phase detector, a lock detector and an oscillator control circuit. The phase detector provides an output based upon the phase difference between rising edges of the input signal and a loop synthesized signal which is derived by the divider from an oscillator output signal. A window signal, which begins slightly before and ends slightly after an anticipated rising edge of the input signal, is also derived from the oscillator output signal. The lock detector provides a lock detect signal which indicates whether the loop is in lock. The oscillator control circuit provides an oscillator control voltage based upon the phase detector output signal, the window signal, and the lock detect signal.