Abstract: A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

Abstract: A signal processor is provided for use with a first signal generator and a second signal generator, wherein the first signal generator provides a first signal having a first amplitude and the second signal generator provides a second signal having a second amplitude. The signal processor includes: a threshold component that stores a threshold value; a threshold detection component that generates a sum of the first amplitude and the second amplitude, compares the sum with the threshold value, generates a modification required signal when the sum is greater than the threshold value; a delay component that generates a delay signal; and a delay processor operable to output an output signal based on the sum of a modified first signal and the second signal when the sum is greater than the threshold value.

Abstract: Modified viruses and methods for preparing the modified viruses are provided. Vaccines that contain the viruses are provided. The viruses can be used in methods of treatment of diseases, such as proliferative and inflammatory disorders, including cancer, and as anti-tumor and/or antiangiogenic agents. The viruses also can be used in diagnostic methods.

Abstract: A transmitter comprising a power amplifier, a phase modulator, a switched DC-DC converter, all operating in dual mode, and a controller is disclosed. The power amplifier is arranged to selectively operate either in a first mode or in a second mode, wherein the first mode is a linear mode and the second mode is a non-linear mode in order to save power with least increasing cost in hardware. The transmitter is adapted to operate at different allocated bandwidths, for different radio standards while keeping minimum power consumption governed by the controller. A transceiver, a communication device, a method and a computer program are also disclosed.

Abstract: A phased array includes a number of transmission units with an unequal array of power amplifiers for receiving or transmitting input signals at millimeter wave frequencies. The phase array transmits millimeter waves in air to reconstruct original phase-and amplitude signals by combining the signals from the unequal array of power amplifiers. The unequal array of power amplifiers comprises power amplifiers having a higher peak power than other power amplifiers of the array. The power amplifiers can also have different transmission powers from one another.

Abstract: Modified viruses and methods for preparing the modified viruses are provided. Vaccines that contain the viruses are provided. The viruses can be used in methods of treatment of diseases, such as proliferative and inflammatory disorders, including cancer, and as anti-tumor and/or antiangiogenic agents. The viruses also can be used in diagnostic methods.

Abstract: An RF system using PR-ASK with orthogonal offset is disclosed. In some embodiments, the system includes a PR-ASK signal generator and an orthogonal offset generator. The PR-ASK signal generator can produce a signal representing a sequence of symbols, for example, RFID symbols. The orthogonal offset generator can shift the PR-ASK signal trajectory away from the origin while maintaining the time domain requirements for an RFID signal, such as waveform edge rise and fall times. In some embodiments stored waveforms incorporating the controlled orthogonal offset are used to synthesize a sequence of symbols. The stored waveforms may also include nonlinear and/or linear predistortion to reduce computational complexity. The waveforms can be represented in Cartesian coordinates for use in a direct conversion transmitter or polar coordinates for use in a polar modulation transmitter. An RFID system can also include a receiver to receive incoming RFID signals.

Abstract: An oscillator circuit having a programmable output frequency may include a first delay section having a negative gain and a variable delay that is set by a control signal provided to the first delay section. A second delay section having a negative gain and a fixed delay may be connected in series with the first delay section. The oscillator circuit may include an output comprising the output of the second delay section having a frequency that is dependent on the delay of the first delay section and the delay of second delay section.

Abstract: Apparatus and method for clock and data recovery are disclosed. A reset circuit counts clock cycles between edges of an input signal and resets a signal processing circuit that performs acquisition and tracking of a data stream when the clock cycle count is outside of a range. The signal processing circuit is further configured to perform acquisition and tracking according to a corrected data rate, which can be generated by data rate adjustment through a phase error correcting control loop and/or dithering between two data rates.

Abstract: A carrier leakage correction device includes a non-modulation signal generator that outputs a first non-modulation signal having a first amplitude or a second non-modulation signal having a second amplitude larger than the first amplitude, a quadrature modulator that performs quadrature modulation on the first or second non-modulation signal and converts a first or second quadrature modulation signal into a high-frequency signal, an envelope detector that detects an envelope of the high-frequency signal, a correction value searcher that performs a search for a correction value giving a minimum value of a fluctuation amount of an envelope amplitude of the envelope detected by the envelope detector by changing a candidate for the correction value, and a corrector that adds the correction value obtained through the search of the correction value searcher to the first or second non-modulation signal.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.

Abstract: A periodically resetting integration angle demodulation device and a method using the same is disclosed, which uses a waveform multiplier and a periodically resetting integrator to modulate a continuous-time angle modulation signal into a discrete-time signal. The waveform multiplier multiplies the continuous-time angle modulation signal by a square wave signal whose frequency is integer times a carrier frequency, and then transmits the continuous-time angle modulation signal to a periodically resetting integrated circuit. The periodically resetting integrated circuit performs integration during a carrier period to generate a discrete-time angle modulation output signal. The present invention can greatly reduce the difficulty for designing an optical sensing system in the front end without limiting a modulation depth. Besides, the present invention achieves a small volume, high speed, high sensitivity, high reliability, high performance and high condition-adapting properties.

Abstract: A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

Abstract: An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

Abstract: A communications system includes a target receiver having a passband and configured to receive an intended signal within the passband. The communications system also includes a jammer configured to jam the target receiver from receiving the intended signal. The jammer has at least one antenna, a jammer receiver coupled to the at least one antenna, a jammer transmitter coupled to the at least one antenna, and a controller configured to cooperate with the jammer receiver. The controller is configured to detect the intended signal and to generate an interfering signal comprising a continuous phase modulation (CPM) waveform having a constant envelope so that the interfering signal at least partially overlaps the passband of the target receiver.

Abstract: Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

Abstract: A new coded continuous phase modulation (CPM) scheme is proposed to enhance physical layer performance of the current DVB-RCS standard for a satellite communication system. The proposed CPM scheme uses a phase pulse design and combination of modulation parameters to shape the power spectrum of CPM signal in order to improve resilience to adjacent channel interference (ACI). Additionally, it uses a low complexity binary convolutional codes and S-random bit interleaving. Phase response using the proposed CPM scheme is a weighted average of the conventional rectangular and raised-cosine responses and provides optimum response to minimize frame error rate for a given data rate.

Abstract: A binary bi-phase shift modulator having an input piezoelectric transducer and an output piezoelectric transducer connected in series between a radio frequency input and a radio frequency output. A fixed DC pole voltage having a first polarity is connected to one of the transducers. A DC switched pole voltage is connected to the other transducer which switches between the pole voltage of the first polarity and a pole voltage of the opposite polarity in accordance with a binary data signal. The polarity of the radio frequency input relative to the radio frequency output varies as a function of the polarity of the DC switched pole voltage.

Abstract: A Direct VCO (DCO) modulation apparatus and method that provides a wideband modulated signal output. The wideband response is obtained via signal processing to counteract a high-pass frequency characteristic as seen from the VCO modulation input. That is, low frequency components of data signals are compensated before being applied to a VCO input. The high-pass characteristic in combination with the compensated signal provides a relatively flat, wideband frequency response of the DCO modulator.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals.

Abstract: A drain modulator circuit for operation with a radio frequency (RF) amplifier, includes a pair of AC signal sources each of the AC signal sources having an output at which an AC signal is provided. The drain modulator circuit further includes a pair of tapped delay elements, each of which is configured to receive an AC signal from a respective one of the AC signal sources and a control element coupled to provide one or more control signals to the pair of tapped delay elements such that the tapped delay elements provide a selected instantaneous differential voltage to the RF amplifier.

Abstract: Disclosed is an analog-digital converter which includes a pre-amplifier configured to output a comparison result between a sampled analog input signal and a reference signal and to control a power supply operation in response to a power control signal; a digital signal processor configured to generate a digital signal based on the comparison result; a power controller configured to generate an amplifier operation clock signal for controlling the pre-amplifier; and a counter configured to count the number of falling edges of the amplifier operation clock signal and to detect a power interruption point of time of the pre-amplifier according to the counted falling edge number. The power controller generates the power control signal for interrupting a power to be supplied to the pre-amplifier when the power interruption point of time of the pre-amplifier is detected.

Abstract: A binary bi-phase shift modulator having an input piezoelectric transducer and an output piezoelectric transducer connected in series between a radio frequency input and a radio frequency output. A fixed DC pole voltage having a first polarity is connected to one of the transducers. A DC switched pole voltage is connected to the other transducer which switches between the pole voltage of the first polarity arid a pole voltage of the opposite polarity m accordance with a dinar data signal The polarity of the radio frequency input relative to the radio frequency output varies as a function of the polarity of the DC switched pole voltage.

Abstract: A modulation apparatus comprising a first modulating section that outputs a first modulated signal having a fixed amplitude and a set phase; a second modulating section that outputs a second modulated signal having the fixed amplitude and a set phase; an adding section that outputs the output signal as the sum of the first and second modulated signals; a calculating section that calculates two phases to be set respectively in the first and second modulating sections, based on designated amplitude and phase; an allocating section that allocates, for the first and second modulated signals, the two phases calculated by the calculating section such that the first and second modulated signals are each connected more smoothly; and a setting section that sets the phase allocated for the first modulated signal in the first modulating section and sets the phase allocated for the second modulated signal in the second modulating section.

Abstract: A wideband phase modulator comprises a multiphase generator, a phase selector, and a phase adjuster. The wideband phase modulator is configured to receive an N-bit digital phase-modulating signal comprising a timed sequence of N-bit phase-modulating words, where N is a positive integer representing the bit resolution of the N-bit digital phase-modulating signal. The multiphase generator generates a plurality of coarse carrier phases, all having the same carrier frequency but each offset in phase relative to the other. The M most significant bits of the N-bit phase-modulating words are used to form M-bit phase select words that control the output phase of the phase selector. The phase adjuster performs a precision rotation operation, whereby a selected coarse carrier phase is adjusted so that the phase of the resulting final precision phase-modulated signal more closely aligns with a desired precision phase.

Abstract: Embodiments of digital high-speed bi-phase modulator and method for bi-phase modulation are generally described herein. In some embodiments, the digital high-speed bi-phase modulator comprises a high-speed digital divider, a high-speed digital multiplexer, and matched signal paths provided between the divider and the multiplexer. The high-speed digital divider is configured to receive a carrier signal and generate complementary output signals. The high-speed digital multiplexer is configured to switch between the complementary output signals and generate a bi-phase modulated output at a carrier frequency (fc) modulated with a bi-phase code. The bi-phase code may be provided to control inputs of the multiplexer.

Abstract: A feedback loop is used to determine phase distortion created in a signal by directly extracting the phase distortion information from a feedback signal using original frequency modulation information.

Abstract: A fan speed control circuit includes a first fan, a second fan, a first temperature sensor, a second temperature sensor, a PWM regulator, and a driving module. The first temperature sensor senses a temperature of the first component to generate a first temperature signal. The second temperature sensor senses a temperature of a second component to generate a second temperature signal. The PWM regulator is connected to the first temperature sensor and the second temperature sensor. The PWM regulator generates a first PWM signal according to the first temperature signal and generates a second PWM signal according to the second temperature signal. The driving module is connected to the PWM regulator. The driving module generates a first driving voltage provided to the first fan according to the first PWM signal. The driving module also generates a second driving voltage provided to the second fan according to the second PWM signal.

Abstract: A circuit includes a phase shifter configured to selectively shift a phase of a baseband phase signal in accordance with a zero crossing signal to output a selectively phase-shifted signal, a phase modulator configured to provide a phase modulated carrier signal in accordance with the selectively phase-shifted signal, and an inverter configured to selectively invert the phase modulated carrier signal in accordance with the zero crossing signal.

Abstract: A technique for adjusting a phase relationship among modulation symbols is disclosed. A method embodiment of this technique comprises the steps of applying to a sequence of modulation symbols a phase ramp that continuously increases over the duration of the symbol sequence, and applying a compensation phase to each modulation symbol to introduce a phase offset between two subsequent modulation symbols. The joint application of the phase ramp and the compensation phase can be used to establish a saw tooth-like phase characteristic over the sequence of modulation symbols. In one embodiment, the phase ramp is applied in the context of impressing a frequency shift on the modulation symbols.

Abstract: Polar feedback architecture. A polar modulator, as may be implemented within a transmitter module, of a communication device includes feedback. This feedback involves monitoring of phase information and magnitude/amplitude information of an output signal generated by the polar modulator. The output signal can be a radio frequency (RF) signal such as may be transmitted via a communication channel within a communication system. A baseband processing module processes the monitored phase information and magnitude/amplitude information to perform adjustment of a phase modulator and/or other components within the polar modulator.

Abstract: A method for phase modulation of a carrier signal from a transmitter to a contactless transponder in which data is coded as consecutive symbols, each corresponding to a predefined number of carrier cycles, and in which a symbol time is at least two cycles of the carrier signal includes, at the transmitter, spreading a phase jump of a symbol in relation to a preceding symbol over a first part of the symbol time. The establishment of the phase jump is completed in the first part of the symbol time. The periods of the cycles are constant during a second part of the symbol time.

Abstract: Methods, systems and software are provided for high order signal modulation based on improved signal constellation and bit labeling designs for enhanced performance characteristics, including decreased power consumption. According to the improved signal constellation and bit labeling designs for enhanced performance characteristics, designs for 8-ary, 16-ary, 32-ary and 64-ary signal constellations are provided. According to an 8-ary constellation, improved bit labeling and bit coordinates are provided for a 1+7APSK signal constellation. According to a 16-ary constellation, improved bit labeling and bit coordinates are provided for a 6+10APSK signal constellation. According to three 32-ary constellations, improved bit labeling and bit coordinates are provided for a 16+16APSK signal constellation and two 4+12+16APSK signal constellations.

Abstract: Provided is a Polar modulation apparatus which compensates for output characteristics of a power amplifier. A data generator generates an amplitude component signal and a phase component signal. A phase modulator generates a phase modulated signal obtained by phase modulating the phase component signal. An adder adds an amplitude offset voltage to the amplitude component signal. A power amplifier which includes a first hetero-junction bipolar transistor, amplifies the phase modulated signal by using the amplitude component signal. A monitor unit monitors the power amplifier and outputs a monitor voltage. The control unit calculates the amplitude offset voltage according to the monitor voltage and outputs the calculated amplitude offset voltage to the adder. The monitor unit includes a second hetero-junction bipolar transistor and outputs a collector emitter voltage of the second hetero-junction bipolar transistor as the monitor voltage.

Abstract: A wideband phase modulator comprises a multiphase generator, a phase selector, and a phase adjuster. The wideband phase modulator is configured to receive an N-bit digital phase-modulating signal comprising a timed sequence of N-bit phase-modulating words, where N is a positive integer representing the bit resolution of the N-bit digital phase-modulating signal. The multiphase generator generates a plurality of coarse carrier phases, all having the same carrier frequency but each offset in phase relative to the other. The M most significant bits of the N-bit phase-modulating words are used to form M-bit phase select words that control the output phase of the phase selector. The phase adjuster performs a precision rotation operation, whereby a selected coarse carrier phase is adjusted so that the phase of the resulting final precision phase-modulated signal more closely aligns with a desired precision phase.

Abstract: A phase modulation apparatus and method are provided. The phase modulation apparatus includes a storage to store phase modulation setting values corresponding to various communication modes; a phase modulation setting value selector to select, when a communication mode is changed, phase modulation setting values corresponding to the changed communication mode among the phase modulation setting values stored in the storage; and a phase modulator to modulate a phase of a transmission signal using the phase modulation setting values selected by the phase modulation setting value selector. According to the phase modulation apparatus, since a frequency characteristic of a loop filter in a PLL circuit is changed depending on a transmission mode of a communication apparatus and phase modulation is performed using appropriate bandwidths according to various transmission modes, it is possible to prevent noise characteristics from degrading when a PLL bandwidth changes.

Abstract: A signal modulator includes: a modulating circuit; a first signal trace block arranged to conduct a first in-phase oscillating signal to the modulating circuit, and conduct a first quadrature-phase oscillating signal to the modulating circuit; and a second signal trace block arranged to conduct a second in-phase oscillating signal to the modulating circuit, and conduct a second quadrature-phase oscillating signal to the modulating circuit, and a phase difference caused by the first signal trace block substantially equals a phase difference caused by the second signal trace block.

Abstract: An vector modulator using a time delay and a phase shifter is disclosed, the vector modulator including a time delay (110) varying a phase of an input signal by time-delaying the input signal; a first coupler (120) converting the signal outputted in changed phase through the time delay to an I channel signal and a Q channel signal each having a 90° phase difference and outputting the I/Q channel signals; a first phase shifter (130) varying the phase of the I channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable I channel signal; a second phase shifter (140) varying the Q channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable Q channel signal; and a second coupler (150) coupling phase-variable I/Q channel signals and outputting the coupled signals.

Abstract: Systems, methods, and apparatus are described that provide for low phase-noise, spectrally-pure, and low-jitter signals from electrical oscillators. An aspect of the present disclosure includes utilization of an open-loop feed-forward phase-noise cancellation scheme to cancel phase noise, or jitter, of an electrical oscillator. Phase noise can be measured and then subtracted, with the phase noise measurement and subtraction being performed at a speed faster than phase noise variations of the oscillator. Another aspect of the present disclosure includes use of a feedback scheme for phase noise reduction. A feedback scheme can be used alone or in conjunction with a feed-forward scheme. Related phase-noise cancellation and/or reduction methods are described. Notch filter and RF amplifier circuits are also described.

Abstract: Some aspects of the present disclosure provide for polar modulation techniques that utilize an 180° phase shift module disposed downstream of a VCO-DCO. In some embodiments, this configuration allows a polar modulator to use the VCO-DCO to achieve small phase shifts (e.g., less than or equal to) 90°), while carrying out 180° phase shifts in the 180° phase shift module downstream of the VCO-DCO.

Abstract: A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.

Abstract: The present invention provides a semiconductor device. In the semiconductor device, a signal distributor distributes a high frequency signal generated by an oscillator and inputted to an input part to first and second signals and outputs the same from first and second output parts respectively. A modulator modulates a baseband signal with the first signal and outputs the same therefrom. An offset adjustment unit compares the second signal and the first signal that leaks from the output of the modulator to thereby adjust an offset of the baseband signal. The signal distributor includes a first capacitive element provided between the input part and the first output part, and a second capacitive element provided between the first output part and the second output part. The electrostatic capacitance of the first capacitive element is larger than that of the second capacitive element.

Abstract: A power amplifier that amplifies an RF modulation signal containing an amplitude modulation component and a phase modulation component, including a polar modulator that outputs an amplitude component signal that is the amplitude modulation component of the RF modulation signal, a direct current power supply that outputs a direct current voltage, a pulse modulator that pulse-modulates the amplitude component signal, a pulse amplification circuit that amplifies a pulse modulation signal, a combining circuit that adds a direct current voltage that is outputted from the direct current power supply to an output signal of the pulse amplification circuit, a low pass filter that smoothens an output signal of the combining circuit, and an RF amplifier that not only amplifies the RF modulation signal, but also amplitude-modulates the amplified signal with an output signal of the low pass filter and outputs the resultant signal.

Abstract: A quadrature demodulation circuit includes: first to fourth mixers to receive a modulation signal; a phase shifter to supply to the first and third mixers a first local frequency signal, to supply to the second mixer a second local frequency signal having a designated phase difference relative to the first local frequency signal, and to supply to the fourth mixer a third local frequency signal that is an inverse in phase to the second local frequency signal; a first adder to add a signal output from the first mixer and a signal output from the second mixer and to output a first demodulation signal; and a second adder to add a signal output from the third mixer and a signal output from the fourth mixer and to output a second demodulation signal.

Abstract: A jitter generation apparatus for applying a phase modulation to a PLL is controlled by a control unit so as to output a signal with the desired jitter based on a parameters. When a switching unit is switched to a first state, the control unit controls first and second level control units so that the desired jitter in which an amplitude of a first modulation signal matches the parameter is added to an output signal from a voltage controlled oscillator unit, and passes through a quadrature modulator. When the switching unit is switched to the second state, the control unit controls the first and second level control units so that a quadrature modulation is applied to a local signal, which is input to the quadrature modulator without adding any jitter to an output signal from the voltage controlled oscillator unit, and a quadrature-modulated local signal is output.

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±?/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +? (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract: A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.

Abstract: A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.

Abstract: Disclosed are an angle modulator, a transmission apparatus, and a radio communication apparatus that can compensate phase discontinuity when an operational mode of a voltage controlled oscillator is switched. Angle modulator (100) includes phase difference detection section (150) that detects a difference of phases between an input signal of subtractor (141) and an angle modulated signal, using the result of subtraction by subtractor (141) of frequency locked loop circuit (140); correction control section (160) that generates a control signal for compensating that difference of phases based on that difference of phases; correction section (120) that corrects the phase of the angle modulated signal by adding the control signal to an input signal of angle modulator (100), an input signal of loop filter (142), or an input signal of VCO (143) during a predetermined period after VCO (143) switches the operational mode (from time t3 to time t4).