Abstract: A low loss multiple output switch with integrated distributed attenuation is disclosed. In an exemplary embodiment, an apparatus includes a switchable shunt network having an input terminal and a plurality of network output terminals, the switchable shunt network comprising selectable signal paths that connect the input terminal to the network output terminals. The apparatus also includes selectable shunt impedances connected to the selectable signal paths to adjust parasitic loading on the selectable signal paths.

Abstract: A circuit can include multiple data input ports and data output ports, pickoff tees coupled therebetween, and a resistive network coupled between the pickoff tees. A differential signal generator can be coupled with the resistive network and the pickoff tees. Resistances of the pickoff tees and resistive network can be selected such that impedances looking into the data input ports and data output ports are matched to a desired system impedance.

Abstract: A microwave, power splitter/combiner (20) is formed as part of a multilayer laminate (27, 28, 29, 33, 34) such that two ports (22, 23) are connected by plated vias (31, 32) to conductive pads (29, 30) connected across an isolation resistor (27). Furthermore, a microwave circuit is provided in the form of a multi-layer laminate including a substrate carrying a resistive layer which has been etched to define at least one resistor, a dielectric membrane covering the resistor, a conductive layer defining at least part of an electrical circuit, and said at least one resistor is electrically connected to the conductive layer by vias extending through the dielectric membrane.

Abstract: A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

Abstract: A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines.

Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal and a second node via a first branch transmission line, a first receiving terminal which is a test point configured to detect errors of the circuit topology coupled to the first node via a second branch transmission line, a second and a third receiving terminal respectively coupled to the second node via a third branch transmission line and a fourth branch transmission line, wherein the difference between the length of the second branch transmitting line and that of the third branch transmitting line, and the difference between the length of the third branch transmitting line and that of the fourth branch transmitting line are greater than the product of a transmission speed and a rise time of the signal, and a first resistor is connected in the third branch transmission line.

Abstract: Printed circuit board having a termination of a T-shaped signal line having at least two line ends, one line end being terminated using a terminating resistor against a supply voltage, and the other line end being terminated against the reference potential of the supply voltage.

Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal via a main transmission line, a second node coupled to the first node via a first branch transmission line, a first receiving terminal coupled to the first node via a second branch transmission line, a third node coupled to the second node via a third branch transmission line, and a second receiving terminal coupled to the second node via a fourth branch transmission line. The second branch transmission line is longer than the first transmission line, and a first resistor is connected in the second branch transmission line. The third branch transmission line is longer than the fourth branch transmission line, and a second resistor is connected in the third branch transmission line.

Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal and a second node via a first branch transmission line, a first receiving terminal which is a test point configured to detect errors of the circuit topology coupled to the first node via a second branch transmission line, a second and a third receiving terminal respectively coupled to the second node via a third branch transmission line and a fourth branch transmission line, wherein the difference between the length of the second branch transmitting line and that of the third branch transmitting line, and the difference between the length of the third branch transmitting line and that of the fourth branch transmitting line are greater than the product of a transmission speed and a rise time of the signal, and a first resistor is connected in the third branch transmission line.

Abstract: A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.

Abstract: In some embodiments, a first conducting line, having a characteristic impedance, connects to a digital device while a second conducting line, also having a characteristic impedance, connects to another digital device. An impedance pathway connects the two conducting lines and has an impedance of at least one-third of the first conducting line's characteristic impedance and of at least one-third of the second conducting line's characteristic impedances. Other embodiments are claimed.

Abstract: Resistors may be more accurately tuned by using an external resistor and comparing the value of an internal resistor to the value of the external resistor. The value of the internal resistor may be adjusted to match the value of the external resistor. Any number of on-chip resistors may then be matched and adjusted using the information obtained with respect to the first internal resistor.

Abstract: Improved methods and apparatuses are provided for conducting bi-directional signaling and testing. The outputs of at least two driver circuits are connected to a resistive network. The output signals from the driver circuits are combined through the resistive network to produce a resultant signal that is an attenuated version of at least one of the output signals. The resistive network and the driver circuits are configured such that the resultant signal is provided to an output node of the resistive network but not to an input node of the resistive network. An input/output node of an external circuit is connected to the input node of the resistive network, wherein the external circuit is configured to receive the resultant signal and output an external signal. An input node of a receiver circuit is connected to the output node of the resistive network.

Abstract: Improved methods and apparatuses are provided for conducting bi-directional signaling and testing. The outputs of at least two driver circuits are connected to a resistive network. The output signals from the driver circuits are combined through the resistive network to produce a resultant signal that is an attenuated version of at least one of the output signals. The resistive network and the driver circuits are configured such that the resultant signal is provided to an output node of the resistive network but not to an input node of the resistive network. An input/output node of an external circuit is connected to the input node of the resistive network, wherein the external circuit is configured to receive the resultant signal and output an external signal. An input node of a receiver circuit is connected to the output node of the resistive network.

Abstract: An attenuator includes first resistors that are connected in series to each other at connection nodes and between an input node and a fixed voltage node, voltage output nodes coupled to the input node and the respective connection nodes of the first resistors, switches and corresponding second resistors being respectively connected in series between the connection nodes and voltage output nodes and commonly connected to an output node, and a load capacitance connected between an output node and the fixed voltage node. The phase between input and output signals is independent of the attenuation. A phase difference is added by the second resistor so that the phase shift determined by the voltage dividing ratio of the first resistors selected by closing a switch and by the value of the load capacitance is compensated.

Abstract: A transformer bus coupler, which connects a transceiver to a data bus without impedance discontinuities. The transformer bus coupler maintains the voltage-to-current ratio of signals as they enter and leave the coupler by providing a shunt circuit that attenuates the current of these signals by the same ratio that the series elements of the coupler attenuate the voltage. The result is an avoidance of impedance discontinuities, which would otherwise result in the signal reflections and the loss of signal fidelity experienced by prior art data bus couplers.

Abstract: A electrical transmission line termination device capable of performing various termination requirements including matching the line impedance of wires in a transmission line with load impedances, electrically connecting conductors in a transmission line for maintaining electrical continuity, detecting improper wiring of the various wires in a transmission line, and connecting a cable shielding conductor to a ground wire.

Abstract: A terminator for a transceiver device for transmitting data signals to and receiving data signals from a second transceiver device over a transmission line therebetween. The terminator has a transmitter connected to the transmission line for transmitting data signals to the second transceiver device, a receiver connected to the transmission line for receiving data signals from the second transceiver device, a termination resistor connected to the transmission line for improving the transmission characteristics of the transmission line, and a switch device between the termination resistor and the transmission line. The switch device is closed for a portion of the time when the receiver is receiving data signals from the second transceiver device such that when it is closed the termination resistor is connected to the transmission line, and is open for the remainder to the time such that when it is open the termination resistor is not connected to the transmission line.

Abstract: A very high speed data bus system for communication among the various functional units that may constitute a large computer system. The bus communication medium comprises a number of line pairs on the backplane, and the bus system comprises a bus control unit for arbitrating requests from a plurality of interface units or ports, there being one such port associated with each functional unit. The functional units are densely packed, that is, mounted in immediately adjacent connectors to define a populated section of the backplane in which all connectors have ports coupled thereto, and one or two unpopulated sections of the backplane in which the connectors are empty. In the populated section, the effective characteristic impedance, designated Z.sub.0 ', is lower than the effective characteristic impedance, designated Z.sub.0, in the unpopulated region. A populated end of the transmission line is resistively terminated with a resistance corresponding to Z.sub.

Abstract: A family of improved 2-wire resistance bridges having from 3 to 14 ports, or legs, is provided for use in interconnecting a plurality of stations or devices in a private line circuit. The bridges include a resistance connected in shunt across the common end of each leg in the bridge, which permits the intrinsic port-to-port loss of the bridges to be adjusted to a desired value that essentially equals the difference between standard toll line input and output power levels, while at the same time maintaining the proper terminating impedance for each of the interconnected devices.