Abstract: Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.

Abstract: Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

Abstract: A channel information sending method, a data sending method, and a device are provided, to improve feedback precision of a precoding matrix. These include a receiver that receives a reference signal and a memory, configured to store at least one computer instruction which, when executed by the processor, cause the processor to measure the reference signal from the receiver to obtain first channel information and second channel information and send the first channel information and the second channel information to the second device.

Abstract: A half-bridge electronic device comprises a high level switch and a low level switch in series that are connected at a central point, and a first and a second synchronization system: • the first system comprising a first detection circuit configured to interpret a variation, following a falling edge, of the voltage (Vm) at the central point, and the first system being configured to generate a first synchronization signal (ATON-LS) for activating the low level switch; • the second system comprising a second detection circuit configured to interpret a variation, following a rising edge, of the voltage (Vm) at the central point, and the second system being configured to generate a second synchronization signal (ATON-HS) for activating the high level switch.

Abstract: Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

Abstract: Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

Abstract: Systems and methods for transmitting data using various Modulation on Zeros schemes are described. In many embodiments, a communication system is utilized that includes a transmitter having a modulator that modulates a plurality of information bits to encode the bits in the zeros of the z-transform of a discrete-time baseband signal. In addition, the communication system includes a receiver having a decoder configured to decode a plurality of bits of information from the samples of a received signal by: determining a plurality of zeros of a z-transform of a received discrete-time baseband signal based upon samples from a received continuous-time signal, identifying zeros that encode the plurality of information bits, and outputting a plurality of decoded information bits based upon the identified zeros.

Abstract: A filter having an impulse response including a first partial impulse response and a second partial impulse response includes a supplementary filter having a supplementary impulse response. A first filter has the first partial impulse response using an output of the supplementary filter as an input and a second filter has the second partial impulse response using an output of the supplementary filter as an input.

Abstract: Reconfigurable Chirp Fourier Transform (CFT) based continuous convolution apparatus(es) and method(s) that are effectively used, for example, in interference cancellation applications.

Abstract: Disclosed herein is an echo cancellation and echo channel estimation system that can relay transmit signals without interference with echo signals by canceling the undesired echo signals received by a relay. The echo cancellation and echo channel estimation system is designed to relay signals between a transmitter and a receiver through a relay using multiple antennas. The echo cancellation and echo channel estimation system includes a receive antenna, a preprocessing vector generation module, an echo cancellation module, and a transmit array antenna. The receive antenna receives a transmit signal from the transmitter and an echo signal via an echo channel. The preprocessing vector generation module generates a preprocessing vector and applies the preprocessing vector, the transmit signal and the echo signal, received from the receive antenna, to the echo cancellation module.

Abstract: An electromagnetic field strength reducing device includes a high-frequency wave eliminator that eliminates a high frequency component from an electrical signal input from a signal source. An electrical signal line is disposed between the high-frequency wave eliminator and the electrical member so as to convey the electrical signal with the high frequency component eliminated to an electrical member. The device also includes a resonant-frequency regulator connected between the electrical signal line and ground to cause the electrical signal line to be resonant at a frequency used for radio communication. The electromagnetic field strength reducing device may be employed in a portable electronic device with a HAC standard radio frequency communication compliance requirement, and use a corresponding method to eliminate the high frequency component.

Abstract: An enhanced quality band-pass filter is disclosed. The filter includes a Q-enhancement core for improving the quality of the filter performance. The system also includes a calibration circuit that monitors the oscillation of the Q-enhancement core and makes adjustments to the Q-enhancement core setting until the filter is not oscillating. By coupling the Q-enhancement core with a robust calibration scheme, the disclosed system maintains a higher quality filter.

Abstract: A method and device for filtering electromagnetic interference generated by the antenna of a transmitter on a sensor sensitive to electromagnetic waves, characterized in that it includes: vi. elements suitable for sampling the signal received by the sensor, vii. elements for count down the elapsed time, called the detection time, after the sampled signal has exceeded a threshold value, the signal, before exceeding the threshold value, being in a range of standard values, viii. elements for comparing in real time the detection time with a threshold time value, ix. elements suitable for providing a diagnosis of electromagnetic interference to be filtered if the sampled signal reverts to a standard value after a detection time of less than the threshold time value, and a diagnosis of an uninterfered sampled signal if this is not the case, x. elements for generating an output signal from the sensor eliminating the diagnosed electromagnetic interference.

Abstract: In an equalizing filter circuit having an input terminal 101, an output terminal 102, delay devices 104 connected in multi-stage to the input terminal 101, and a plurality of weighting circuits 105 which are branched from and connected to the plurality of delay devices to thereby combine respective output signals of the weighting circuits, gain adjustment of the weighting circuits is performed to determine a coefficient of the equalizing filter circuit without depending on a load connected to the output terminal. Thus, an amount of compensation for a distorted waveform may be enhanced. To this end, an impedance converting circuit 108 is connected between at least one weighting circuit and the output terminal.

Abstract: A full range phase shifter circuit includes a power divider, a hybrid coupler, a differential phase shifter, a power combiner and switched attenuators. The power divider, hybrid coupler, differential phase shifter and power combiner comprise lumped elements and can be integrated in semiconductor processes, decreasing the circuit size of the full range phase shifter.

Abstract: A filter arrangement comprises a switching element coupled to a filter input, wherein the switching element is controllable by a reference clock signal. The filter arrangement further comprises an input storage element, an output storage element, and a first and a second auxiliary storage element. The first and the second auxiliary storage element can each be connected in parallel to the input storage element or to the output storage element depending on a switching signal. The output storage element is coupled to a filter output. The filter arrangement can be used as a loop filter in an analog-to-digital converter, wherein the output signal of the filter arrangement is quantized to provide an output word. Respective feedback signals can be generated from the output word and be provided to the storage elements.

Abstract: Input data segments of received symbols are continuously stored in a decision feedback equalizer buffer at a symbol rate S. Output data sections of received symbols are supplied from the decision feedback equalizer buffer at an output rate of nS such that void times separate the output data sections, and n>1. The received symbols supplied by the decision feedback equalizer buffer are equalized in a decision feedback equalizer to provide equalized symbols; and the equalized symbols are decoded by a decoder to provide decoded symbols. Adjustments for the decision feedback equalizer are calculated during the void times such that the adjustments are calculated based on both the received symbols supplied by the decision feedback equalizer buffer and the decoded symbols. The adjustments are applied to the decision feedback equalizer.

Abstract: System and methods for modifying an electrical parameter of an electrical component are described. The system includes an electrical component disposed on a circuit board and a dielectric material. The electrical component has an electrical parameter that is sensitive to a dielectric constant of a substance proximate to the electrical component. The dielectric material is attached to the circuit board proximate to the electrical component and modifies the electrical parameter of the electrical component.

Abstract: A vector space comprising all of the filter coefficients (heq, opt) for different interfering signals (w(n)) is provided, based on an acquired impulse response (hchan). A linear vector sub-space (popt) comprising all of the optimal filter coefficients (heq, opt) for different interfering signals (w(n)) is established from said vector space using a vector space optimization method. The filter coefficients (heq, opt) are established from the vector sub-space according to the current interfering signal (w(n)) being detected, during ongoing data transmission and at the maximum transmission speed.

Abstract: Method and system for a programmable analog tapped delay line filter are disclosed. One embodiment of the present invention is a programmable analog tapped delay line filter comprising an input line, an output line, and one or more gaincells or taps coupled between the input line and the output line. The input and output lines each comprises a cascade of one or more differential delay cells, and each of the one or more gaincells or taps corresponds to a tap weight or coefficient. Furthermore, the input and output lines are terminated in impedances and the filter produces one or more outputs.

Abstract: This invention provides a method for initializing the filter coefficients of a hybrid frequency-time domain adaptive equalizer device implementing frequency domain (FD) filter equalization in a forward path and a time domain (TD) filter equalization in a feedback path, with each filter unit having a plurality of adaptable filter taps.

Abstract: A programmable driver/equalizer with an alterable FIR enables the equalization of serial links or other transmission systems to adapt to a variety of transmission media and impairments specifically, intersymbol interference (ISI). Current mode differential drive circuits are coupled to a transmission media via a Finite Impulse Response (FIR) filter operating in the Z transform mode. The filter transfer function is of the general form of H(Z)=AB0+AB1Z−1+AB2Z2Z−2+ABnZ−N. The driver circuit is coupled to A and B coefficient setting circuits for the filter. The driver circuit also includes A coefficient level driver compensation and B coefficient level driver compensation to reduce the self-induced ISI from the driver while the filter coefficients are activated. The driver includes logic to further reduce ISI by switching off high capacitance paths when the filter coefficients are inactive.

Abstract: A programmable high frequency (HF) bandpass filter is disclosed. The programmable filter has a tunable bandwidth and center frequency over a large range of the radio frequency (RF) and intermediate frequency (IF) spectrum. The programmable filter incorporates micro-electro-mechanical switches (MEMS), Acoustic Charge Transport (ACT) devices, or a combination thereof, to provide tunability of the bandpass filter response characteristics.

Abstract: A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by "RAKE method" the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Abstract: A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by "RAKE method" the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Abstract: The charge coupled device (CCD) charge detection system includes a first CCD register having N non-destructive charge readouts where N is an integer greater than one, and N second CCD registers coupled to the N non-destructive charge readouts where each of the N second CCD registers is coupled to a corresponding one of the N non-destructive charge readouts.

Abstract: A digital high-pass filter derived from a digital low-pass filter of conventional design. The digital low-pass filter periodically calculates respective low-pass filter output values. Corresponding high-pass filter output values are then calculated by subtracting the low-pass filter output values from input samples provided by digitizing an input signal. The high-pass filter output values are then used to generate samples which are applied to a digital-to-analog converter for outputting a high-pass filtered replica of the input signal. The digital high-pass filter compensates for sudden, relatively large changes in the input signal by comparing the low-pass filter output value to the input sample and, in the event that there is a large discrepancy therebetween, setting the low-pass filter output value to the input sample before calculating the high-pass filter output value.

Abstract: A multi-layered printed circuit board is provided.

Abstract: A complementary acoustic charge transport circuit element comprises first and second buried channels. Each of the channels is comprised of a piezoelectric semiconductor and each channel has a source through which charge is injected and a drain through which charge is extracted. A transducer propagates an acoustic wave through each channel and the propagated waves transport the charge between the sources and the drains. A source and/or a drain of one channel is connected in parallel with the corresponding souce and/or drain of the other channel. The waves are complementary at the interconnected ones of the sources and/or the drains.

Abstract: An acoustic charge transport device comprises a substrate with a layer disposed thereon; a channel disposed within the layer for providing a propagation path for a surface acoustic wave; a contact operably connected and disposed at one end of the channel for injecting an electronic signal into the channel; a transducer disposed at the one end of the channel for generating and propagating the surface acoustic wave through the channel; a plurality of sensing electrodes operably associated with the channel and disposed along the propagation path of the surface acoustic wave for non-destructively sensing the electronic signal; and a plurality of active buffer circuits each having an input operably connected to respective sensing electrode and an output operably connected to an output circuit.

Abstract: A CCD filter according to the present invention can provide good comb-shaped characteristics with no adjustments, and can be produced at low cost. The input section 15 of a first CCD 11 is constructed so that it can linearly reduce transferred charges when an input voltage increases. The input section 17 of a second CCD 12 is constructed so that it can linearly increase transferred charges when the input voltage increases. The transferred charges of the first and second CCDs 11 and 12 are added to each other by means of charge adder section 13, and the addition result is output from an output section 14.

Abstract: A sampling device operating as a buffer between a first data signal and a relatively slow processing device accepts the input signal and stores samples of it on a SAW traveling past an input electrode. A blocking potential is applied to a set of electrodes to store a set of charge packets with the SAW device. Packets are consecutively released at a slower rate accommodated to the needs of the next processing unit in line, to read out the sampled signal at a modified rate for intentional distortion of the input signal, for slowing the output stored signal rate, or for time reversal of the signal.

Abstract: A high speed analog to digital converter system employs a set of ACT devices in parallel to buffer a high speed data sampling rate to the processing rate of the analog to digital converters employed. Vernier control of phase between individual devices is maintained by controlling the speed of propagation of the SAW wave by illumination of the substrate in response to a phase comparison between the SAW and a reference signal.

Abstract: A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A heterostructure acoustic charge transport (HACT) device having a number of signal tap electrodes has revealed unexpected insensitivity to electrode spacing and unexpected sensitivity to electrode width. Spacing of one SAW wavelength between consecutive electrodes and an electrode width of .lambda./20 are preferred.

Abstract: A delay device comprises a semi-conductor chip having acoustic charge transport channel disposed therein; a contact operably connected to and disposed at one end of the channel for injecting an electronic signal into the channel; a transducer for generating a single frequency, large amplitude acoustic surface wave through the channel for thereby transporting the electronic signal through the channel; a plurality of electrodes operably associated with the channel and disposed along the propagation path of the surface acoustic wave for non-destructively sensing the electronic signal; switches monolithically disposed on the chip and operably connected to the electrodes for preselecting any one of the electrodes, thereby extracting a delayed replica of the signal from the channel; and an output circuit for processing the extracted signal for generating an output.

Abstract: An acoustic charge transport device (ACT) alters the intersection of an associated surface acoustic wave (SAW) electric potential with the static depletion potential and the input contact potential to correct the timing variations inherent in conventional ACT devices. The ACT device incorporates a pair of correcting electrodes secured to the ACT channel on either side of an input electrode. The electrodes vary the depth of the electric potential of the SAW which ensures sampling of the input signals at consistent times.

Abstract: A new structure for electro-magnetic signal filters is described. The structure of the invention incorporates ideal time lag elements having delay values selected to match an arbitrarily selected set of frequencies matched to a desired frequency response and connected in a cascade array by second filter elements which null the frequency filtered by the preceding array, the output of which is summed to provide a composite output with the desired frequency response. The resultant filters are easily implemented in conventional hardware and the techniques may be applied to a broad range of the electro-magnetic spectrum by the choice of appropriate components.

Abstract: An acoustic charge transport (ACT) device is easily constructed to provide for variable carrier frequency operation or, alternatively, for variable time delays. Variable carrier frequency operation in an ACT device is achieved by incorporating a two dimensional dispersive transducer array which has an interdigitated finger arrangement. This array has a graded periodicity or finger spacing that varies along the length of the array and also has the fingers placed at a 45 degree angle with respect to the length of the array. Because of the varying spacing of the electrode fingers, different spatial regions in the piezoelectric substrate are preferentially excited reflecting the presence of specific frequency components in an applied input signal. A variable time delay is similarly achieved in an ACT device by incorporating a two dimensional interdigital transducer array having fingers with a graded periodicity.

Abstract: A compact low pass/high pass filter phase shifter including a semiconductor switch having a control electrode and first and second load electrodes; a first inductance connected in series with one load electrode and second inductance connected in series with the other load electrode; a third inductance connected in parallel with one load electrode to ground and a fourth inductance connected in parallel with the other load electrode to ground; a capacitance connected in series between the control electrode and ground; and means for applying a control signal to the control electrode for switching the semiconductor switch between a first state in which it operates as a low pass filter and a second state in which it operates as a high pass filter to introduce a phase shift in a propagated signal.

Abstract: The invention relates to a method of implementing programmable tuned filters, in particular for telegraph signal receivers, and also to tuned filters obtained by the method. A resonator (16) organized around a multipath filter and controlled by a first clock signal is associated with a comb filter (17) organized around a delay line (21) and controlled by a second clock signal, in order to constitute a tuned filter which is programmed by the clock signals. The invention is applicable to making programmable tuned filters and banks of such filters, in particular for remote protection equipment in grids for transporting electrical power.

Abstract: An image processing apparatus is provided which is capable of real time image processing, especially filtering, without generating a delay in a frame memory. A cascade filtering circuit filters digital video signals obtained by digitally converting analog video signals to obtain a time sequential digital pixel data stream for the filtering operation based on a pattern of predetermined constants of a p-rows, q-columns. The cascade filtering circuit uses p basic filter circuits (100) cascade-connected with each other. Each basic filter circuit carries out the filtering for one-row and q columns of pixel data. Each basic filter circuit (100) includes delay circuits (40, 41, 42), multipliers (20, 21, 22), and adders (30, 31, 32).

Abstract: A magnetic article surveillance system utilizing microcomputer control and unique time domain and frequency domain information gathering channels whose information is processed by the microcomputer via preselected time domain and frequency domain criteria.

Abstract: The invention relates to a charge-coupled device, in which the channel is provided with two or more separation regions for obtaining a desired charge subdivision, for example, for a transversal filter. Due to asymmetry in the potential distribution between the outer subchannels and the central subchannels, an inaccuracy occurs in the charge distribution, which according to the invention is eliminated for the major part by locally providing the separation channels bounding the outer subchannels with an interruption.

Abstract: A semiconductor CCD focal plane array convolver is taught which permits performing convolution functions on the focal plane array chip. An X-Y array of photosensitive pixels is disposed in a semiconductive substrate, with a CCD roadway comprising a pattern of rows and columns of conductive gates upon the substrate surrounding and defining the X-Y array of pixels. The number of gates for each pixel are selected to permit charge from the pixel to be collected in either a first charge holding packet for a positive convolution coefficient, or in a second paired charge holding packet for a negative convolution coefficient. The convolution function is performed by applying gate signals which move the charge packets around the CCD roadway. A differencing electrometer is provided at the periphery of the CCD roadway to permit differencing the accumulated charge stored in the paired charge holding packets to difference the positive and negative convolution coefficients to provide a convolution output signal.

Abstract: A CCD output signal generating circuit includes a CCD type charge transfer device for transferring and outputting signal charges in response to the drive signal of a frequency f.sub.c, an output circuit for generating an output signal corresponding to the output signal charges from the CCD type charge transfer device, and a correlated double sampling circuit. The CDD output signal generating circuit also has a low-pass filter circuit which, having a cut-off frequency set within a range of 2.5f.sub.c to 4f.sub.c, and being connected between the output circuit and the correlated double sampling circuit, acts to filter an output signal from the output circuit before supplying the signal to the correlated double sampling circuit.

Abstract: A technique for compensating for charge transfer inefficiency in charge coupled devices. A convolver output is summed concurrently with a previous convolver output delayed by a sample period and weighted by a selected coefficient related to the charge transfer inefficiency.

Abstract: A CCD delay line may be tapped using a floating-diffusion electrometer at the tap. Charge sensing is made non-destructive by not resetting the floating diffusion to a reset drain after charge sensing. The resulting charge integration on the floating diffusion causes a smearing of the samples described by successive charge packets. The smearing is in the baseband frequencies of the sample frequency spectrum, but does not appreciably affect the subspectra surrounding harmonics of the delay line clock rate. Consequently, smear-free response to the floating-gate electrometer output signals can be obtained by synchronously detecting them at a harmonic of the delay line clock rate. Using floating-diffusion electrometers, rather than floating-gate electrometers, to sense charge packet amplitudes at taps along a CCD delay line lowers the noise in the output response of output-weighted, charge-coupled-devive transversal fiters.

Abstract: An analog transversal filter includes a charge transfer delay line, including a plurality of cells for storing electrical charge, and a multiphase clock to transfer electrical charge from cell to cell through the delay line. A plurality of injection electrodes are connected to predetermined ones of the cells to sample an electrical signal, weight the signal sample a predetermined amount, and inject a charge packet representing the weighted signal sample into the cell. An output electrode collects and sums the charge packets transferred through the delay line. In another embodiment, the filter includes a plurality of charge transfer delay lines, with a plurality of cells for storing electrical charge in each delay line.