Abstract: A transversal filter is provided which includes a delay circuit comprising a plurality of cascaded saturating circuit elements. The delay circuit has a series of taps from which signals with varying delays are obtained. The obtained signals are combined to form filtered signal(s).

Abstract: A charge coupled device has a meandering charge path formed by a channel stop of unique shape. The channel stop is of interdigitated pattern, and the gate electrodes form a straight strip. The channel stop pattern and an asymmetric depletion layer formed within the channel cause the transfer of the charge through the channel via the meandering charge path. A transversal filter and imaging device are readily provided by extracting the signal from one or both sides of the channel.

Abstract: Programmable signal processing apparatus for multiplying a sampled analog signal by a multiple bit digital word coefficient. All signal processing operations are accomplished by the splitting, routing and combining of charge packets formed in a charge domain device.

Abstract: The invention relates to a charged-coupled transversal filter of the parallel-in series-out (PISO) type having a buried channel of one conductivity type and zones diffused into the channel of the other conductivity type, which zones constitute the clock electrodes. The inputs also comprise a zone of the one conductivity type which is provided in the associated zone of the second conductivity type. The weighting factors are formed by selecting the sizes of these zones, which constitute the emitters of bipolar transistors, whose bases are constituted by the clock electrodes and whose collectors are constituted by the channel. The signal to be filtered is introduced by first converting the signal into a current and by then distributing the latter over the various emitters. Stages having positive and negative weighting factors can be readily combined to form a CCD.

Abstract: A programmable charge coupled device transversal filter 5 includes a charge coupled device register 10 for receiving and delaying incoming analog signals, a series of floating gate charge detectors 15, a corresponding number of sets of binary scaled capacitors C.sub.0, . . . 2C.sub.0 . . . 2.sup.n C.sub.0, an output circuit including a positive and negative bus coupled to a differential amplifier, and mask or otherwise definable electrical connections for connecting selected ones of the scaled sets of capacitors between the floating gate 15 corresponding to that set and one of the positive and negative buses 22 and 23.

Abstract: A circuit for detecting a Frequency Modulated (FM) signal is provided. An amplitude limited FM signal is propated through a delay circuit comprising a plurality of cascaded saturating inverters. A Boolean logic "Exclusive Or" (XOR) operation is performed between the FM signal before entering the delay circuit and after exiting the delay circuit.

Abstract: Methods and apparatus for high speed signal sampling and recording utilizing mutual repulsion field-induced splitting of charge carriers in a charge transfer channel.

Abstract: A charge transfer filter utilizing a charge transfer accumulator structure for exponential smoothing of sampled data signals is described. The charge transfer accumulator structure performs charge equilibration at high speed thereby enabling an exponential decay impulse response to be obtained at high speed.

Abstract: In this transverse charge transfer filter having N MOS capacitors arranged on the same semiconductor substrate and provided with electrodes, the electrode of every other MOS capacitor has its ends covered by the ends of the electrodes of two adjacent MOS capacitors, the N MOS capacitors being arranged in n rows and the charge transfer direction in two adjacent rows being opposite, which makes it possible to compensate for the effects of the displacements of the masks used for manufacturing the transverse charge transfer filters.

Abstract: A Gaussian convolution is produced in a CCD imager or shift register by a method involving a special clocking sequence. The principle of operation, analagous to the process of diffusion, involves the deliberate intermixing of adjacent charge packets in a controlled way. Amounts of charge are exchanged between adjacent pixels a number of times, the result approximating the convolution of the image with a Gaussian function whose width is dependent upon the number of mixing cycles.

Abstract: A digital filter imparting a desired tone color to the tone signal is realized by the combination of a digital pole filter and a digital zero filter capable of controlling a pole and a zero in an amplitude-frequency characteristic respectively. The amplitude-frequency characteristic of the digital filter is a composite of the respective characteristics of the pole filter and the zero filter. A "peak" portion and a "valley" portion in this composite characteristic can be set independently by the pole control of the pole filter and the zero control of the zero filter, whereby the desired tone color characteristic can be readily realized. Further, the digital filter may comprise a plurality of digital filters having respective different constructions and a connection switching circuit capable of setting arbitrarily connection between these filters. The filter characteristic as a whole can be diversely altered by changing the connection, whereby diverse tone color characteristics can be realized with ease.

Abstract: A bias charge (commonly known as a "fat zero") is divided into a plurality, n, of equal parts. These equal parts are differentially delayed, and the results appearing parallel in time are summed to generate a bias charge with reduced noise. The reduced-noise bias charge is then applied to an input of a charge transfer device -- e.g., one of the charge coupled device (CCD) analog shift registers used in a CCD imager to transport charge packets descriptive of picture elements in an imager.

Abstract: A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system functionH(z)=b.sub.o .multidot.(1+b.sub.1 z(1+b.sub.2 .multidot.z( . . . 1+b.sub.n .multidot.z)))describing the filtered signal, where z is the delay which the signal values respectively experience when traversing a stage of the shift register. The filter is employed as an analog filter in communication technology.

Abstract: A charge-transfer-device (CTD) transversal filter which makes use of tap-weight-adjustment circuitry for removing effects of charge-transfer inefficiency (CTI) and fixed-pattern noise (FPN). The tap weights are adjusted by measuring the response of the CTD-transversal filter to an isolated pulse input and to a zero-frequency input. The results of the measurements and reference-filter coefficients are used by the tap-weight-adjustment circuitry in order to set tap weights for the CTD-transversal filter. The tap-weight-adjustment circuitry allows the frequency response of the CTD transversal filter to be accurately tailored even though the CTD filter suffers imperfections due to CTI and FPN.

Abstract: A charge coupled device has a meandering charge path formed by a channel stop of unique shape. The channel stop is of interdigitated pattern, and the gate electrodes form a straight strip. The channel stop pattern and an asymmetric depletion layer formed within the channel cause the transfer of the charge through the channel via the meandering charge path. A transversal filter and imaging device are readily provided by extracting the signal from one or both sides of the channel.

Abstract: A circuit for obtaining an output from a CCD type signal processing circuit should operate satisfactorily in a high frequency band covering, for instance, video signals. For this purpose, the floating gate electrode of the CCD is connected to a first potential point through first and second capacitors. The connecting point of the floating gate electrode in the series circuit is connected to a second potential level through a first control switch which is driven by a reset clock pulse, and the connecting point of the first and second capacitors is connected to a third potential level through a second control switch which is driven by a reset clock pulse, so that the output is provided at the connecting point of the capacitors.

Abstract: A transversal adaptive filter with a tap weight computer having a respective first and second input responsively coupled to a respective output and input of the filter, and including spectrum shaping means. The spectrum shaping means comprises matched or like preselected bandpass means interposed at the inputs of the tap weight computer.

Abstract: Methods and apparatus for recording pulse signal information utilizing threshold integrating devices in which a pulse shaped signal is applied to a plurality of threshold integrating devices each having a predetermined quantity of electric charge carriers stored therein, in which the threshold integrating devices are responsive to application of electric potentials above a predetermined threshold potential value for altering the amount of charge stored in the charge storage zone of the threshold integrating devices. By providing a plurality of threshold integrating devices each having a different threshold potential, significant signal information may be obtained by passive application of the pulsed signal to a plurality of the devices. This signal information may be obtained by determining the amount of charge in the charge storage zones of the respective threshold integrating devices subsequent to application of the pulsed signal thereto.

Abstract: A video signal processor, particularly for use in identifying light source position, in which a video signal stream from an image detector is processed directly on a substrate using charge coupled device stored image transfer technology. The video signal is clocked through an array of charge coupled devices in a plurality of closely adjacent channels on a single semiconductor chip in such manner that the pattern of signals stored on the chip in the region of the adjacent channels corresponds to the light source image on the detector. Video signal processing is shared between the chip and external electronics to provide an indication of signal strength (acquisition), signal background, and signal centroiding in both horizontal and vertical axes. Much of the signal processing is provided directly on the chip by segmenting and intercoupling the charge coupled device electrodes in a predetermined pattern.

Abstract: Disclosed is a programmable frequency converting filter having a plurality of selectable operating modes, and having frequency passbands of a unique width for each of the operating modes. The programmable frequency converting filter is comprised of a charge transfer device transversal filter, a non-sampling filter, and a frequency band selector. The transversal filter has an output lead coupled to an input of the non-sampling filter, and has clock leads coupled to the output of the frequency band selector. The frequency band selector has control leads for receiving logic signals which together select operating modes from the plurality of modes. The frequency band selector generates, on the clock leads, clocking signals having a unique frequency for each mode of the plurality.

Abstract: A charge transfer device (CTD) delay line comb filter for separating the frequency interleaved luminance and chrominance components of a composite video signal is provided wherein signal charges representative of the composite video signal within first and second delay lines are effectively subtracted one from the other by alternately passing them under a common, periodically clamped, normally floating sense electrode. This eliminates the need for a phase inverter, which causes imperfect separation due to having a non-zero time delay and not having exactly unity gain.

Abstract: Charge subtraction for charge packets of two charge transfer device (CTD) delay lines is provided by alternately transferring them under a periodically clamped, normally floating sense gate, common to both delay lines. Adjacent the sense electrode, each delay line includes preceding and succeeding transfer gates, the gates of each line clocked by one of first and second oppositely phased clock signals for alternately transferring the charge packets under the sense gate. A reset switch clamps the sense gate to a reference voltage whenever its input voltage exceeds a first threshold level and unclamps the gate whenever its input voltage falls below the first threshold level.

Abstract: A superconducting transversal filter circuit for processing signals in the 2-20 GHz range consisting of a miniature transmission line of niobium or similar material, a series of taps for coupling the input and output, and cryogenic refrigerator.

Abstract: In a device for current-reading of a quantity of electric charges, the control circuit for the first and second MOS transistors receives a constant potential and comprises:a third transistor, the drain and gate of which are connected to the constant potential and the source of which is connected to the drain and to the gate of the second transistor;a second capacitor connected through one of its terminals to the nodal point of the second and the third transistor.The device is employed for reading quantities of charges which arrive under the storage electrodes of charge-transfer filters.

Abstract: A sound effect imparting device for an electronic musical instrument is capable of imparting a plurality of desired sound effect such as vibrato and reverberation effects to a digital musical tone generated from the electronic musical instrument. The device comprises a digital arithmetic operation unit constructed with a combination of adders, multipliers, delay circuits, etc., a control unit, a parameter memory and a read-out unit.By control data and parameter data which are respectively read out from the control unit and the parameter memory by means of the read-out unit, switching of the operation mode of the digital arithmetic operation unit is controlled in a time-sharing manner, whereby a plurality of sound effects are imparted to a musical tone through digital arithmetic operations.

Abstract: The output filters of the modulator and of the demodulator, the input filter of the demodulator are transverse charge-transfer filter whose weighting coefficients are determined by the result of the division between the numerator and the denominator of the recursive charge-transfer filter having the desired passband characteristic, the number of the coefficients which the transverse filter comprises being limited.

Abstract: A common channel charge transfer recursive filter has two delay lines, in which charges are transferred in opposite directions. Exchange bridges having two sections extend between the lines. Each section feeds a predetermined charge fraction to one of the two downstream electrodes with charges flowing from the two upstream electrodes. The charge transfer is controlled by a three-phase system (.phi.1, .phi.2, .phi.3). Split memory electrodes and the exchange bridges are connected to the first phase (.phi.1) bus. A transfer electrode is in each gap between an exchange bridge and a memory electrode and is connected to the second phase (.phi.2) bus. A second transfer electrode is connected to the third phase (.phi.3) bus. The gap between a memory electrode and the next exchange bridge is occupied by a transfer electrode connected to the second phase (.phi.2) bus and by a transfer electrode connected to the third phase (.phi.3) bus.

Abstract: A switched capacitor all pass filter which provides an output signal having substantially linear magnitude and phase response is provided. A transfer function which represents an all pass filter and which has a predetermined phase response is provided. A filter/phase equalizer structure having integrating operational amplifiers and various feedback portions which represent the transfer function is also provided.

Abstract: CTD transversal filter, for time delayed forming of a given input signal being weighted and subsequently summed for producing a filter characteristic, with weighting coefficients optionally having a negative and a positive sign, including a separate input stage for forming each desired weighting coefficient for obtaining a desired filter characteristic, the input signal being scanned by a common scanning frequency for all input stages, being converted to a charge packet proportional to its voltage and being time delayed in the input stages, the input stages for forming the negative weighting coefficients being formed in an inverting manner as compared to the input stages for forming the positive weighting coefficients, gate electrodes of the input stages, the areas of the gate electrodes of the input stages under which the charge packets are formed proportional to the input voltage, corresponding to the ratio of the absolute values of the required weighting coefficients, and a common output stage in which the

Abstract: The effects of crosstalk of an FM carrier from a first signal channel into a second signal channel are reduced by a variable-frequency notch filter coupled in the second channel. The frequency of the notch in the transmission characteristic of the filter is controlled to track the frequency of the FM carrier. Signals in the second channel at the frequency of the FM carrier are attenuated, and therefore the crosstalk signal is attenuated and its effects reduced.

Abstract: Output signals are derived from two portions of a CCD imager. The first output signal is derived from a drain diffusion in the form of a signal current and applied to an amplifier with poor high frequency S/N due to needed high frequency peaking. The second output signal is derived from a floating diffusion (or floating gate) through an on-chip MOSFET amplifier which has a poor low frequency S/N due to 1/f noise. The first and second output signals are filtered through complementary LPF and HPF respectively and then combined together.

Abstract: A low cost automatic equalizer is provided for reducing the amplitude and phase distortion produced by close-in echos. The color subcarrier burst, or some other portion of the video signal having predetermined amplitude and phase characteristic prior to transmission, is gated into detection circuitry. A regenerated color subcarrier, phase shifted to be in phase with the subcarrier burst, is used to detect the in-phase and quadrature components of the subcarrier burst, which are indicative of amplitude and phase distortion. The signals indicative of amplitude and phase distortion are applied to a three tap delay line equalizer, where the amplitude and polarity of the first and third tapped signals are controlled in unison to reduce amplitude distortion, and where the amplitude of the first and third tapped signals is controlled in unison, but the polarity of the first and third tapped signals is controlled oppositely to reduce phase distortion.

Abstract: The invention relates to an electrical filter circuit operated with a definite sampling and clock frequency f.sub.T, such filter being made up of CTD elements, and having at least one bipolar or quadripolar resonator in the form of a self-contained conductor loop (for example, C.sub.1, C.sub.2) with unidirectional transmission behavior.Differences in the transfer capacitances of such circuits are reduced, as far as possible, in order to thereby simplify integrated manufacture as far as possible, by positioning the frequency band to be filtered out at a frequency position which lies above half the clock frequency (f.sub.T /2), or in the range from f.sub.T /2 through 3f.sub.T /2.

Abstract: In the present invention, image processing is performed at speeds comparable to those achieved in parallel processing without requiring substantially more area on the substrate than that required in serial processing. In this invention, for an N.times.N processing kernel, N rows of image memory are processed in parallel through a plurality of N floating gate arrays of dimension N.times.N, N-1 of the data rows from the memory being recirculated through the N floating gate structures before being discarded. Each of the floating gate structures is offset from the adjacent floating gate structure by one row so that the data from memory need be recirculated only once.

Abstract: An adaptive analog processor incorporating a analog shift register having a plurality of taps, multipliers at each tap for multiplying the tap value times a weight value, a first adder for summing the output of the multipliers, a second adder for subtracting the output of the adder from a second analog signal, means for incrementing the weights in response to the magnitude and polarity of the error signal and the polarity of the data signal. The invention overcomes the problem of building monolithic multitap adaptive filters utilizing the clipped-data least mean square error algorithm.

Abstract: CCD devices, such as imagers, typically have built in MOSFET output amplifiers with a large amount of l/f noise. Instead of using the baseband video output signal, the present invention uses video signal sidebands centered about the C-register clock frequency or a harmonic thereof for improved S/N. An integrator and a gate are used to still further improve the S/N.

Abstract: A filter circuit comprising a charge transfer device of the type which includes first and second sets of charge storage devices, such as capacitors, the first and second sets of charge storage devices being supplied with first and second clock signals, respectively, and further including first and second sets of switches which are actuated in response to the first and second clock signals, respectively, each switch being operable, when actuated, to transfer charge between a charge storage device in one set and a charge storage device in the other set, thereby transferring a charge through succeeding switches to be temporarily stored in succeeding charge storage devices. A semiconductor element, such as a transistor, is actuated in response either to the first or to the second clock signals for transferring the charge stored in a first predetermined charge storage device to a second predetermined charge storage device.

Abstract: A dynamically variable electronic delay line for real time ultrasonic imaging systems is disclosed which controllably phases the signals associated with an array of electromechanical transducer elements and thereby enables selective scanning and dynamic focusing of a target. A controllable variable electronic time delay apparatus is coupled to each of the electromechanical transducer elements of the array having separate write-in and read-out addressing capabilities. The signals associated with a respective ultrasonic transducer element are fed in at selected write-in addresses and subsequently read-out and extracted after an initial time delay interval. The write-in and read-out address pointers of the memory system are continuously sequenced during operation of the device and the time delay interval is a function of the difference between the addresses and the clock rate.

Abstract: CCD methods and devices for recording transient data signals, in which charge is transferred under the influence of transmission line fields at sampling sites disposed along a charge transfer channel.

Abstract: A filter circuit for electrical waves including at least one line which supplies electrical input waves and at least one line for withdrawing output electrical waves and in which the frequency dependent transmission characteristic is determined by coupled line loops each of which is in the form of a line ring and wherein coupling between the line loops is unidirectional and the individual line loops are designed so that they have unidirectional transmission characteristics.

Abstract: By dividing the split gate electrode into four sections, in which two non-adjacent sections are solely clock sections and the other two sections are "plus" and "minus" sections, respectively, and in which the sum of the lengths of the first two sections, in serial order, is substantially equal to the sum of the last two sections, in serial order, only a single mask must be changed, in the fabrication of transversal filters that exhibit a small common mode, in order to change the particular filter characteristic of a fabricated filter.

Abstract: A bucket brigaded device is provided which includes first and second clocking signal generators for generating a first set and a second set of clocking signals respectively, a plurality of successive capacitors for sequentially holding charge level representing an input signal, and a plurality of transistors for controlling the transfer of charge levels from one capacitor to another. Each of the transistors is connected between adjacent capacitors.The bucket brigaded device further comprises a first clocking signal driver for supplying one of the first set of clocking signals to each capacitor, and a second clocking signal driver for supplying one of the second set of clocking signals to each transistor.

Abstract: A filter utilizing charge transfer devices for providing recursive transfer functions is described. The filter includes a circular charge transfer shift register having an even number N of stages, greater than two, a first charge transfer shift register, and a second charge transfer shift register. A first input stage is unidirectionally coupled to the first stage of the first shift register and is also bidirectionally coupled to the N.sup.th stage of the circular shift register. A second input stage is unidirectionally coupled to the first stage of the second shift register and is also bidirectionally coupled to the (N/2).sup.th stage of the circular shift register. A first input sequence of packets of charge representing positive weight components of a signal is applied to the first input stage and a second input sequence of packets of charge representing negative weight components of the signal is applied to the second input stage. All three shift registers are clocked at the same frequency.

Abstract: A CCD comb filter includes long and short CCD delay lines connected to receive a common input signal and is arranged to combine output signals of the long and short CCD delay lines. In order to realize a CCD comb filter very close to an optimum comb filter the product of the number of stages of the long CCD delay line and the transfer inefficiency of each stage thereof is set substantially equal to the product of the number of stages of the short CCD delay line and the transfer inefficiency of each stage thereof. In order that the transfer inefficiency of the short CCD delay line may be made greater to satisfy the above-mentioned requirement, transfer electrodes of the short CCD delay line are designed such that their length as viewed in charge transfer direction is made larger than the length of transfer electrodes of the long CCD delay line.

Abstract: A digital adaptive finite impulse response (AFIR) filter having a large number of coefficients is composed of two or more separate filter units. The first filter unit computes response samples h.sub.o -H.sub.n+1 in response to input signal samples to provide a partial estimated response during each sampling period. After the signal samples are fully processed by the first unit, they are transferred to a second filter unit which produces response samples h.sub.n+2 -h.sub.p+1 in response thereto to provide a second partial response. The sum of the two partial responses is computed to provide the total estimated system response. The two independent filter units thus act simultaneously to provide twice as many coefficients as prior art AFIR filters in the same amount of time.

Abstract: A switched-capacity amplifier formed from integrated capacities has undesirable parasitic capacities that are large and variable on only one terminal of each of the capacities. A voltage-follower stage is connected to this terminal of each of the capacities (except those capacities which are grounded) to offset the parasitic capacity. The amplifier is also connected in a switched-capacity filter and a charge-transfer filter.

Abstract: A switched capacity filter having capacities formed by MOS technology on a semiconductor substrate. The connection between two capacities whose first plates are formed by the semiconductor substrate are periodically connected by providing transfer of charges in the substrate on which these two capacities are integrated. The external or other plate of each capacity receives, the input voltage, or a reference voltage, or the surface potential under another capacity which is provided by a reinjection and reading device formed from a diode and a voltage follower stage.

Abstract: Disclosed is a frequency converting filter comprised of a charge transfer device transversal filter and a non-sampling filter. The transversal filter has an output lead coupled to an input of the non-sampling filter, and has frequency passbands of width .DELTA.f centered at the fixed frequencies nf.sub.s .+-.f.sub.o. The non-sampling filter has a single passband. The single passband has a width of less than f.sub.s -f.sub.o -.DELTA.f/2 and it is centered to include only a selected one of the passbands of the transversal filter.

Abstract: Two analog filters of the second order are arranged in series with a transverse charge transfer filter upstream and downstream of the latter. The analog filters are switched capacitor filters having an amplifier and a network of capacitors and MOS transistors. The filtering device is entirely integrated onto the same semiconductor substrate.

Abstract: A clocking signal drive circuit supplies at least one clocking signal in a charge transfer device which has a plurality of successive capacitive storage elements for sequentially holding a charge level representing a time sampled input signal, with each of the capacitive storage elements having a clocking electrode for receiving one of a plurality of clocking signals so that the charge level representing the time sampled input signal is transferred from one to another of the capacitive storage means in succession in response to the clocking signals.