Abstract: A voltage conversion circuit and a control circuit thereof are provided. The control circuit includes a voltage selection circuit, a buffer circuit, and a pull-down switch. The voltage selection circuit receives an input voltage and an output voltage, and selects a smaller voltage value as a selected voltage from the input voltage and the output voltage. The buffer circuit receives the selected voltage, and provides the selected voltage as a reference voltage. A control end of the pull-down switch receives an enable signal, so that the pull-down switch is switched on or switched off based on the enable signal. The pull-down switch is switched on based on the enable signal, to pull down a voltage at a control end of a driver switch to the reference voltage and switch off the driver switch.

Abstract: Techniques are described for reducing or dampening harmonics in a power signal to be supplied to a power system. The techniques may also be used to synchronize the power signal to be supplied to the power system with the power that is currently present on the power system. The techniques operate to step down the signals to be processed, process the signals using low-current op amps, and then step the signals back up to be transmitted on a high current system. The values of the circuit components may be determined by using a solution for an accompanying transfer function.

Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Abstract: Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

Abstract: A resonance circuit includes a first resonator, a second resonator, a capacitance element and an inverting amplifier, and a negative capacitance circuit. The second resonator is connected to the first resonator in series. The capacitance element and the inverting amplifier are connected to one another in series. The capacitance element and the inverting amplifier are connected to the first resonator in parallel. The negative capacitance circuit is connected between a node and ground. The node is disposed between the first resonator and the second resonator.

Abstract: An amplification cell employing a linearization scheme and an active inductor using the same are provided. The active inductor includes: first and second amplification cells each including a main amplifying unit amplifying an input signal, an auxiliary amplifying unit connected in parallel to the main amplifying unit and eliminating nonlinear characteristics of the main amplifying unit while amplifying the input signal, and a negative load unit connected to an output terminal of the main amplifying unit and that of the auxiliary amplifying unit; a plurality of load resistors for tuning frequency; and a plurality of capacitors for tuning frequency, wherein an output from the first amplification cell is negatively fed back to the second amplification cell, an output from the second amplification cell is negatively fed back to the first amplification cell, and the plurality of load resistors and the plurality of capacitors are disposed on negative feedback paths of the first and second amplification cells.

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).

Abstract: An active bandpass filter is disclosed herein. The active bandpass filter has N transmission lines, N negative resistant circuits, a DC circuit, and at least (N?1) coupling circuit. Each transmission line has a first end and a second end. Each negative resistant circuit has a third end and a fourth end and is electrically coupled with a related transmission line, wherein the third end and the fourth end are electrically coupled with the first end and second end, respectively. The DC circuit provides a bias voltage for N negative resistant circuits, wherein the DC circuit electrically couples with N transmission lines via N coupling elements. Each coupling circuit has a fifth end and a sixth end and is electrically coupled with any two transmission lines, wherein the fifth end and sixth end are electrically coupled with the second end and the first end, respectively.

Abstract: Disclosed is a package having a thin film bulk acoustic resonator (FBAR). The package may be utilized for suppressing spurious resonance occurred during operation of the FBAR. The package includes a negative impedance converter (NIC) operatively coupled to the FBAR through at least one interconnect. The at least one interconnect includes transmission lines and bonding wires. The package further includes a filter operatively coupled to the NIC. The filter exhibits a parallel resonance at a predefined frequency. The parallel resonance exhibited by the filter is converted to a series resonance by the NIC such that the series resonance of the NIC is responsible for suppressing the spurious resonance occurring during the operation of the FBAR.

Abstract: Disclosed is a package having a thin film bulk acoustic resonator (FBAR). The package may be utilized for suppressing spurious resonance occurred during operation of the FBAR. The package includes a negative impedance converter (NIC) operatively coupled to the FBAR through at least one interconnect. The at least one interconnect includes transmission lines and bonding wires. The package further includes a filter operatively coupled to the NIC. The filter exhibits a parallel resonance at a predefined frequency. The parallel resonance exhibited by the filter is converted to a series resonance by the NIC such that the series resonance of the NIC is responsible for suppressing the spurious resonance occurring during the operation of the FBAR.

Abstract: Compensation of effects derived from bandwidth limitations of an active frequency-selective circuit is effected by appropriately coupling a resistance to the frequency-selective circuit. In one embodiment, the resistance is designed to have a value that is inversely related to the tangent of a phase-shift at a compensation frequency.

Abstract: A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance R3 and a first resistance R1 disposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance R1 is disposed in series with the first inductor and is equal to the parasitic resistance RL1 thereof. Likewise, a second resistance R2 is disposed in series with the second inductor and is equal to the parasitic resistance RL2 thereof. The Q enhancement circuit further includes a first transistor Q1 and a second transistor Q2.

Abstract: The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.

Abstract: There is provided a negative impedance converter, which has negative impedance conversion function by widening the available range of a generalized impedance converter. A generalized impedance converter is composed of two operational amplifiers Q1 and Q2 and four series-connected first to fifth impedance elements Z1 to Z4. The four impedance elements included in the generalized impedance converter are all set as the same resistor R1, and an impedance element Z6 is connected between the intermediate point B of the series-connected impedance elements and the ground. The magnitude of the impedance element Z6 is set smaller than that of load impedance element Z5. By doing so, the input impedance Z11? becomes negative, and the kind of the impedance is determined depending on the kind of the impedance elements Z5 and Z6.

Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: In order to improve Q of a tuning circuit by using a negative resistance circuit, a tuning circuit wherein a frequency selectivity characteristic and a tuning circuit gain does not vary and are kept constant values even if a tuning frequency is changed, is provided. The tuning circuit is constructed so as to compensate a series resistance component by connecting a negative resistance circuit to a series resonance circuit. The negative resistance circuit includes a differential amplifying circuit having two transistors emitters of which are connected in common, and a low output impedance circuit such as an emitter follower. The low impedance output is fed back to a same phase input side of the differential amplifying circuit directly and also to an inverse phase input side thereof to obtain a negative resistance value at this inverse input terminal.

Abstract: There is provided a negative impedance converter, which has negative impedance conversion function by widening the available range of a generalized impedance converter.

Abstract: A circuit for an apparatus is an active circuit that synthesizes self-induction. The active circuit comprises only one operational amplifier. With the use of tunable capacitors, the inductor synthesized by the active circuit becomes a tunable inductor.

Abstract: In order to improve Q of a tuning circuit by using a negative resistance circuit, a tuning circuit wherein a frequency selectivity characteristic and a tuning circuit gain does not vary and are kept constant values even if a tuning frequency is changed, is provided. The tuning circuit is constructed so as to compensate a series resistance component by connecting a negative resistance circuit to a series resonance circuit. The negative resistance circuit includes a differential amplifying circuit having two transistors emitters of which are connected in common, and a low output impedance circuit such as an emitter follower. The low impedance output is fed back to a same phase input side of the differential amplifying circuit directly and also to an inverse phase input side thereof to obtain a negative resistance value at this inverse input terminal.

Abstract: A method and a circuit for power amplification over a wide frequency range based upon the use of minimum-rating filters or matching networks, negative-component signal processing, and single or multiple amplifiers. The filters and matching networks are preferably designed to minimize the required ratings of the amplifier(s) driving them. The signal processor or generator preferably uses negative components to produces a driving signal that is compensated for the ripple in the filter, matching network, and load. The outputs of multiple amplifiers optimized for different frequency ranges can be combined into a single load with flat frequency response, resistive loads presented to the amplifiers, and no inherent power loss in the combining network.

Abstract: A tuning circuit has a simple circuit construction and is capable of setting Q thereof to a high desired value. The tuning circuit is formed by a resonance circuit consisting of an inductor and a capacitor and a negative resistance circuit connected in series to the resonance circuit including a negative impedance converter and a variable resistor. A counter counts clock signals from a clock signal generating circuit and a count value is converted to an analog signal by a D/A converter. The negative resistance circuit is controlled by the analog signal so that an effective resistance of the tuning circuit is made negative to oscillate and to vary a negative resistance value in a positive direction. When the effective resistance value becomes zero, oscillation stops and thereafter when a value of Q becomes a predetermined value, the clock signals are stopped and the latch circuit holds a final count value.

Abstract: A circuit and method for input side impedance matching of a power amplifier in an electronic device. Specifically, the present invention provides an impedance transformer network that includes a negative resistor in series with a bondwire inductor. The network is placed in parallel with a signal source and synthesizes the source side impedance at the input of the power amplifier. The desired impedance is synthesized by selecting an appropriate value for the negative resistor and setting the reactance of the inductor equal to the capacitance of the electronic device at a required frequency of operation.

Abstract: A tuning circuit enables its Q to be always maintained with the condition of high grade even when tuning frequency of the tuning circuit is changed. The tuning circuit is constituted in such a way that a negative resistance circuit is connected to the tuning circuit in series. Series resistance component of an inductor of the tuning circuit is divided into a fixed resistance component r0 having nothing to do with a frequency and a variable resistance component r1 which is changed depending on a frequency. Load resistances r0′, and r1′ of the negative resistance circuit are made to correspond to the fixed resistance component r0 and the variable resistance component r1 respectively. When changing the tuning frequency, operation is made to control in such a way that the load resistance r1′ of the negative resistance circuit which corresponds to the variable resistance component r1 is changed while corresponding to change of actual resistance value of the tuning circuit.

Abstract: In order to provide a tuning circuit having small, cheap and simple circuit construction capable of setting Q thereof to a high desired value, said tuning circuit is constituted by a resonance circuit consisting of an inductor and a capacitor and a negative resistance circuit connected to said resonance circuit in series including a negative impedance converter and a variable resistor.

Abstract: According to an embodiment of the present invention, a capacitor comprising field effect transistors and a bias transistor.

Abstract: A transistor M1 has its drain connected to a source of a transistor M2 through a capacitor Cc3. A series connection of a resistor R and a capacitor Cc3 is provided between a source of the transistor M1 and a gate of the transistor M2. The transistor M1 has its gate connected to a drain of the transistor M2 through a capacitor Cc2. Appropriate dc bias potentials P1, P2 and P3 are provided for the drain of the transistor M2, the gate and the drain of the transistor M1, respectively, so that an active inductor is obtained between the gate and the source of the transistor M2.

Abstract: A tuning circuit enables its Q to be always maintained with the condition of high grade even when tuning frequency of the tuning circuit is changed. The tuning circuit is constituted in such a way that a negative resistance circuit is connected to the tuning circuit in series. Series resistance component of an inductor of the tuning circuit is divided into a fixed resistance component r0 having nothing to do with a frequency and a variable resistance component r1 which is changed depending on a frequency. Load resistances r0′, and r1′ of the negative resistance circuit are made to correspond to the fixed resistance component r0 and the variable resistance component r1 respectively. When changing the tuning frequency, operation is made to control in such a way that the load resistance r1′ of the negative resistance circuit which corresponds to the variable resistance component r1 is changed while corresponding to change of actual resistance value of the tuning circuit.

Abstract: An innovated transimpedance amplifier circuit consists of a buffer circuit, a simulation resistance circuit, and an amplifier circuit. The buffer circuit for inputting a signal circuit is constituted by two FETs and a resistor, and has a high current input efficiency and function of widening circuit frequency band. The simulation resistance circuit is constituted by a resistor, two buffer units, a coupling capacitor, and a biasing resistor. When operating at a low frequency, the simulating resistance circuit permits a large amount of background DC to flow through; on the other hand, when operating at a high frequency, this circuit can improve the signal coupling efficiency and reduce foreign signal output voltage. On the whole, by the circuit of the present invention, both the detecting sensitivity and the amplification factor of the signal current can be significantly improved.

Abstract: A method and a circuit for power amplification over a wide frequency range based upon the use of minimum-rating filters or matching networks, negative-component signal processing, and single or multiple amplifiers. The filters and matching networks are preferably designed to minimize the required ratings of the amplifier(s) driving them. The signal processor or generator preferably uses negative components to produces a driving signal that is compensated for the ripple in the filter, matching network, and load. The outputs of multiple amplifiers optimized for different frequency ranges can be combined into a single load with flat frequency response, resistive loads presented to the amplifiers, and no inherent power loss in the combining network.

Abstract: An impedance matched branch connection for local area networks (LANs). A stub or branch connection increases the number of computers that can connect to a LAN. A star connection is formed when several stub lines are connected at the same point. Stub connections introduce an impedance discontinuity in the line and this discontinuity causes signal reflections which interfere with normal data transmission. The impedance discontinuity is avoided by providing a negative impedance device at the star point which makes the impedance at each transmission line appear as though the stub lines were not added.

Abstract: A low pass filter using two pseudo gyrators 10 and 20 is disclosed. The gate-source capacitances of field effect transistors forming the pseudo gyrator circuit can be considered to be included in capacitors for forming the low pass filter. Therefore, an ideal admittance matrix for a gyrator is obtained. Increase in integration density of the low pass filter can be achieved since the low pass filter is formed by a simplified pseudo gyrator circuit.

Abstract: A reactance circuit comprises a differential amplification circuit formed by differentially connecting the first and second transistors to each other, a load connected to a collector of the first transistor, a reactance element interposed between a base of the first transistor and a reference potential point, and a capacitor and a resistor connected in series between the collector and the base of the first transistor. A negative feedback loop to the first transistor is formed by the capacitor and the resistor. Accordingly, when the collector of the first transistor is used as an output terminal, a negative equivalent reactance is produced in the output terminal.

Abstract: A monodirectional, current-reducing impedance magnifier (MCRIM) provides continuously variable magnification of any general impedance Z.sub.0 without affecting its phase charateristics. The monodirectional, current-reducing impedance magnifier circuit realizes floating resistors, inductors and capacitors, suitable for use over any range of frequencies, and the simulated impedance is continuously user-variable over wide ranges. In another embodiment, a monodirectional, generalized impedance synthesizer (MGIS) permits simulation of user-variable floating impedances whose phase and frequency characteristics are widely subject to design objectives. In addition to realizing all conventional circuit elements R, L and C, including positive and negative values thereof, the MGIS produces an infinite set of alternatives for the simulation of user-variable resistance and reactance functions of frequency. The MGIS is also usable over any bandwidth.

Abstract: A negative admittance converter or a negative impedance converter can be formed from a negative immitance converter having two preferably identical transformers each having a center tapped coil and respective coil end terminals. One end of each of the coils is connected through a first amplifier element, and the other ends are connected through a second amplifier element, the amplifier elements having control inputs connected to a 180.degree. phase shifter. The phase shifter is formed by a voltage differential amplifier having one input connected to a voltage divider connected across the first amplifier element, and the other input connected to a voltage divider connected across the other amplifier element, the amplifier differential outputs being connected to the control inputs of the first and second amplifier elements.

Abstract: A variable reactance, the value of which is controllable, is produced between a pair of terminals of a variable reactance circuit comprising a pair of current steering circuits. First and second reactive components are coupled respectively between the pair of terminals and the first and second current steering circuits to produce first and second antiphase reactive currents'. The first reactive current is split by the first current steering circuit into first and second antiphased proportional currents. Likewise, the second reactive current is split by the second current steering circuit into third and fourth antiphased proportional currents with said first and third currents being antiphased with respect to each other. The first reactive current is summed at a first one of the pair of terminals with said first and third currents while the second reactive current is summed at the second one of the pair of terminals with said second and fourth currents to produce the variable reactance across the terminals.

Abstract: Two terminal negative admittance networks are disclosed. The preferred networks include a pair of opposite type transistors or a field-effect transistor combined with a bipolar transistor of the opposite type. These networks operate over a very wide frequency range and also can function with a very small operating current.

Abstract: A variable reactance circuit which can produce equivalent reactance varying from negative given values to positive given values in accordance with fundamental reactance elements such as capacitor, coil, etc. The present invention has a big advantage of being capable of easily producing the positive, negative equivalent reactance given times as much as the basic reactance element with the use of a circuit which can be integrated.

Abstract: A bilateral amplifier is disclosed, which comprises a negative impedance converter which is connected between two signal sources similar in character when viewed as loads. One of the signal sources is utilized as a load for negative impedance conversion with respect to the other signal, while the other signal source is utilized as a load for negative impedance conversion with respect to the first-mentioned signal source.

Abstract: Communication lines for example telephone loop circuits are typically terminated with line feed circuits such that d.c. and a.c. terminating impedances are dissimilar. The line feed circuit includes tip and ring feed resistors of similar ohmic values for supplying the communication line with energizing current. An a.c. terminating impedance of greater ohmic value than the d.c. terminating resistance is provided by a negative impedance circuit which is a.c. coupled across the communication line, in shunt with the feed resistors.

Abstract: An improved impedance generator circuit, for use with two-wire transmission systems of the type encountered in telephony, is adapted to be interfaced with the wires and operates in a manner to effectively generate a desired positive or negative impedance across the wires. The impedance generator includes a current source, and generates a positive impedance by drawing from the wires all of the current that would otherwise be required by the positive impedance, or a negative impedance by providing on the wires all of the current that would otherwise be provided by the negative impedance, in response to a metallic voltage applied across the wires by a signal source. At the same time, the impedance generator provides common mode rejection to longitudinal voltages on the wires.

Abstract: A filter network that exhibits a bandstop response comprises a network of basically low pass or high pass structure. The network is developed by choosing a bandstop transfer function, a fourth-orderelliptic is disclosed, which is converted to a low pass function. This function describes a passive low pass LC ladder network including a negative impedance element. A Bruton transformation is applied to the passive LC network to give an active version including an ungrounded negative resistance network in a series arm and frequency-dependent negative resistances in shunt arms without requiring inductance coils for its implementation.

Abstract: A two terminal circuit comprising a capacitive element (with a negative capacitance of value -C/2) connected between the terminals, and an integrated capacitor (with a positive capacitance C) having one and other sides thereof alternately or periodically connected to associated sides of the element and to ground for simulating a floating bilinear resistor having a resistance R=T/C across the terminals which satifies the bilinear transformation s=(2(z-1/T)z+1). This circuit is insensitive to both top and bottom plate parasitic capacitance effects assocated with the capacitance when one terminal is connected to a voltage source and the other to a virtual ground point on the input to an operational amplifier. In alternate embodiments, the circuit simulates a grounded bilinear resistor when only one of the terminals is connected to ground, and when one terminal and one side of the capacitor are grounded.

Abstract: Within a negative impedance network of the type which includes a current mirror amplifier having transistors in master and slave paths, a bias current is applied at the commonly connected control electrodes of the master and slave path transistors in inverse proportion to the voltage applied across the slave path and thereby a negative impedance characteristic is derived through the slave path.

Abstract: The present invention relates generally to electrical signal transmission lines which are terminated in a manner enabling efficient use of signal energy transmitted through such lines while preventing signal reflections in such lines, and in particular is directed to a termination circuit for a lossy delay line which includes a pair of emitter coupled transistors having positive feedback to develop a negative impedance to terminate the lossy delay line to compensate for the loss in the lossy delay line.

Abstract: An improved negative impedance converter is provided comprising an additional differential operational amplifier to improve signal handling capability.

Abstract: A construction of an active filter having the same characteristics as a predetermined passive filter is described in which the capacitors of the passive filters are replaced by a topologically equivalent first network of resistors and the inductors of the passive network are replaced by a topologically equivalent second network of resistors, the two networks of the resistors being interconnected in a manner corresponding to the connections in the passive filter and connected to points corresponding to interconnection points of the passive filter by means of negative impedance converters, the converters connected to the first network having conversion ratios effective to convert resistance into negative capacitance and the converters connected to the second network having conversion ratios effective to convert resistance into negative inductance. The input and output to the active filter may be through similar negative impedance converters or may be directly to points in one or other resistive networks.