Providing Negative Resistance Patents (Class 333/217)
  • Patent number: 10694289
    Abstract: One example includes a system that is comprised of a speaker, an amplifier, a current sensor, and a compensator circuit. The speaker produces audio in response to an amplified analog input signal received at a speaker input. The amplifier receives an analog audio input signal and provides the amplified analog audio input signal to the speaker input. The current sensor senses current passing through the speaker and provides a current sensor signal indicative thereof. The compensator circuit applies a transfer function to the current sensor signal to provide a compensation signal as feedback into the analog audio input signal, the transfer function matching at least one of resistance and inductance of the speaker.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 23, 2020
    Inventors: Rahmi Hezar, Rajan Narasimha, Srinath Ramaswamy
  • Patent number: 10171051
    Abstract: An amplification circuit coupled to another circuit by alternating current (AC) coupling includes: an amplifier that amplifies and outputs a signal input from the other circuit or amplifies an input signal and outputs the amplified input signal to the other circuit; a feedback circuit that positively feeds back the signal output from the amplifier to an input of the amplifier; and a low pass filter that attenuates a high frequency component of the signal positively fed back to the input of the amplifier by the feedback circuit, and in which a higher cut-off frequency is set such that a lower cut-off frequency in a combination of the amplification circuit and a high pass filter formed by the AC coupling is lower than a lower cut-off frequency in the high pass filter.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 1, 2019
    Inventor: Hideki Oku
  • Patent number: 9654064
    Abstract: An audio amplifier apparatus includes an audio amplifier which receives a single audio signal and produces a plus phase audio signal and a minus phase audio signal, both dependent upon the single audio signal. The plus phase audio signal and minus phase audio signal are received by first and second inputs of a speaker, respectively. A current sensing circuit senses a level of current received by the first or second inputs of the speaker and outputs a current sensing signal dependent upon the sensed level of current. An amplifying circuit receives and amplifies the current sensing signal. A mixer circuit receives the amplified current sensing signal and an audio drive signal and produces the single audio signal dependent upon the amplified current sensing signal and the audio drive signal. The single audio signal is produced at a node in-between two resistors.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 16, 2017
    Assignee: Panasonic Automotive Systems Company of America, Division of Panasonic Corporation of North America
    Inventor: Richard Fay
  • Patent number: 9184729
    Abstract: The reconfigurable Nth-order filter includes a CCII adopting active current division networks for implementing the proposed filter. This digitally programmable second generation current conveyor leads to wide control of filter coefficients for reconfiguration of the filter. Programmability characteristics are demonstrated through experimental results obtained from integrated circuit chips fabricated in a 0.18 ?m CMOS process.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: November 10, 2015
    Inventor: Hussain Alzaher
  • Patent number: 9124279
    Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital converters (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancellation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.
    Type: Grant
    Filed: September 3, 2012
    Date of Patent: September 1, 2015
    Assignee: Tensorcom, Inc.
    Inventor: Dai Dai
  • Patent number: 8988173
    Abstract: A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as “non-Foster circuits.” The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: March 24, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Donald A. Hitko, Carson R. White, Michael W. Yung, David S. Matthews, Susan L. Morton, Jason W. May, Joseph S. Colburn
  • Patent number: 8878636
    Abstract: Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: November 4, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Padraig Cooney
  • Publication number: 20140285180
    Abstract: An improved measurement circuit includes a current transformer and an active feedback circuit operated as a negative resistance that matches the value of the winding resistance of the current transformer. An amplifier in the feedback circuit provides power to drive a secondary current through a sense resistor and the transformer winding resistance, reducing the most significant error source in a current transformer circuit by presenting a negative impedance to the current transformer. Combined with the positive resistance of the transformer's winding, the negative impedance results in a net burden of zero on the current transformer, which eliminates the need for the transformer having to provide power to drive the secondary current. This facilitates the use of smaller transformers while achieving reduced measurement errors. Thus, a single, compact measurement device may be used in a wide range of applications with high measurement performance.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 25, 2014
    Applicant: National Instruments Corporation
    Inventor: Garritt W. Foote
  • Patent number: 8604887
    Abstract: The current-feedback operational amplifier-based sinusoidal oscillator provides oscillations based on a single external resistor and a single external capacitor, which exploit the internal parasitic components of the CFOA. The external resistor and external capacitor are passive, externally connected, and grounded.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: December 10, 2013
    Assignee: King Fahd University of Petroleum and Minerals
    Inventor: Muhammad Taher Abuelma'atti
  • Patent number: 7683681
    Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes an active inductor unit, a source injection unit, a first transistor and a second transistor. The injection-locked frequency divider generates a frequency-divided signal having a half frequency of the signal source. A locking frequency range of the injection-locked frequency divider is determined by a quality factor of a resonant cavity. A quality factor of the active inductor unit is lower than a conventional spiral inductor because the active inductor unit is composed of active elements. In the injection-locked frequency divider, the active inductor unit is used to instead of the conventional spiral inductor, so that the chip area can be reduced and the locking frequency range of the injection-locked frequency divider can be increased. Further, an induction value of the active inductor unit can be altered to change the locking frequency range of the injection-locked frequency divider.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 23, 2010
    Assignee: National Taiwan University of Science and Technology
    Inventors: Sheng-Lyang Jang, Cheng-Chen Liu, Jui-Cheng Han
  • Patent number: 7522024
    Abstract: A circuit for synthesising a negative resistance, comprising first and second active devices, the first device having a control terminal connected to a first node, and the second device having a current flow terminal connected to the first node, and the first and second devices interacting with each other such that the circuit synthesises a negative resistance.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: April 21, 2009
    Assignee: MediaTek Inc.
    Inventor: Federico Alessandro Fabrizio Beffa
  • Publication number: 20080315964
    Abstract: A tunable active inductor and a voltage controlled oscillator (VCO) are provided. The tunable active inductor includes a first current source coupled to a power source, a first metal-oxide semiconductor (MOS) transistor including a drain coupled to the first current source and a gate coupled to a first bias voltage, a second MOS transistor including a drain coupled to the power source and a gate coupled to the drain of the first MOS transistor, the gate of the second MOS and the drain of the first MOS being coupled to a second bias voltage, a resonator coupled to a source of the second MOS transistor, and a second current source coupled to the resonator. The VCO employs the tunable active inductor to freely vary the oscillation range of the VCO in a high frequency band.
    Type: Application
    Filed: June 20, 2008
    Publication date: December 25, 2008
    Inventor: Su Tae Kim
  • Patent number: 7202762
    Abstract: A Q enhancement circuit and method. In a most general embodiment, the inventive circuit is adapted for use with a component having a parasitic resistance R3 and a first resistance R1 disposed in series with the component and an arrangement for making the resistance a negative resistance. In the illustrative embodiment, first and second inductors constitute the components for which Q enhancement is effected. A resistance R1 is disposed in series with the first inductor and is equal to the parasitic resistance RL1 thereof. Likewise, a second resistance R2 is disposed in series with the second inductor and is equal to the parasitic resistance RL2 thereof. The Q enhancement circuit further includes a first transistor Q1 and a second transistor Q2.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: April 10, 2007
    Assignee: Raytheon Company
    Inventor: Louis Luh
  • Patent number: 7119640
    Abstract: The present invention provides an improved Chua's circuit providing current mode operation, access to all state variables, minimum use of grounded passive elements, and freedom from passive component matching comprising a dual output current conveyer based inductor having one grounded terminal, a capacitor connected across the second terminal of said inductor, a resistor having one terminal connected to the second terminal of said inductor, the second terminal of said resistor connected to one terminal of a second capacitor the other end of which is grounded, and a pair of dual output current conveyers connected together to form a 2-terminal negative resistance having one terminal connected to ground and the second terminal connected to the second terminal of said resistance.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: October 10, 2006
    Assignee: STMicroelectronics Pvt Ltd.
    Inventor: Gaurav Gandhi
  • Patent number: 6985053
    Abstract: In order to provide a negative resistance circuit which is not influenced by means of change of temperature and source voltage, etc., operates stably and has simple circuit construction, a first stage circuit of the negative resistance circuit is a collector-emitter dividing type amplifying circuit comprising of a npn transistor and a second stage circuit thereof is an emitter earth type amplifying circuit comprising of a pnp transistor. A collector output of the pnp transistor is connected to a base of the npn transistor to constitute a positive feedback path and is divided and is connected to an emitter of the npn transistor to constitute a negative feedback path. An amplification factor A of the emitter earth type amplifying circuit and voltage dividing ratio ? is set to be (1+A?)<A.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: January 10, 2006
    Assignee: General Research of Electronics, Inc.
    Inventor: Kazuo Kawai
  • Patent number: 6954123
    Abstract: Selectivity Q of a tuning circuit is maximized by using a negative resistance circuit that is not influenced significantly by changes in conditions such as temperature, source voltage, etc. The tuning circuit operates stably and is constituted by a series resonance circuit and the negative resistance circuit connected thereto. The negative resistance circuit can be a C-E dividing type circuit including a npn transistor as a first stage circuit and an emitter earth type amplifying circuit including a pnp transistor as a second stage circuit. A collector output of the pnp transistor is connected to an emitter of the npn transistor to constitute a negative feedback circuit and the collector output is divided and connected to a base of the npn transistor to constitute a positive feedback circuit. Selectivity Q is improved by the negative resistance circuit provided by the negative feedback circuit.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: October 11, 2005
    Assignee: General Research of Electronics, Inc.
    Inventor: Kazuo Kawai
  • Patent number: 6870447
    Abstract: A tuning circuit using a negative resistance circuit for compensating an equivalent series resistance component thereof is provided. The negative resistance circuit has simple circuit construction and design and adjustment thereof is easy. The tuning circuit comprises a series resonance circuit and a negative resistance circuit connected to the series resonance circuit in series. In the negative resistance circuit, a first transistor constitutes an inverse amplifier by providing a resistor in an emitter circuit thereof and a second transistor constitutes an emitter follower circuit. A positive feedback circuit is constituted by feeding back an output of the emitter follower circuit to an emitter circuit of the first transistor and a negative feedback circuit is constituted by feeding back an output terminal to a base circuit of the first transistor. Thus a negative resistance is produced between this base input terminal and an earth.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: March 22, 2005
    Assignee: General Research of Electronics, Inc.
    Inventor: Kazuo Kawai
  • Publication number: 20040183628
    Abstract: In order to provide a negative resistance circuit which is not influenced by means of change of temperature and source voltage, etc., operates stably and has simple circuit construction, a first stage circuit of the negative resistance circuit is a collector-emitter dividing type amplifying circuit comprising of a npn transistor and a second stage circuit thereof is an emitter earth type amplifying circuit comprising of a pnp transistor. A collector output of the pnp transistor is connected to a base of the npn transistor to constitute a positive feedback path and is divided and is connected to an emitter of the npn transistor to constitute a negative feedback path.
    Type: Application
    Filed: January 28, 2004
    Publication date: September 23, 2004
    Inventor: Kazuo Kawai
  • Publication number: 20040130416
    Abstract: In order to improve selectivity Q of a tuning circuit by using a negative resistance circuit which is hard to be influenced by means of change of use condition such as temperature, source voltage, etc., operates stably and has simple circuit construction, the tuning circuit is constituted by a series resonance circuit and a negative resistance circuit connected thereto.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Inventor: Kazuo Kawai
  • Patent number: 6747531
    Abstract: A circuit and method for input side impedance matching of a power amplifier in an electronic device. Specifically, the present invention provides an impedance transformer network that includes a negative resistor in series with a bondwire inductor. The network is placed in parallel with a signal source and synthesizes the source side impedance at the input of the power amplifier. The desired impedance is synthesized by selecting an appropriate value for the negative resistor and setting the reactance of the inductor equal to the capacitance of the electronic device at a required frequency of operation.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: June 8, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Vickram R. Vathulya
  • Patent number: 6734767
    Abstract: The invention refers to a diplexer, particularly for use in microwave devices, comprising a low-pass filter and a high-pass filter, both having inductors and capacitors. It is suggested that at least one inductor of each of said filters is provided as an active inductor.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: May 11, 2004
    Assignee: Alcatel
    Inventors: Justine Vanoverschelde, Georges Coury, Lucien Loval
  • Patent number: 6628181
    Abstract: A tuning circuit is constructed to set Q of the tuning circuit to a high desired value by using a negative resistance value. The tuning circuit is made to oscillate weakly by using a negative resistance circuit, a voltage-resistance converter and a digital-analog converter. A negative resistance of the negative resistance circuit is scanned by a counter so that two negative resistance values corresponding to an oscillation amplitude and another oscillation amplitude of one half are obtained by analog comparators COMP1 and COMP2. A negative resistance value to be set is operated by an adder/subtracter from a series resistance value corresponding to a desired Q and this value. Scanning is stopped when the negative resistance value is obtained. The tuning circuit can be formed by small size digital integrated circuits.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 30, 2003
    Assignee: General Research of Electronics, Inc.
    Inventor: Kazuo Kawai
  • Patent number: 6583685
    Abstract: A matching circuit for a screen antenna receives on its signal input an MF or LF signal output of a screen antenna and feeds a signal though its signal output via a capacitive feeder to a radio receiver. The matching circuit includes components which operate in conjunction with capacitances in components connected to the signal input and the signal output to form an internally-terminated band-pass filter network having a pass-band which covers a range of frequencies to be received by the receiver.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: June 24, 2003
    Assignee: Glass Antennas Technology Limited
    Inventors: Brian Easter, Keith Jeremy Twort, John Davies
  • Publication number: 20030042979
    Abstract: A group delay adjusting circuit. The group delay adjusting circuit comprises an electronically adjustable variable capacitance, and an electronically variable virtual inductor coupled in parallel to the electronically variable capacitance at a node.
    Type: Application
    Filed: May 20, 2002
    Publication date: March 6, 2003
    Inventors: Mark Gurvich, Alex Rabinovich, Nikolai Maslennikov, Jianquing He
  • Patent number: 6504458
    Abstract: In order to automatically set a Q value to an optimal value, a tuning circuit has a resonance circuit composed of an inductor and a capacitor. The resonance circuit includes a negative resistance circuit having a dummy load resistance and a negative impedance converter. An operating circuit provides the dummy load resistance so that a negative resistance value is output to obtain a desired Q value.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: January 7, 2003
    Assignee: General Research of Electronics, Inc.
    Inventor: Kazuo Kawai
  • Publication number: 20020118082
    Abstract: In order to set up automatically Q value by optimal value, a tuning circuit connected a resonance circuit composed of an inductor and a capacitor, it is connected a resonance circuit of an inductor and a capacitor with a negative resistance circuit comprised of a dummy load resistance and a negative impedance transform circuit NIC in series, is constituted the tuning circuit.
    Type: Application
    Filed: August 16, 2001
    Publication date: August 29, 2002
    Inventor: Kazuo Kawai
  • Patent number: 6366172
    Abstract: The present invention has an objective of providing a semiconductor amplifier circuit having a cascode amplifier in which a negative characteristic of an output conductance is improved at least in a particular frequency band. A semiconductor amplifier 1 includes a cascode amplifier 500 having a transistor 101 and a transistor 102 which are cascaded, and improvement means for improving the negative characteristic of the output conductance Gout of the cascode amplifier 500 at least in a particular frequency band.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: April 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Joji Hayashi, Hiroshi Kimura
  • Patent number: 6356143
    Abstract: A variable bandpass filter system passes a selected range of frequencies while rejecting other frequencies in an RF input signal. The system includes a switch and an oscillator. The switch receives the RF input signal and an oscillating calibration signal, and passes the RF input signal or said oscillating calibration signal based on a control signal. The oscillator receives an output of the switch, and frequency and gain control signals. The frequency control signal selects an operating frequency of the oscillator, such that the operating frequency determines a range of frequencies to pass. The gain control signal selects gain of the oscillator, where the oscillating calibration signal allows the oscillator to be calibrated by varying the gain such that the oscillator acts as a filter.
    Type: Grant
    Filed: November 1, 1999
    Date of Patent: March 12, 2002
    Assignee: Intreon Corporation
    Inventor: Steven B. Waltman
  • Patent number: 6307442
    Abstract: A tunable electronic filter circuit is provided including an input terminal and an output terminal connected to the input terminal with a node therebetween. An inductor, a variable capacitor, and a variable resistor are connected between the node and ground. Coupled to the variable capacitor and the variable resistor is a feedback control circuit. The feedback control circuit is operable to tune the variable capacitor in order to set a predetermined frequency, or center frequency, of the electronic filter circuit. The feedback control circuit is further operable to tune the variable resistor in order to calibrate a quality factor of the electronic filter circuit. In use when an input signal is applied to the input terminal, the electronic filter circuit passes an output signal to the output terminal. Such output signal includes components of the input signal within a predetermined frequency bandwidth set by the predetermined frequency and filters out other components of the input signal.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 23, 2001
    Assignee: Maxim Integrated Products
    Inventors: Robert G. Meyer, Madhu Avasarala
  • Patent number: 6114930
    Abstract: An impedance device has a first conductor and a second conductor, the first and second conductors being positioned in relation to each other so as to provide magnetic coupling between them. The impedance of the impedance device is controlled by receiving, in the first conductor, a first electric signal having a first amplitude and a first phase angle, generating a second electric signal having a second amplitude and a second phase angle, delivering the second electric signal to the second conductor, and controlling the second phase angle.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: September 5, 2000
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Jose-Maria Gobbi, Ted Johansson
  • Patent number: 5959504
    Abstract: A voltage controlled oscillator (VCO) CMOS circuit wherein back gate terminals of CMOS transistors are used to vary the parasitic capacitances of the transistors. The back gate terminals receive a signal from a variable voltage source so that oscillation can be controlled by adjusting the variable voltage. The CMOS transistors are connected across an inductor and the transconductance characteristics of the transistors reduce the resistance of the inductor, thereby improving circuit oscillation and providing enhanced stability and capabilities at high operating frequencies.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: September 28, 1999
    Inventor: Hongmo Wang
  • Patent number: 5939941
    Abstract: A high efficiency power amplifier includes an integrated circuit with a heterojunction interband tunneling field effect transistor (HITFET) amplifier coupled to receive high frequency (into the GHz) RF signals. The HITFET amplifier is constructed to receive the RF signal with a given frequency at the input terminal and to produce a substantially square wave signal at the given frequency at an output terminal in response to the RF signal applied to the input terminal. The gate of a switching FET connected as a class E amplifier is coupled to the output of the HITFET for receiving the square wave signal and an impedance matching output circuit is coupled to the drain of the switching FET.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: August 17, 1999
    Assignee: Motorola, Inc.
    Inventors: Vijay K. Nair, George N. Maracas, Herbert Goronkin
  • Patent number: 5890058
    Abstract: In an FDNR type active filter fabricated on an integrated circuit, an FDNR circuit is provided wherein one ends of a first capacitor and an impedance element are connected to an inverted input of an operational amplifier, one ends of the impedance element and a second capacitor are connected to an output end of the operational amplifier, and the other ends of the first and second capacitors are connected to each other. To the impedance element, resistors are connected in series. To the connecting end of the resistors, one end of another resistor is connected, the other end thereof being grounded in an alternating current form. The capacity value of the second capacitor is greater than that of the first capacitor.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: March 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ueno, Tetsuro Itakura, Hiroshi Tanimoto
  • Patent number: 5726613
    Abstract: An active inductor having a greater inductance, low loss, and which is small is provided by the present invention. The active inductor comprises a common source FET and a cascode-connected common gate FET connected thereto for providing unidirectional feedback. The drain electrode of the front FET and the source electrode of the rear FET, consisting of the common gate cascode FET, are connected together. A resistor is connected at one end to this connection. The two terminals of the active inductor correspond to the other end of the resistor and the source electrode of the common source FET. A frequency independent negative resistance is generated in series with the inductance by this configuration. By properly tuning the resistance of the resistor, it is possible to make the impedance viewed from the two terminals to have inductance component only, and therefore an active inductor having less resistance loss is obtained.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: March 10, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hitoshi Hayashi, Masashi Nakatsugawa, Masahiro Muraguchi
  • Patent number: 5550520
    Abstract: An active tuneable band-pass filter is provided which has a negative resistance circuit for generating a tuneable amount of negative resistance for a passive band-pass filter structure so as to compensate for resistive losses. The negative resistance circuit has a bipolar transistor with a base connected in shunt to the passive filter structure and a collector connected to a shunt inductive element. A negative resistance is generated at the base of the transistor and is applied to the passive filter structure. A coarse Q-factor tuning circuit is coupled to the emitter of the transistor for providing a coarse amount of tuning of the negative resistance. Also connected to the emitter terminal, is a fine tuning circuit for providing fine tuning of the negative resistance. The fine tuning may be achieved manually or automatically with a control circuit.
    Type: Grant
    Filed: April 11, 1995
    Date of Patent: August 27, 1996
    Assignee: TRW Inc.
    Inventor: Kevin W. Kobayashi
  • Patent number: 5451915
    Abstract: A negative resistance generator includes first and second terminals; first and second inductors connected in series between the terminals; and a semiconductor amplifying device having a first control electrode connected to the first terminal and a first active electrode connected to the second terminal and a second active electrode connected to the junction of the inductors. When employed in an active filter resonator a first variable capacitor is interconnected with the inductors for setting the resonant frequency of the resonator. The resonators may be combined in an active filter with a transmission line where each of the resonators is interconnected to the line by decreasing resistance from the input to the output in order to balance the rf currents to which the resonators are subjected.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: September 19, 1995
    Assignee: Hittite Microwave Corporation
    Inventors: Peter J. Katzin, Yalcin Ayasli, Brian E. Bedard
  • Patent number: 5424686
    Abstract: A monolithic microwave buffer amplifier is adapted to increase its input impedance at microwave frequencies. Capacitive reactances in first and second stages of the buffer amplifier appear collectively at the input of the first stage as a negative resistance. Compensating positive resistance is electrically connected to the input of the first stage to cancel the negative resistance and provide a sufficiently high resistive input impedance.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: June 13, 1995
    Assignee: Philips Electronics North America Corporation
    Inventors: Stephen L. Wong, Jose M. Garcia
  • Patent number: 5343172
    Abstract: Series reactance elements constituted by capacitors are connected to an input side corresponding to the gate electrode of an amplifying FET and an output side corresponding to the drain electrode of the amplifying FET, respectively. Parallel variable reactance circuits are connected to the input and output sides, respectively. Each variable reactance circuit includes a FET, where the source electrodes of the FET are connected to the input and output sides through MIM capacitors, respectively. Additionally, drain electrodes of the FETs are grounded through inductive loads which are constituted by spiral inductors, respectively. The source electrodes of the FETs constituting the variable reactance circuits are grounded through choke coils, respectively. The drain electrodes of the FETs receive control bias voltages through the choke coils, respectively.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: August 30, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Junsi Utsu, Seishin Mikami, Masao Kodera
  • Patent number: 4995054
    Abstract: A transmission arrangement includes a switched resonant circuit (5) for switching data states of digital signals on a pair of transmission lines (1, 2) and a regenerative circuit (7) for feeding power back on the lines. The switched resonant circuit has a switching device (22) connected in series with an inductance (20) and parallel with a capacitance (21). A digital logic system (8) controls the switching device such that switching occurs at a line current zero crossover point. Where a change of data state is to be transmitted to a receiver (6), the logic system (8) turns the switching device on at an appropriate time. The switching device is switched off when the voltage (+Vm) on the lines reaches approximately the same magnitude in the opposite sense (-Vm). The change in the line voltage indicates a change of the data state to the receiver.
    Type: Grant
    Filed: April 14, 1989
    Date of Patent: February 19, 1991
    Inventor: Gregory P. Eckersley
  • Patent number: 4963845
    Abstract: A monodirectional, current-reducing impedance magnifier (MCRIM) provides continuously variable magnification of any general impedance Z.sub.0 without affecting its phase charateristics. The monodirectional, current-reducing impedance magnifier circuit realizes floating resistors, inductors and capacitors, suitable for use over any range of frequencies, and the simulated impedance is continuously user-variable over wide ranges. In another embodiment, a monodirectional, generalized impedance synthesizer (MGIS) permits simulation of user-variable floating impedances whose phase and frequency characteristics are widely subject to design objectives. In addition to realizing all conventional circuit elements R, L and C, including positive and negative values thereof, the MGIS produces an infinite set of alternatives for the simulation of user-variable resistance and reactance functions of frequency. The MGIS is also usable over any bandwidth.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: October 16, 1990
    Inventor: Robert L. Collier
  • Patent number: 4943956
    Abstract: A driving apparatus for electrically driving a vibrator constituting an acoustic apparatus, wherein the output impedance of the driving apparatus is negative at least one frequency associated with the output sound pressure of the acoustic apparatus among resonance frequencies when the acoustic apparatus is viewed from a terminal for driving the vibrator, and the ratio of the output impedance to the internal impedance inherent in the vibrator never becomes constant over all the acoustic reproduction range of the acoustic apparatus. Then, it is possible to eliminate mutual dependency between resonance systems having the resonance frequencies, design of the resonance systems become easy, and improved performance of sound radiation can be expected.
    Type: Grant
    Filed: April 19, 1989
    Date of Patent: July 24, 1990
    Assignee: Yamaha Corporation
    Inventor: Masao Noro
  • Patent number: 4904952
    Abstract: A differential amplifier capable of achieving a large amplification, a wide frequency range, a high common mode rejection ratio, and a wide dynamic range simultaneously includes a device to produce negative resistance connected to output terminals. The differential amplifier also includes level shift circuits to generate additional voltages.
    Type: Grant
    Filed: October 6, 1988
    Date of Patent: February 27, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Tanimoto
  • Patent number: 4816788
    Abstract: A high frequency band-pass filter which includes a single resonator or a plurality of resonators adapted to pass a high frequency signal of a predetermined frequency band region, and an active element device electrically coupled with one or the plurality of the resonators so as to present a negative resistance when the resonator is in a resonant state.
    Type: Grant
    Filed: June 30, 1987
    Date of Patent: March 28, 1989
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Youhei Ishikawa, Hiroaki Tanaka
  • Patent number: 4751480
    Abstract: An overcoupled resonator having a resonant cavity defined by a thin film of magnetic material with a pair of end walls parallel to a transducer. Because this resonator is overcoupled, it is suitable for use in a broadband oscillator.
    Type: Grant
    Filed: November 14, 1986
    Date of Patent: June 14, 1988
    Assignee: Hewlett-Packard Company
    Inventors: William E. Kunz, Kok W. Chang, Waguih S. Ishak
  • Patent number: 4720665
    Abstract: A transducer for converting electrical input signals into an electrical or mechanical output. The transducer employs a circuit for producing a negative source impedance and a winding cooperating with the circuit. The winding has first and second parts connected end to end. The ratio of the induced electromotive forces developed across the first part relative to that of the second part differs from the ratio of the ohmic resistance of the first part relative to that of the second part.
    Type: Grant
    Filed: October 2, 1986
    Date of Patent: January 19, 1988
    Assignee: Willi Studer A.G. Fabric fur elektronische Apparate
    Inventor: Paul Zwicky
  • Patent number: 4686486
    Abstract: A fourth (or higher) order filter has a series resonant section terminated by a parallel resonant section, both based on frequency dependent negative resistance (FDNR). The FDNR, resistance and capacitance (representing damping) of the series section are provided by a capacitive potential divider (C41,C42) connected between low impedance input (A) to the filter and an intermediate terminal forming the input of a unity-gain amplifier (A4) whose output is connected via a resistance (R4O) to the tapping point of the divider; the intermediate terminal is connected via a second resistance (R1) to the parallel section.
    Type: Grant
    Filed: July 5, 1985
    Date of Patent: August 11, 1987
    Assignee: British Telecommunications public limited company
    Inventors: Alan J. Greaves, Phillip J. Hunter
  • Patent number: 4644306
    Abstract: A predetermined and variable synthesized capacitance which may be incorporated into the resonant portion of an electronic oscillator for the purpose of tuning the oscillator comprises a programmable operational amplifier circuit. The operational amplifier circuit has its output connected to its inverting input, in a "follower" configuration, by a network which is low impedance at the operational frequency of the circuit. The output of the operational amplifier is also connected to the non-inverting input by a capacitor. The non-inverting input appears as a synthesized capacitance which may be varied with a variation in gain-bandwidth product of the operational amplifier circuit. The gain-bandwidth product may, in turn, be varied with a variation in input set current with a digital to analog converter whose output is varied with a command word. The output impedance of the circuit may also be varied by varying the output set current.
    Type: Grant
    Filed: July 15, 1985
    Date of Patent: February 17, 1987
    Assignee: The United States of America as represented by the administrator of the National Aeronautics and Space Administration
    Inventor: Leonard L. Kleinberg
  • Patent number: 4608543
    Abstract: Disclosed is a circuit providing a controllable effective resistance which comprises of transistor means that provides current at an input node responsive to an input voltage at the input node. The transistor means is coupled to a settable current source which operates to control the effective value of the controllable effective resistance. The invention also includes a filter which employs the controllable effective resistance to vary the breakpoint frequency of the filter. Also, a phase-locked loop apparatus employing the filter is disclosed.
    Type: Grant
    Filed: December 17, 1984
    Date of Patent: August 26, 1986
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Neil R. Adams
  • Patent number: 4554504
    Abstract: A compensated circuit for use in interfacing a transmission device to a cable facility. The circuit includes a transformer one winding of which is connected to the cable facility and the other winding of which is connected through an impedance generating device to the transmission device. The circuit provides a predetermined one of a number of selectable impedances to the cable facility. The impedance generating device allows the desired impedance to be elected and includes a negative resistance generating circuit which responds to the current flowing in the loop formed by the winding and the impedance generating device.
    Type: Grant
    Filed: April 30, 1984
    Date of Patent: November 19, 1985
    Assignee: Reliance Electric Company
    Inventor: Philip L. Dillon
  • Patent number: 4532384
    Abstract: Communication lines for example telephone loop circuits are typically terminated with line feed circuits such that d.c. and a.c. terminating impedances are dissimilar. The line feed circuit includes tip and ring feed resistors of similar ohmic values for supplying the communication line with energizing current. An a.c. terminating impedance of greater ohmic value than the d.c. terminating resistance is provided by a negative impedance circuit which is a.c. coupled across the communication line, in shunt with the feed resistors.
    Type: Grant
    Filed: February 4, 1983
    Date of Patent: July 30, 1985
    Assignee: Northern Telecom Limited
    Inventors: Magdy H. Keriakos, Stanley D. Rosenbaum