Abstract: The mounting area for an electronic component and a resistor for current detection is reduced. A current detection resistor for detecting current includes a plate-like resistive body, and a first electrode and an opposite second electrode which are stacked in a thickness direction of the resistive body and are disposed so as to sandwich the resistive body. The first electrode has a groove portion.

Abstract: A surface mount component is disclosed including an electrically insulating beam that is thermally conductive. The electrically insulating beam has a first end and a second end that is opposite the first end. The surface mount component includes a thin-film component formed on the electrically insulating beam adjacent the first end of the electrically insulating beam. A heat sink terminal is formed on the electrically insulating beam adjacent a second end of the electrically insulating beam. In some embodiments, the thin-film component has an area power capacity of greater than about 0.17 W/mm2 at about 28 GHz.

Abstract: The disclosure provides a low-cost near-hermetic package, which may a substrate configured to support one or more internal components. The package may also include an enclosure comprising a cavity surrounding the one or more internal components and a first sidewall extending upward from the substrate. The first sidewall may be coupled to the substrate. The package may further include a first flexible circuit comprising conductive traces configured to connect to the one or more internal components. The first flexible circuit may include a first section outside the first sidewall of the enclosure, a second section inside the enclosure, and a third section between the first section and the second section joining to the enclosure and the substrate.

Abstract: [Object] A method for efficiently manufacturing chip resistors is provided. [Means] The method includes the steps of preparing at least three conductive elongated boards 711 made of an electrically conductive material and a resistive member 702 made of a resistive material, arranging the at least three conductive elongated boards 711 apart from each other along a width direction crossing a longitudinal direction in which one of the at least three conductive elongated boards 711 is elongated, forming a resistor aggregate 703 by bonding the resistive member 702 to the at least three conductive elongated boards 711, and collectively dividing the resistor aggregate 703 into a plurality of chip resistors by punching so that each of the chip resistors includes two electrodes and a resistor portion bonded to the two electrodes.

Abstract: Structures and formation methods of a semiconductor device structure are provided. A method for forming a semiconductor device structure includes forming a first patterned conductive layer. The method also includes forming a dielectric layer covering the first conductive layer. The method further includes forming a conductive via in the dielectric layer. In addition, the method includes forming a resistor layer and a protection layer over the dielectric layer. The method also includes patterning the protection layer to form a protection feature and patterning the resistor layer to form a resistor feature overlapping the first conductive layer. The resistor feature is electrically connected to the first conductive layer through the conductive via. The method further includes forming a second conductive layer over the dielectric layer. The top surface of the resistor feature maintains covered by the protection feature during the formation of the second conductive layer.

Abstract: A resistive device includes a resistive layer, a flexible substrate arranged on the resistive layer, and an electrode layer. The electrode layer includes two electrode sections arranged below the resistive layer and separate to each other. Moreover, a method for manufacturing the resistive device with flexible substrate is also disclosed.

Abstract: [Object] To provide a chip resistor with which laser irradiation requires no extremely high positional accuracy, and a plating layer provided on a base and adjacent to a resistor element can be connected to an external conductive layer. [Solution] A chip resistor includes a base 1, a first principal surface electrode 21, a second principal surface electrode spaced apart from the first principal surface electrode 21 in a first direction X1, a resistor element 4 in contact with the first principal surface electrode 21 and the second principal surface electrode 31, an overcoat 6 covering the resistor element 4, the first principal surface electrode 21 and the second principal surface electrode, a first auxiliary electrode 25 covering the first principal surface electrode 21 and the overcoat 6, and a first plating electrode 27 covering the first auxiliary electrode 25. The first auxiliary electrode 25 includes a portion 259 offset from the first principal surface electrode 21 in the first direction X1.

Abstract: A resistor device includes a resistor plate having opposite first and second surfaces; a first metal layer including first and second portions which are disposed on the first surface of the resistor plate at opposite first and second sides, respectively; and a second metal layer including a first sensing pad, a second sensing pad, a first current pad and a second current pad, separate from one another, wherein the first sensing pad and the first current pad are disposed on the first portion of the first metal layer and the second sensing pad and the second current pad are disposed on the second portion of the first metal layer. A protective layer is preferably provided, overlying the resistor plate and the first metal layer uncovered by the second metal layer.

Abstract: A resistor device includes a resistor plate and an electrode structure. The electrode structure includes an electrode layer and an auxiliary layer. The electrode layer is disposed at a first face of the resistor plate and includes a first portion and a second portion overlying a first side and a second side of the resistor plate, respectively, and a current path is conducted between the first portion and the second portion through the resistor plate. The auxiliary layer is disposed at a second face of the resistor plate and includes at least a first block and a second block overlying the first side of the resistor plate, and at least a third block overlying the second side of the resistor plate, wherein the first, second and third blocks of the auxiliary layer are separated from one another so that any current flow among the blocks is blocked.

Abstract: [Object] A method for efficiently manufacturing chip resistors is provided. [Means] The method includes the steps of preparing at least three conductive elongated boards 711 made of an electrically conductive material and a resistive member 702 made of a resistive material, arranging the at least three conductive elongated boards 711 apart from each other along a width direction crossing a longitudinal direction in which one of the at least three conductive elongated boards 711 is elongated, forming a resistor aggregate 703 by bonding the resistive member 702 to the at least three conductive elongated boards 711, and collectively dividing the resistor aggregate 703 into a plurality of chip resistors by punching so that each of the chip resistors includes two electrodes and a resistor portion bonded to the two electrodes.

Abstract: A resistance element that includes a resistor made of a thin film containing VO2 as a main component and at least one of W, Nb, Mo and Ti as an additive element. The thin film has a plurality of layer regions distributed in the direction of thickness thereof, and amounts of the additive elements doped in the layer regions are different from each other between the adjacent layer regions. Terminal electrodes are disposed such that a current flows through the plural layer regions of the resistor. Preferably, an interval at which the plural layer regions are distributed is selected to be not less than 8 nm and not more than 35 nm.

Abstract: An RF power resistor includes: a lossy layer; and a dielectric layer. The lossy layer is shaped and/or sized as a transmission line. The lossy layer is made of a lossy material. The dielectric layer is made of a dielectric material. The lossy layer and the dielectric material are located to be adjacent to each other and in contact with each other.

Abstract: An ultra wideband frequency compensated resistor and related methodologies for frequency compensation are disclosed. In exemplary configuration, a resistive layer is provided over a substrate, and a frequency compensating structure is provided over at least a portion of the resistive layer and separated therefrom by an insulative layer. In certain embodiments, the insulating layer may be an adhesive that may also be effective to secure a protective cover over the resistive material and supporting substrate. In selected embodiments, the frequency compensating structure corresponds to a plurality of conductive layers, one or more of which may be directly electrically connected to terminations for the resistive material while one or more of the conductive layers are not so connected.

Abstract: A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.

Abstract: An ultra wideband frequency compensated resistor and related methodologies for frequency compensation are disclosed. In exemplary configuration, a resistive layer is provided over a substrate, and a frequency compensating structure is provided over at least a portion of the resistive layer and separated therefrom by an insulative layer. In certain embodiments, the insulating layer may be an adhesive that may also be effective to secure a protective cover over the resistive material and supporting substrate. In selected embodiments, the frequency compensating structure corresponds to a plurality of conductive layers, one or more of which may be directly electrically connected to terminations for the resistive material while one or more of the conductive layers are not so connected.

Abstract: A nanoflat resistor includes a first aluminum electrode (360), a second aluminum electrode (370); andnanoporous alumina (365) separating the first and second aluminum electrodes (360, 370). A substantially planar resistor layer (330) overlies the first and second aluminum electrodes (360, 370) and nanoporous alumina (365). Electrical current passes from the first aluminum electrode (360), through a portion of the planar resistor layer (350) overlying the nanoporous alumina (365) and into the second aluminum electrode (370). A method for constructing a nanoflat resistor (390) is also provided.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, respectively forming a transistor having a dummy gate in the transistor region and a resistor in the resistor region, removing the dummy gate and portions of the resistor to form a first trench in the transistor and two second trenches in the resistor, forming at least a high-k gate dielectric layer in the first trench and the second trenches, and forming a metal gate in the first trench and metal structures respectively in the second trenches.

Abstract: There are provided a resistor and a method of fabricating the same. The resistor includes: a substrate; a lower resistant material layer formed on the upper portion of the substrate; an insulating layer to be stacked on the upper portion of the lower resistant material layer; an upper resistant material layer to be stacked on the upper portion of the insulating layer; and two penetration parts vertically penetrating through the insulating layer, wherein the penetration part is filled with a resistant material having the same component as that of the lower resistant material layer and the upper resistant material layer to electrically connect the upper resistant material layer to the lower resistant material layer.

Abstract: A substrate device includes a layer of non-linear resistive transient protective material and a plurality of conductive elements that form part of a conductive layer. The conductive elements include a pair of electrodes that are spaced by a gap, but which electrically interconnect when the transient protective material is conductive. The substrate includes features to linearize a transient electrical path that is formed across the gap.

Abstract: The present invention relates to a laminate thermistor device comprising a lead terminal 12 connected to a terminal electrode 10. A device main body 4 is a rectangular parallelepiped having mutually perpendicular first side 4a, second side 4b and third side 4c, and when a length of the first side is ?, a length of the second side is ? and a length of the third side is ?, the length of each side ?, ? and ? satisfies a relation of ???>?. The terminal electrodes 10 are respectively formed on two plane surfaces including the first side 4a and second side 4b, and the lead terminals 12 are connected to the terminal electrodes 10 respectively to sandwich the third side 4c of the device main body 4 in a length direction therebetween.

Abstract: A resistor device includes a resistor plate and an electrode structure. The electrode structure includes an electrode layer and an auxiliary layer. The electrode layer is disposed at a first face of the resistor plate and includes a first portion and a second portion overlying a first side and a second side of the resistor plate, respectively, and a current path is conducted between the first portion and the second portion through the resistor plate. The auxiliary layer is disposed at a second face of the resistor plate and includes at least a first block and a second block overlying the first side of the resistor plate, and at least a third block overlying the second side of the resistor plate, wherein the first, second and third blocks of the auxiliary layer are separated from one another so that any current flow among the blocks is blocked.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: A chip-like electric component such as a chip resistor is provided, which is easy to manufacture and in which cracks or fractures of an insulating substrate are unlikely to occur. A pair of surface electrodes 21, 23 are formed so that thicknesses of the pair of surface electrodes increase from a resistor layer 13 toward end portions 30 of an insulating substrate 29 in a direction in which the pair of surface electrodes 21, 23 are arranged. A plating reservoir S is formed between one of the surface electrodes 21, 23 and an insulating protective layer 15. When forming at least one plated layer 33, a plated metal pools in the plating reservoir S. The at least one plated layer 33 may work to reduce to some extent a height difference between a soldering electrode portion 21, 23, 27, 33 and the insulating protective layer 15.

Abstract: A resistor device includes a resistor plate having a first aperture, a second aperture, a third aperture and a fourth aperture respectively arranged on a first side, a second side, a third side and a fourth side thereof. A first electrode plate is coupled to the first side of the resistor plate and includes a first measurement zone and a second measurement zone disposed at opposite sides of the first aperture; and a second electrode plate is coupled to the third side of the resistor plate and including a third measurement zone and a fourth measurement zone disposed at opposite sides of the third aperture, wherein the first measurement zone and the third measurement zone are disposed at opposite sides of the second aperture, and the second measurement zone and the fourth measurement zone are disposed at opposite sides of the fourth aperture.

Abstract: A nanoflat resistor includes a first aluminum electrode (360), a second aluminum electrode (370); and nanoporous alumina (365) separating the first and second aluminum electrodes (360, 370). A substantially planar resistor layer (330) overlies the first and second aluminum electrodes (360, 370) and nanoporous alumina (365). Electrical current passes from the first aluminum electrode (360), through a portion of the planar resistor layer (350) overlying the nanoporous alumina (365) and into the second aluminum electrode (370). A method for constructing a nanoflat resistor (390) is also provided.

Abstract: There are provided a resistor and a method of fabricating the same. More particularly, there are provided a resistor having a parallel structure capable of easily implementing a resistance value when forming a resistor directly on a wafer during a wafer process, and a method of fabricating the same. The resistor includes: a substrate; a lower resistant material layer formed on the upper portion of the substrate; an insulating layer to be stacked on the upper portion of the lower resistant material layer; an upper resistant material layer to be stacked on the upper portion of the insulating layer; and two penetration parts vertically penetrating through the insulating layer, wherein the penetration part is filled with a resistant material having the same component as that of the lower resistant material layer and the upper resistant material layer to electrically connect the upper resistant material layer to the lower resistant material layer.

Abstract: An RF terminating resistor with a flange body, a planar layer structure, an upper face of a substrate, a resistance layer, an input conductor track, and an earth connection conductor track. The input conductor track electrically connected to opposite ends of the resistance layer. The substrate having a contact face, facing away from the layer structure. The flange body being bent around in a direction parallel to a first edge facing the earth conductor track, and a predetermined section bent around in a direction at right angles to this edge. The bent-around section extending in a space between a first plane, defined by the contact face, and a second plane, defined by the upper face, with the substrate abutting on the bent-around section connecting the contact face to the upper face and facing the earth connection conductor track on the upper face.

Abstract: In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate 10 including an integrated circuit 12 having a plurality of electrode pads 14 placed in a distance from each other in the most upper part of a plurality of stacked interconnections, and the integrated circuit 12 having a passivation film 16 formed between the plurality of electrode pads 14; a secondary interconnections 18 electrically connected to the electrode pads 14; an insulating film 20 formed in a place in between the secondary interconnections 18 on the passivation film 16; and a resistor 26 formed 18 in a predetermined place in between the secondary interconnections 18 on the insulating film 20.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: Methods of forming a layered heater are provided that comprise at least one resistive layer comprising a resistive circuit pattern, the resistive circuit pattern defining a length, a thickness, and a spacing, wherein the thickness varies along the length of the trace of the resistive circuit pattern for a variable watt density. The methods include achieving the variable thickness by varying a dispensing rate of a conductive ink used to form the resistive circuit pattern, varying the feed rate of a target surface relative to the dispensing of the ink, and overwriting a volume of conductive ink on top of a previously formed trace of the resistive circuit pattern.

Abstract: A ceramic heater includes a core material and a ceramic sheet covering the core material, and wherein a side of the ceramic sheet opposite the core material is an outer side of the ceramic heater. A method for manufacturing the ceramic heater includes forming a through hole in a ceramic sheet which is diametrically enlarged from a first surface toward a second surface of the ceramic sheet, forming a via conductor, forming on the second surface a heating portion and lead portion for connecting the heating portion and the via conductor, and covering a core material with the ceramic sheet such that the first surface faces an outer side of the ceramic heater.

Abstract: The present invention relates to an adjustable resistor embedded in a circuit board and a method of fabricating the same. The adjustable resistor comprises a resistor with a number of connection terminals, and a number of via holes extending to contact with the resistor. The resistive value of the resistor is variable depending on the size of the via holes, the number of the via holes, or the distance between the via holes.

Abstract: A resistor device includes a resistor plate having a first aperture, a second aperture, a third aperture and a fourth aperture respectively arranged on a first side, a second side, a third side and a fourth side thereof. A first electrode plate is coupled to the first side of the resistor plate and includes a first measurement zone and a second measurement zone disposed at opposite sides of the first aperture; and a second electrode plate is coupled to the third side of the resistor plate and including a third measurement zone and a fourth measurement zone disposed at opposite sides of the third aperture, wherein the first measurement zone and the third measurement zone are disposed at opposite sides of the second aperture, and the second measurement zone and the fourth measurement zone are disposed at opposite sides of the fourth aperture.

Abstract: An electrical structure. The electrical structure includes a resistor having a length L and an electrical resistance R(t) at a time t; and a laser radiation directed onto a portion of the resistor, wherein the portion of the resistor includes a fraction F of the length L, wherein the laser radiation heats the portion of the resistor such that the electrical resistance R(t) instantaneously changes at a rate dR/dt, and wherein the resistor is coupled to a semiconductor substrate.

Abstract: The chip resistor (1) includes an insulating substrate (2) and a main upper electrode (4) formed on a main surface of the insulating substrate (2). On the main surface of the insulating substrate (2), a resistor film (5) including an end (5a) overlapping the upper surface of main upper electrode (4) is formed. The resistor film (5) is covered by a protective coat (7, 8). An auxiliary upper electrode (6) is formed on the upper surface of the main upper electrode (4). The auxiliary upper electrode (6) includes an inner end (6a) overlapping the upper surface of the end (5a) of the resistor film (5). The protective coat (7, 8) overlaps the inner end (6a) of the auxiliary upper electrode (6).

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 ?m to about 20 ?m. The insulative layer has a substantially constant thickness.

Abstract: Embodiments of a resistor are disclosed.

Abstract: A substrate device includes a layer of non-linear resistive transient protective material and a plurality of conductive elements that form part of a conductive layer. The conductive elements include a pair of electrodes that are spaced by a gap, but which electrically interconnect when the transient protective material is conductive. The substrate includes features to linearize a transient electrical path that is formed across the gap.

Abstract: An RF terminating resistor with a flange body, a planar layer structure, an upper face of a substrate, a resistance layer, an input conductor track, and an earth connection conductor track. The input conductor track electrically connected to opposite ends of the resistance layer. The substrate having a contact face, facing away from the layer structure. The flange body being bent around in a direction parallel to a first edge facing the earth conductor track, and a predetermined section bent around in a direction at right angles to this edge. The bent-around section extending in a space between a first plane, defined by the contact face, and a second plane, defined by the upper face, with the substrate abutting on the bent-around section connecting the contact face to the upper face and facing the earth connection conductor track on the upper face.

Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.

Abstract: A chip-type component 11 includes an insulating chip substrate 12 whose upper surface is provided with a resistor element 13 and a cover coat 14 covering the resister film. At the opposite ends of the substrate, terminal electrode films 15, 16 are formed for the resistor element in a manner such that they extend onto the lower surface 12a of the insulating substrate. The lower surface 12a of the substrate is provided with an insulating projection 18 between the terminal electrode films, where the projection includes a peak portion 18a positioned at or near the center of the insulating substrate in a longitudinal direction along which the terminal electrode films are spaced from each other. This prevents the insulating substrate from breaking when the chip-type component 11 is vacuum-sucked by a collet nozzle 19 to be supplied to a printed circuit board 17.

Abstract: A chip resistor includes a resistor element, a reinforcing member, and a pair of electrodes. The resistor element includes a first surface and a second surface opposite to the first surface. The reinforcing member is bonded to the first surface of the resistor element. The pair of electrodes are formed on the second surface of the resistor element. The resistor element is formed with a slit located between the pair of electrodes.

Abstract: In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate 10 including an integrated circuit 12 having a plurality of electrode pads 14 placed in a distance from each other in the most upper part of a plurality of stacked interconnections, and the integrated circuit 12 having a passivation film 16 formed between the plurality of electrode pads 14; a secondary interconnections 18 electrically connected to the electrode pads 14; an insulating film 20 formed in a place in between the secondary interconnections on the passivation film 16; and a resistor 26 formed 18 in a predetermined place in between the secondary interconnections 18 on the insulating film 20.

Abstract: A first voltage variable material (“VVM”) includes an insulative binder, first conductive particles with a core and a shell held in the insulating binder and second conductive particles without a shell held in the insulating binder; a second VVM includes an insulating binder, first conductive particles with a core and a shell held in the insulating binder, second conductive particles without a shell held in the insulating binder, and semiconductive particles with a core and a shell held in the insulating binder; a third VVM includes only first conductive particles with a core and a shell held in the insulating binder.

Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

Abstract: The present invention provides a novel method for electrical connection between a polymer PTC device and a metal lead element to thereby prevent the problems of the connection by caulking or soldering. For this purpose, the present invention provides a process for producing a connection structure by laser welding, said connection structure having (A) a PTC device (10) including (i) a laminar polymer PTC element (12) and (ii) a metal foil electrode (14) disposed on a main surface of the laminar polymer PTC element (12), and (B) a metal lead element (20) electrically connected to the metal foil electrode. The metal foil electrode (14) has at least two metal layers, one of which, the X-th layer, has laser beam absorption a % that is the lowest among the metal layers of the metal foil electrode (14). The X-th layer is present between a first metal layer (18) of the metal foil electrode and the laminar polymer PTC element (12).

Abstract: Methods of assembling a high heat transfer and tailored heat transfer layered heater systems are provided. One method includes a step of pressing one of a target part and a layered heater into the other one of the target part and the layered heater to create an interference fit between the layered heater and the target part. When the target part is disposed within the layered heater, the layered heater includes a substrate defining an inner periphery less than or equal to an outer periphery of the target part. When the layered heater is disposed within the target part, the layered heater includes a substrate defining an outer periphery larger than or equal to an inner periphery of the target.

Abstract: A process for manufacturing a composite polymeric circuit protection device in which a polymeric assembly is provided and is then subdivided into individual devices. The assembly is made by providing first and second laminates, each of which includes a laminar polymer element having at least one conductive surface, providing a pattern on at least one of the conductive surfaces on one laminate, securing the laminates in a stack in a desired configuration, at least one conductive surface of at least one of the laminates forming an external conductive surface of the stack, and making a plurality of electrical connections between a conductive surface of the first laminate and a conductive surface of the second laminate. The laminar polymer elements may be PTC conductive polymer compositions, so that the individual devices made by the process exhibit PTC behavior.

Abstract: A method of manufacturing a PTC element comprising a pair of lead terminals bonded together by thermocompression with a matrix held therebetween comprises a matrix preparing step of preparing a matrix constructed by dispersing a conductive filler into a crystalline polymer; a terminal preparing step of preparing a pair of lead terminals holding the matrix therebetween, a surface of each lead terminal facing the matrix being formed with a plurality of anchor protrusions separated from each other; a flattening step of flattening the anchor protrusions formed in respective nonoverlapping areas in the pair of lead terminals kept from overlapping the matrix; and a thermocompression bonding step of holding the matrix between respective overlapping areas in the pair of lead terminals overlapping the matrix, and securing the pair of lead terminals and the matrix together by thermocompression bonding.