Abstract: A receiver gain tracking loop utilizing two Digital-to-Analog Converters (DACs) and methods for operating the gain tracking loop are provided. The gain tracking circuit includes a signal detector for detecting at least one signal and outputting a detected signal; a digital integrator connected in series to the signal detector for integrating the detected signal in the digital domain; two DACs connected in parallel to the digital integrator; and an analog summing element for summing the first digital output and the second digital output of the DACs producing a combined output.

Abstract: System and method of demodulation by adapting constellation values based on statistic distributions of received data symbols. To determine an adapted constellation, an expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. For a set of received symbols, a count ratio of symbols falling in a first range to all the symbols in the set is compared with the expected ratio, where the first range is defined as below a first value. The first value is repeatedly adjusted to adjust the first range until the count ratio equals the expected ratio. The final first value is then designated as the optimal adapted constellation.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present invention relates to a method and a device for efficiently shortening and puncturing a non-binary LDPC code, the method for a transmitter shortening and puncturing a non-binary code being capable of supporting various modulation methods by using a single non-binary code, and the method comprising the steps of: shortening, on the basis of a modulation method, at least one information bit in at least one information symbol constituting the non-binary code; encoding the at least one information symbol having a shortened information bit; and puncturing, on the basis of the modulation method, at least one parity code in at least one parity symbol obtained through the encoding step.

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: In a serial communication control circuit, serial data transmitted from a transmission processing unit is switched to data generated in a mark ratio improvement data generation unit depending on a switch signal from the transmission processing unit, and is transmitted. Thereby, mark ratio improvement data is inserted in a transmission signal to improve a mark ratio during communication, thereby preventing reception signal's jitters from increasing.

Abstract: An imaging apparatus and a method of driving the same that can generate a digital data of a high resolution pixel signal are provided. The imaging apparatus includes: a pixel (10-1) for generating a signal by photoelectric conversion; a comparing circuit (30-1) for comparing a signal based on the pixel with a time-dependent reference signal; a counter circuit (40-1) performing a counting operating until an inversion of a magnitude relation between the signal based on the pixel and the time-dependent reference signal; and a selecting circuit (30-2) for setting a time-dependent change rate of the reference signal, according to a signal level of the signal based on the pixel.

Abstract: Data compression is described herein. The encoder transmits a coded word having replacement bits, as well as a code that defines the starting location of the replacement bits in a data sample. The replacement bits may be actual bits from a selected location in the new data sample. The selected location of the replacement bits can vary from data sample to data sample. The encoder may select the location based on the most significant bit that has changed. Thus, reconstructed data will be bit-accurate from the replaced bits all the way to the highest-order bit. A limited number of key values can be transmitted losslessly. Moreover, the data compression does not need forward error correction (FEC), which is a necessary part of many lossy delta encoding schemes. Furthermore, the encoding and decoding can be done very efficiently in terms of hardware and/or software.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: Embodiments of the invention relate to a method, apparatus and computer readable storage medium wherein the method comprises; padding a data block of a data structure to enable encoding of the data block; encoding the data block; reducing the size of the encoded data block; and spreading the data block.

Abstract: Systems, methods, and other embodiments associated with an encoder. In one embodiment, a system includes an encoder having a code word generator and an appending logic. The code word generator is configured to generate code words based on input data and identify one or more short code words. A short code word has a length less than a length of a full code word. The appending logic is configured to append at least one dummy value to at least one of the short code words to convert the at least one short code word to a full code word. The encoder may further be configured to encode the converted full code word and store the converted full code word without the at least one dummy value in a storage medium.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: A code mapping method includes: providing M bits of digital input codes; checking the 1st bit of the M bits to generate a checking result; determining whether to perform 2's compliment operation on the 2nd to Mth bits according to the checking result; and converting the 1st to Nth bits of the M bits into P bits according to a designated mapping manner.

Abstract: A method and apparatus to compress a DVB-ASI bit stream including accepting the stream containing packets of compressed media, sync words, and stuffing words, identifying starts of packets, identifying and discarding stuffing words; and adding information to form a compressed stream, added information sufficient to reconstruct a reconstructed stream from the compressed stream, with the relative locations of starts of packets in the reconstructed bit stream matching the relative locations of starts of corresponding packets in the accepted stream. Also a method recover the timing of MPEG packets including accepting a serial bit stream containing packets of compressed media streams, and ascertaining if the stream includes information indicating that the bit stream has a DVB-ASI form with stuffing words discarded and with indicating information added.

Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: A network device comprises a data translator that receives a first data stream at a first data rate and that includes a data sampler that selects one of X data symbols that are received, wherein the one of the X data symbols includes (M+N) bits, and that outputs a second data stream at a second data rate and a data remover that removes N of the (M+N) bits and that outputs a third data stream including symbols with the M bits at a third data rate. A physical layer device receives the third data stream.

Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A method that employs a piecewise linear algorithm, P, to map m-dimensional symbols into code tuples, followed by the construction of codes of weight m from the code tuples. To reverse the operation, constant weight codes are converted to code tuples, and a reverse piecewise linear algorithm P? is used to map the code tuples into symbols, from which data is recovered. The m-dimensional symbols are obtained from mapping of input data into the symbols, which are contained within an m-dimensional parallelopiped, with each coordinate having a different span but the symbols along each of the coordinate are equally spaced apart. The code tuples, which are obtained by employing process P, are contained within an m-dimensional simplex.

Abstract: The present invention relates to the field of wireless communications and discloses wireless signal transmission and reception methods and devices, thus more information can be transmitted via a fixed resource block. In the present invention, at the transmitter side, information for transmission is divided into an n-bit part and an m-bit part, the n-bit part being taken as information borne in a physical resource and a corresponding mapping mode is selected in accordance with the m-bit part; at the receiver side, a sequence carrying a received signal is de-mapped according to all possible mapping modes of the received signal and transmitted information is derived from an optimum signal sequence resulting from de-mapping and corresponding mapping mode.

Abstract: A system comprising a control logic that generates a code having n digits, a translation logic coupled to the control logic that translates the code to a new code having greater than n digits, and a variable resistance logic coupled to the translation logic and comprising greater than n semiconductor devices. A resistance associated with the variable resistance logic depends on activation statuses of the semiconductor devices. The translation logic adjusts at least some of the semiconductor devices in accordance with the new code.

Abstract: Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream.

Abstract: A data converter (10) for digitizing an analog input signal and providing digital output data at one or more conversion cycles includes a logic circuit (28) for generating a data conversion diagnostic bit (38) having first and second logical states. The data conversion diagnostic bit toggles from one logical state to the other logical state when a conversion cycle is completed and when the digital output data from the previous conversion cycle has been read. The data conversion diagnostic bit remains at the same logical state when no conversion cycle has been completed or when no reading of the digital output data has been carried out.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A system and method for communicating includes a transmitter that transmits a communication signal having a plurality of successive frames, with each frame formed with alternatively arranged N known data symbols and M unknown data symbols such that the N known data symbols as training symbols. The communications signals are received within a receiver. The N known data symbols are synchronized at the receiver by correlating and time averaging the N known data symbols.

Abstract: A system and method for converting analog signals to digital signals minimize the latency of the analog to digital conversion for real-time systems. The conversion system and method implements the hardware of an analog to digital converter input/output (I/O) board and a software-based I/O-driver in an expansion bus. The hardware of the ADC I/O board executes free-running conversion of an analog signal into digital form and stores the converted values in a first level of a buffer having two levels. Previously stored converted values are pushed to the second level of the buffer when a new value is written to the first level. The I/O driver then retrieves stored values from the second level of the buffer when needed by the real-time system and gates the buffer to prevent pushing during retrieval of values from the second level.

Abstract: ACARS systems and methods for compiling messages includes a processing device configured for mapping eight-bit characters in an eight-bit character stream into a six bit map to create a generally six-bit character stream. The processing device is further configured for encoding the generally six-bit character stream into an eight-bit character stream. Optionally, the processing device includes a look-up table configured to retrieve substituted six-bit characters in response to the presence of the eight-bit character received at a processor.

Abstract: A method for communication between a sender and a receiver, including receiving data in the form of an M-of-N code, where the M-of-N code includes a first component of length n1 and a second component of length n2; decoding data in which the first component is an m1-of-n1 code and the second component is an m2-of-n2 code; and decoding data in which the first component is an m3-of-n1 code where m1?m3 and the second component is an m4-of-n2 code where m2?m4.

Abstract: A dual mode decoder which includes an MB810 decoder; an 8B/10B decoder; a mode detection unit, a first low pass filter; a second low pass filter; an IDLE code detection unit which detects IDLE code and transfers to the mode detection unit; a first switch unit which selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input form the decoder determined as the operation decoder.

Abstract: A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function (where M>N) by a (2**N) ×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.

Abstract: An MB810 encoder and/or decoder, dual mode encoder and/or decoder, and a method for generating MB810 codes are provided. Twelve state points in the form of a 4×3 matrix on a state transition map are formed with binary unit digital sum variation & alternate sum variation (BUDA). A 10-bit code from 8-bit data is generated outputting a 10-bit code from a predetermined state point to form the matrix. Codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix are selected. Codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair are selected. Control codes including IDLE code from the codes forming the 12 state points are selected. Codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points are removed.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A serial concatenated coder includes an outer coder and an inner coder. The outer coder irregularly repeats bits in a data block according to a degree profile and scrambles the repeated bits. The scrambled and repeated bits are input to an inner coder, which has a rate substantially close to one.

Abstract: Disclosed are a method and device of converting data words into code words. This method inserts 2p p guided bits before inputting each set of data words, performs a pre-defined operation, and generates 2p data sequences with different guided bits. It chooses q data sequences from the 2p data sequences for coding, performs a run length limited (RLL) coding with a coding rate m/n, and generates q (d, k) constrained code word sequences. Finally, an optimal (d, k) constrained code word sequence is selected from the q (d, k) constrained code word sequences. The device reduces the circuitry of the RLL coding applied guided scrambling without losing the control of direct current and low frequency components.

Abstract: In a data arrangement of a CD-ROM format, data in which DSV control data cannot be placed due to a restriction on the format is followed by control data of two bytes. Main data in which any data cannot be placed is followed by a special control data sequence of two bytes. As a result, after a data sequence of which it is unknown whether the start bit is plus or minus, the sign of the start bit of a diverging control data sequence preceded by the special control data sequence can be kept constant. Consequently, DSV values can be deviated in one direction.

Abstract: A method of generating an 8B/10B-like code bit sequence that is similar to an 8B/10B code may include: generating a parallel pseudo random bit sequence having N bits wherein N is an integer and N?2; and transforming the parallel pseudo random bit sequence into a parallel first bit sequence that is similar to an 8B/10B code, a number Q of consecutive “0”s or “1”s of the first bit sequence being Q?M1, wherein Q and M1 are integers and M<N. Devices related to such a method are also provided.

Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: Input and output sections of an analog-to-digital converter are joined by an interface. In the input section, an analog input signal is converted to a multi-bit digital signal before being converted, by a noise-shaping converter such as a sigma-delta modulator, to a lower bit signal. The lower bit signal is carried across the interface before being converted, by a digital filter to recover the original multi-bit signal. The same principle is applied to the input and output sections of a digital-to-analog converter.

Abstract: A succession of input data words is converted into a first succession of information code words including first candidate one and a second succession of information code words including second candidate one different from first candidate one. One is selected from the first succession of information code words and the second succession of information code words as a final succession of information code words in a manner such that the absolute value of a DSV relating to the final information-code-word succession will be smaller. Check bits are generated in response to the final information-code-word succession and a predetermined parity generation matrix of LDPC encoding. The check bits are changed to conversion code words. The final information-code-word succession and the conversion code words are combined into an output-code-word sequence which obeys (1, k) RLL, where “k” is a predetermined natural number in the range of 9 to 12.

Abstract: A system provides two distinct solutions for encoding and decoding servo positioning data for a hard disk drive. A first solution includes: encoding each group of four bits of a pattern signal in a Matched Spectral Null (MSN) format through an intermediate rate 4/6 code; providing a duplicated bit for each bit of the six bit code word obtained with the previous step. A second solution includes: encoding each group of four bit of the pattern signal adding a parity check bit as an intermediate rate ? code; encoding each of the five bits using the biphase map. Both solutions include subsequently: reading a servo wedge information signal using a read and write channel of the hard disk drive; and using a trellis Partial Response decoding scheme matched to the encoded word for obtaining angular and radial information for the head positioning.

Abstract: An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word to obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.

Abstract: Embodiments of the present invention mitigate crosstalk by equalizing transmit signals in a data dependent fashion.

Abstract: A method of encoding digital information in order to suppress dc includes the steps of receiving a sequence of m message bits of a message word, and mapping the sequence of m message bits of the message word to a codeword, of length n bits, generated from the m message bits using algebraic operations. Multiple codeword candidates are generated from the m message bits using the algebraic operations to combine the m message bits with different periodic scrambling sequences. One of the codeword candidates is selected for mapping based upon an optimizing criteria. Second order digital sum sequences, corresponding to each of the plurality of codeword candidates, can be used as the optimizing criteria to select the codeword.

Abstract: When converting an analog signal to N-bit digital codes, high SNR (signal to noise ratio) by generating multiple N-bit codes from the same analog sample and averaging the N-bit codes. However, the entire N-bit code is determined only a single time, and only P-bit (P less than N) codes are generated. The P-bit codes may be averaged, and the N-bit code is corrected based on the average value to generate an accurate N-bit digital code. As P can be much less than N, the correction can be implemented in a few iterations, thereby enabling the ADCs to be implemented with a high throughput performance. Due to the correction, a high SNR may be attained as well.