Abstract: A method of coding data for communication within a network. The method includes receiving an 8b/10b source protocol data stream containing 10-bit code and translating the data stream into an 8-bit code by converting the 10-bit code into 8-bit data and an ordered set. The method further includes transmitting the 8-bit code.

Abstract: A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: This invention relates to a digital modulation method and apparatus used for recording an audio or video signal, computer data, and etc on a recording medium such as an optical or magneto-optical disc. Data words of m bits are translated into code words of n bits in accordance with a conversion table. The code words satisfy a (d, k) constraint in which at least d “0”s and not more than k “0”s occur between consecutive “1”s. The n-bit code words alternate with p-bit merging words which are selected such that between the leading “1” in the code word following the merging word and the trailing “1” in the merging word are at least d “0”s, and further that between the trailing “1” in the code word preceding the merging word and the leading “1” in the merging word are at least d “0”s.

Abstract: Each input binary digit of an input serial bit string having a referential word in a referential word time period is sampled N times to produce a plurality of over-sampled binary digits corresponding to a first group of sampling operations, a second group of sampling operations,--, an N-th group of sampling operations, and the over-sampled binary digits are divided to N divided bit strings corresponding to the N groups of sampling operations respectively. Because each divided bit string having the referential word is correctly sampled at high probability, a word start position of the referential word in each divided bit string is detected, one divided bit string correctly sampled at the highest probability is selected, and a string of words starting from the word start position is retrieved from the selected divided bit string and is output.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (N−1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.

Abstract: A data transmission system (100) may include a transmitting portion (102) and a receiving portion (104). A transmitting portion (102) may include an encoder (106) that may encode data values of n bits into codes of m bits, where n is less than m. Codes may be transmitted with corresponding clock values. The absolute value of the DC component of a code summed with a corresponding clock value can be no more tan one for all code values.

Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y1, y2, y3) in accordance with a conversion of the Jacoby type, where m and n are integers, with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: An optical transmission system and optical transmission devices in the optical transmission system that can achieve a high quality transmission using considerably simple arrangements are disclosed. At a transmitting-end optical transmission device, encoding means having n outputs, forms k data by aligning phases of data on k channels with each other and for generating (n−k) error correction bits for said k data and adding said (n−k) error correction bits to said k data, and wavelength-multiplexing means connected to the encoding means, converts both said k data and said (n−k) error correction bits ton optical signals having different wavelengths and for wavelength-multiplexing said n optical signals so as to be delivered to the optical transmission line.

Abstract: Described is a scalable interface including a plurality of 2-bit transmission channels. An encoder partitions a digital bit stream into 3 bits which are coded into 4 bits with each pair of bits in each 4 bit pattern transmitted via back-to-back clock cycles on separate ones of the channels.

Abstract: Described is a scalable interface including a plurality of 2-bit transmission channels. An encoder partitions a digital bit stream into 3 bits which are coded into 4 bits with each pair of bits in each 4 bit pattern transmitted via back-to-back clock cycles on separate ones of the channels.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: A method of coding data for communication within a network. The method includes receiving an 8b/10b source protocol data stream containing 10-bit code and translating the data stream into an 8-bit code by converting the 10-bit code into 8-bit data and an ordered set. The method further includes transmitting the 8-bit code.

Abstract: An encoder encodes a stream of date-bits of a binary source signal into a stream of date-bits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words. The encoder includes a converter for converting the source words into corresponding m-bit channel words. The converter converts n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity inverting. The relations hold that m>n≧1, p≧1, and that p is an odd integer that can vary. Preferably, m=n+1. A decoder decodes the channel signal, obtained by means of the encoder, to reproduce the source signal.

Abstract: An improved thermometer-to-binary coder in which the bits of the thermometer code are used to directly generate the binary code without using an intermediate one-hot code.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the stream of databits of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y1, y2, y3) in accordance with a conversion of the Jacoby type, where m and n are integers, with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word o obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.

Abstract: A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Abstract: A method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, a device for encoding, a signal, a record carrier, a method for decoding, and a device for decoding. The signal is constructed by repetitively or alternately using channel codes C1 and C2. Since two channel words with opposite parities are available in the channel code C2 for each information word, and the same state is established, predetermined properties of the constrained binary channel signal can be influenced. Since the method further comprises the step of substituting, in dependence upon a value of a predetermined property of the binary channel signal, a channel word for a substitute channel word, wherein the substituted channel word and the substitute channel word establish the same state, predetermined properties of the constrained binary channel signal can be further influenced.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.

Abstract: Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (N−1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.

Abstract: A PWM power amplifier having at least one PCM/PWM converter fed by PCM digital input signals and producing PWM digital output signals, and at least one power amplification final stage of the PWM digital output signals. At least one PCM/PWM converterincludes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing in output the PWM digital signals. The clock generator device includes a pulse generator device and an oscillator; the pulse generator device receives a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and produces in output reset pulses. The reset pulses are sent in input to the oscillator, which produces in output the at least one clock signal.

Abstract: A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

Abstract: In transmitting ten-bit word string data including synchronous word data converted, at a transmitting side, from eight-bit word string data, representing signal information data synchronization required for reproducing the signal information is reliably established at a receiving side. An additional word data group containing eight-bit synchronous word data is inserted between words of the eight-bit word string data. Then, 8B-10B conversion is performed on the eight-bit word string data, thereby obtaining ten-bit word string data. In this case, the additional word data group is selected so that a running disparity of the ten-bit synchronous word data contained in the additional word data group of the composite ten-bit synchronous word data is consistently positive or negative.

Abstract: The present invention comprises a number transformer that includes an encoder that converts binary numbers to N-NARY numbers. Within an N-NARY number, exactly one of the bits has a value of one and all of the remaining bits have a value of zero. According to some aspects, several N-NARY numbers are generated in response to a binary number. A set of encoding instance selectors defines a partitioning of the bits of the binary number and a range of bits within each partition. The encoder then converts each subset of bits of the binary number to a corresponding N-NARY number, such that exactly one of the bits of each N-NARY number has a value of one and all of the remaining bits of the N-NARY number have a value of zero, and such that the one of the bits of each N-NARY number having a value of one is within the range of bits defined by the corresponding encoding instance selector. The set of encoding instance selectors may define a test point within a circuit under test, and may be produced by an on-chip ROM.

Abstract: A coding method for converting m-bit input data into n-bit codeword satisfying DC-free and minimum bandwidth characteristics that includes the following: Select the number of input bits m and the number of output bits n for an (m,n) block code. Accumulate a sufficient number of BUDA (binary unit DSV and ASV) cells to form a BUDA stack for derivation of the state diagram. Pick one node as a state, and secure at least 2{circumflex over ( )}m exit paths of an n-hop length, and denote each terminating node of each path as another state. Start with a new state and repeat the previous step. If the stack needs to be expanded to complete the state diagram, add more cells to the stack either horizontally or vertically as appropriate. Reduce the number of states as possible with all transition paths terminating on one of the arranged states. At each state, arrange the mapping table as an input m-bit combination to an output n-bit combination.

Abstract: A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel (C), wherein the stream of databits of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) conceived to convert said n-bit source words into corresponding m-bit channel words (y1, y2, y3) in accordance with a conversion of the Jacoby type, where m and n are integers with m>n. The device further comprises control means (10) for carrying out DC-control on said binary channel signal by introducing a freedom of choice in the source-to-channel conversion. Furthermore, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.

Abstract: The invention relates to a method of converting a binary word IN(0:P−1) into a thermometric signal T1 . . . TN. In accordance with the invention, this method comprises the following steps: conversion of the binary word IN(0:P−1) into an analog signal Vin, and comparison of this analog signal Vin with a plurality of reference signals Vi (i=1 to N). The invention enables to immunize the thermometric signal from parasitic transitions of the binary word IN(0:P−1). Moreover, this method can be carried out using simple structures consuming little energy, which, in addition, do not lead to substantial decoding delays.

Abstract: Satellite identification data generated when using the Reduced Order GPS (ROGPS) system are compressed, allowing for shorter data transmission times, reduced transmitter energy and reduced satellite channel occupancy. An indexed list of all possible constellations of a subset of all satellites is created. This list is then used at both the tracked object location and the central station to which the satellite identifications must be sent. At the tracked object location, the chosen satellite GPS indices are identified and the list index is found, encoded, and transmitted with only enough bits to uniquely identify it from all other indices in the list. At the central station, the received list index is used to find the satellite constellation corresponding to the chosen satellite GPS indices. The number of bits used to encode the index can be further reduced by reducing the indexed list size.

Abstract: A method and apparatus for combining a plurality of 8B/10B encoded DVB-ASI input streams into an aggregate output data stream allows a receiving device to synchronize to the aggregate output data stream by mapping a synchronization character to a unique character if the synchronization character occurs in a first timeslot of the aggregate output data stream. This unique character allows a receiving device to synchronize to the aggregate output data stream. If the synchronization character occurs in a timeslot other than the first timeslot, the synchronization character is mapped to another special character that denotes that no data is present in the timeslot. In addition, if the synchronization character occurs in a timeslot after the last timeslot in which data may be placed in the aggregate output data stream, the synchronization character can be mapped to yet another special character denoting that no data is available in the timeslot.

Abstract: The subtracter performs subtraction processing between a pointer outputted from the pointer register and code words candidate outputted from the code word count storing circuit, and in accordance with whether the result is negative or positive, determines the code words of input data words. Code word candidates stored in the code word count storing circuit are created according to a finite-state transition diagram stored in the state transition storing circuit. An encoder and a decoder are thus made compact and faster.

Abstract: In the transmission of a logic signal, there is a reduced maximum value and a reduced average value of the number of bits varied by transforming an input level representation original logic signal having n bits into a transition representation logic signal of m groups with only a maximum of k bits varied, wherein k and m are integer numbers, n is greater than k and each value of k and m is greater than 1. The transformed logic signal of m groups is transmitted. The transmitted logic signal of m groups is then transformed into the original logic signal having n bits. A maximum number of bits varied is k, which can be below n/2 as a maximum, which is less than an average bit variation of the input original signal.

Abstract: An encoding device encodes a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the stream of databits of the source signal is divided into n-bit source words, which device includes converting apparatus to convert the n-bit source words into corresponding m-bit channel words in accordance with a conversion of the parity preserve type, where m and n are integers, with m>n. The device further includes control apparatus for carrying out DC-control on the binary channel signal by introducing a freedom of choice in the source-to-channel conversion. A decoding device decodes the channel signal obtained from the encoding device.

Abstract: A method and structure for decoding n input signals and their complements to one of m output signals is provided. A capacitive network is provided having m output nodes. The output nodes are precharged to a given voltage value. N input signals and their complements are provided each having either a high value or a low value. At least one but less than all of the output nodes are discharged to a value less than the given voltage but greater than ground in output patterns responsive to given input patterns of the true and complement values of the input signals. The output patterns of the discharged nodes is such as to provide one and only one discharged or one and only one undischarged node for any given pattern of input signals. Preferably the capacitive network includes NMOS inversion capacitors.

Abstract: A register file array for storing or outputting binary logic bits of information encoded in 2B format is disclosed. The array includes an integrated 2B encoder which encodes stored information in 2B format before access by a read port to provide 2B formatted output without significantly affecting memory access time.

Abstract: Clock is reproduced stably. If data (limiting code) containing a plurality of consecutive minimum inversion interval Tmin is contained in the data inputted from a shift register, a Tmin consecution limiting code detection unit detects such consecutive interval. A constraint length judgement unit judges the constraint length i to be the constraint length corresponding to the code for limiting the constraint length i when a detection signal is inputted from the Tmin consecution limiting code detection unit, and outputs the judged constant length to a multiplexer. The multiplexer selects the output of a converter corresponding to the constraint length supplied from the constraint length judgement unit out of converters 14-1 to 14-r, and supplies the selected output to a run detection processing unit through a buffer.

Abstract: A fast n-bit to k-bit mapping or translation method and apparatus avoiding the use of content addressable memories (CAMs) is described. It essentially is characterized by using two conventional storage (RAMs). In the first storage (3), the n-bit words are stored preferably in an order determined by the binary search key. The second storage (4) holds the corresponding k-bit translations. Both storages are addressed by essentially the same address, which is established during the (binary) search performed to find a match between an input n-bit word and the contents of the first storage. In variants of the invention, the use of parallel comparisons and of pipelining is demonstrated.

Abstract: A method for selectively enabling one of X agents in a system so as to allow the selected agent to be active in a shared communication system. The method comprises the steps of assigning each agent to a unique subset M of a plurality of N select lines, M being greater than 1 and less than N, and translating an identification number so as to assert M of the plurality of N select lines. The asserted M select lines uniquely select a designated agent. For one embodiment, all of the X agents may be selected by enabling all N select lines. For another embodiment, more than one but not all of the agents may be selected.

Abstract: A track address pattern embedded in the servo zones of a storage medium for representing a track address identification having a binary bit length "n". The track addresses pattern embedded in the medium is recoded from a Gray-code representation of the track address identification and has a code rate of n/(n+1), where n.gtoreq.2. The recoded track address pattern (or codeword) is modeled from a Gray-code representation wherein a plurality of bit cells corresponding to a track address of the data storage apparatus are recoded to include a parity bit selected to maintain a selected parity for the track address pattern. More particularly, when a "1" occurs in the same bit cell location in two adjacent track address patterns, then the parity on "1"s up until the same bit cell location is the same for both of the m.sup.th and the (m-1).sup.th track address patterns and for the m.sup.th and the (m+1).sup.th track address patterns. Furthermore, the codewords provide that the bit cells of an m.sup.

Abstract: In order to provide a detector with fewer switching elements for detecting simultaneous occurrence of more than one of logic `1` or logic `0` out of plural inputs, 4 inputs A, B, C and D for example, a detector of the invention detects more than one of logic `1` from NAND logic of outputs of 3 OR-NAND composit gates as follows. ##EQU1## Each OR-NAND composit gate is composed of 4 pMOS transistors for common use and 4 nMOS transistors and a NAND gate of 3 inputs is composed of 3 pMOS transistors and 3 nMOS transistors.Therefore, the detector of 4 inputs of the invention can be composed of 22 MOSFETs insted of 36 MOSFETs needed for a conventional detector of 6 NAND gates of 2 inputs and a NAND gate of 6 inputs.

Abstract: Multiple resonant tunneling devices offer significant advantages for realizing ultra-dense, ultra-high performance multivalued logic arithmetic integrated circuits. A multivalued logic adder is disclosed, wherein two numbers represented by positive digit base-M range-N words are added by two-input summation circuits 40 which sum corresponding digits, then the digit sums are decomposed into a binary representation by range-7 multivalued to binary converter circuits 42, then three-input summation circuits 44 sum appropriate bits of the binary representations to calculate the digits of a positive digit base-2 range-4 word whose value is the sum of the two numbers. Preferably, the decomposition to binary representation is performed by multi-valued folding circuits 56 which are connected by voltage divider circuitry. Preferably, the multi-valued folding circuits contain multiple-peak resonant tunneling transistors 54. Ripple carries are eliminated and the speed of the adder is independent of input word width.

Abstract: The present invention generates a reference signal including identification information based on a first coding method and generates data signals by a second coding method different from the first coding method. Next, it time division multiplexes signals by allocating the reference signal to a reference time slot and allocating data signals to time slots of which phase difference between the reference time slot is predetermined, and sends a multiplexed signal. In a receiver side, the reference time slot is detected based on identification information in a transmitted signal.

Abstract: Digital data formatting/deformatting circuits perform digital data formatting/deformatting operations separately from a digital signal processor to reduce the required time and power consumption in formatting and deformatting digital data. In the formatting operation, the data to be formatted are arranged in a line and then outputted in the unit of a desired number of bits. In the deformatting operation, the formatted data are arranged in a line and then outputted in the unit of the original number of bits.

Abstract: An input data sequence is divided into fixed-length source segments, and each source segment is predicted from preceding data. The data are coded as a sequence of coded segments, each designating a non-negative number of correctly predicted segments and a non-negative number of literal segments. The literal segments are inserted into the coded data among the coded segments. The coded data are decoded by decoding each coded segment, predicting the designated number of correctly predicted segments from previously decoded data, and copying the literal segments. The length of the coded segments may vary according to the number of consecutive correctly predicted segments. The prediction rule, or the original data, may be modified under certain conditions, in order to increase the predictability of the source segments.