Abstract: A communication device assuring reliable and effective data transfer. Receiving a signal from a transmit timing generator, a communication control circuit sequentially transfers block data in RAM to an encoder. In response to a control signal from the communication control circuit, the encoder outputs a communication control signal, which comprises 6 bits of 0 and 6 bits of 1 and is indicative of the start of communication data, converting 8-bit parallel data (received from the RAM) into a 12-bit code comprising 6 bits of 0 and 6 bits of 1, and outputting a communication control signal indicative of the end of the communication data. The signals from the encoder are outputted as a serial signal, (which is free from any DC component) from a shift register and a driver.

Abstract: N-bit digital signals are transformed into M-bit digital signals (M>N), the N-bit signals being obtained by converting an analog signal into digital signals. Detected are transition points on a time axis and intervals between the transition points at which successive digital signals of the N-bit signals vary. (M-N) bit additional signals are generated which correct errors of the N-bit signals within a range of .+-.0.5 least significant bit of the N-bit signals in response to the transition points and the intervals. The additional signals are delayed so as to correspond to least significant bit of the N-bit signals. The delayed additional signals are combined with the N-bit signals to generate the M-bit signals. Instead of the transition points and intervals, detected are transition patterns of successive digital signals of the N-bit signals over transition points. (M-N) bit additional signals are generated which correct errors of the N-bit signals within a range of .+-.0.

Abstract: A code conversion circuit includes a first decoder having a number of output lines. The first decoder is responsive to an input binary signal representing a value i to develop a signal "1" on the (i+1)-th output line thereof. A second decoder is provided which includes gates connected to the respective ones of the first decoder output lines. The second decoder develops a signal "1" on all of the first to i-th output lines thereof, and a signal "0" on all of the remaining output lines. The gates of the second decoder are divided into a plurality of blocks in which gates are connected in series. Block control signals are prepared from most significant bits of the binary input signal and applied to the respective blocks. The block to which the signal "1" is applied from the first decoder so that the signals "1" and "0" are developed on appropriate ones of the output lines.

Abstract: A system and method for encoding and decoding binary data for serial transmission over a physical medium provides a highly efficient and less complex coding scheme while guaranteeing clocking information and guaranteeing an NRZ(I)-disparity of no greater than one per five-bit word. The system and method of the present invention comprise a 4/5 encoder which enables each nibble to be encoded and decoded independently from one another. The Coding system and method of the present invention guarantees an NRZ(I)-disparity having a magnitude of no greater than one for any word after NRZ(I) while providing at least one word with "NRZ(I) comma" property.

Abstract: An apparatus converts m-bit digital data having a scale factor of K.sub.1 to n-bit digital data having a scale factor of K.sub.2. The apparatus comprises a digital to analog converter which receives the m-bit digital data, for outputting a first analog signal representative of a value associated with the m-bit digital data. An amplifier receives the first analog signal multiplies it by a factor, and outputs a second analog signal. The factor of the amplifier is K.sub.2 /K.sub.1, such that the second analog signal has a value with the scale factor of K.sub.2 associated therewith. An analog to digital converter receives the second analog signal, and converts the second analog signal to the n-bit digital data. The n-bit digital data has the scale factor of K.sub.2 associated therewith, the value representative of the n-bit digital data being essentially equal in the example of the present application to the value representative of the m-bit digital data, however, this is not always a requirement.

Abstract: A system and method for encoding and decoding binary data for serial transmission over a physical medium provides a highly efficient and less complex coding scheme while guaranteeing clocking information and guaranteeing an NRZ(I)-disparity of no greater than one per five-bit word. The system and method of the present invention comprise a 4/5 encoder which enables each nibble to be encoded and decoded independently from one another. The coding system and method of the present invention guarantees an NRZ(I)-disparity having a magnitude of no greater than one for any word after NRZ(I) while providing at least one word with "NRZ(I) comma" property.

Abstract: A decoder has first and second decoder circuits for producing dual sets of outputs. The first decoder circuit is responsive to input lines B.sub.1 -B.sub.n representative of a binary value x and has first outputs Z.sub.1 -Z.sub.m where m=2.sup.n. In response to the value x applied to the first decoder, output line Z.sub.x+1 is set high while the remainder are set low. The second decoder circuit comprises m transmission gates serially connected between a first and a second potential. The transmission gates are each directly driven by a respective one of said first outputs Z.sub.1 -Z.sub.m. The second decoder circuit generates second outputs Y.sub.1 -Y.sub.m-1 at junctions of the transmission gates. In response to the value x applied to the first decoder, x number of the outputs Y.sub.1 -Y.sub.m-1 are set high beginning with the least significant output Y.sub.1 and continuing consecutively up to the output Y.sub.x with the remainder being set low.

Abstract: A digital resampling system is provided for converting a first digital signal to a second digital signal, where both signals represent the same analog signal but sampled at two different clock rates which are not phase-locked together. A filter is clocked by the first clock and outputs filtered samples at the first clock rate, optionally omitting samples which will not be used. A phase indicator determines the relative phase position of the first and second clocks and indicates an integer phase value and a fractional phase value which together indicate where a tick of the second clock falls among the ticks of the first clock. The integer phase value identifies a clock cycle of the first clock in which a tick of the second clock occurs, and the fractional phase value represents a fraction identifying a position of the tick of the second clock within the clock cycle of the first clock. A sample selector selects M filtered samples from those provided by the non-decimating filter based on the integer phase value.

Abstract: An apparatus for converting source data into modulation data includes a compressed look-up table based on a conversion correlation, a non-effective data discriminator, a group discriminator, an output flag generator, a flag modulator, a control signal generator and an output compensator. A first address having the source data and a original input flag and a second address having the source data and a modulated input flag are sequentially applied to the look-up table which in turn generates first tentative data and a first tentative flag with respect to the first address, generates second tentative data and a second tentative flag with respect to the second address, and produces unique non-effective data when non-effective data is applied.

Abstract: A network for transferring packet data in a frame structure, preferably mixed with isochronous data is provided. The frame structure is a continuously repeating structure, with each frame having a number of time slots. Certain ones of the time slots are available for transmitting packet data. The packet data is re-timed, e.g., by using a FIFO to output the data nibble-wise as required by the frame structure. Similar re-timing can be used for isochronous data so that the frame structure defines time-division multiplexing of the packet data and isochronous data. A four/five encoding scheme provides sufficient encoding efficiency that both the packet data and other data can be accommodated without degrading the data rate of the packet data. The encoding scheme provides extra symbols which can be used for transferring "no carrier" information, or "frame alignment" messages.

Abstract: Digital data recording/reproducing apparatus which uses a simple coding scheme for DC channel codes of the form M/N where M=N-1 and M and N are positive integers.

Abstract: An M of N decoder circuit includes N output terminals, log.sub.2 (n+1) logic input terminals, two voltage input terminals, and (N+1)log.sub.2 (N+1) pass transistors, each having a gate connected to one of the logic input terminals, a source connected to one of a voltage input terminal and an output terminal, and a drain connected to one of said output terminals, each of the pass transistors for passing a voltage signal from source to drain when the gate has applied to it one logic level and for not passing said voltage signal when the gate has applied to a different logic level. More particularly, half of the pass transistors are of one conduction type and half of the pass transistors are of an opposite conduction type. The gates of N+1 pass transistors are connected to each of the log.sub.2 (M+1) input terminals. For i =0 to log.sub.2 (N+1)-1, pass transistors of one conduction type whose gates are connected to an i-th input terminal are connected in groups of 2.sup.

Abstract: A method of encoding data for transmission between computer devices is disclosed in which data is encoded into a plurality of sequences, each sequence containing an equal number of ones and zeros and being of a predetermined bit length. There is a finite set of the permutations of equal numbers of ones and zeros in that predetermined bit length. One subset of the finite set is selected for use as data codes and a second subset is selected for use as control codes.

Abstract: A circuit for inversely converting the signal of six bits converted by the 5B6B coding rule conversion method in the digital transmission into the original signal of five bits is described. On the occasion of inversely converting the 6-bit signal to the original 5-bit signal, the mark rate of the 6-bit signal to be converted inversely is detected in accordance with the 5B6B coding rule conversion pattern. In this case, all patterns of six bits are not detected but such six bits are divided into the upper three bits and lower three bits and the mark rates of six bits are detected from the patterns of upper three bits and lower three bits. Thereby, a number of detected patterns can be reduced and simplification of circuit structure can also be realized.

Abstract: An encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m/n, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system and contains an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers, respectively. Each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder, synchronizing with a clock. The n bits of the output of the encoder is received in parallel in another shift register, and are serially output from the shift register, synchronizing with a second clock.

Abstract: In recording systems using partial-response maximum-likelihood detection (PRML) techniques, data sequences are preceded by a preamble consisting of all ones. Coding schemes are disclosed which allow to keep the number of consecutive ones occurring in the coded data sequences at a minimum, while simultaneously restricting the number of consecutive zeros in full and partial data sequences to a low value which is important for improving receiver operation. The disclosed coding schemes and apparatus enable a faster and more reliable discrimination between timing preambles and data sequences, thus allowing to use shorter timing preambles which results in faster receiver start-up and in a reduction of storage overhead for the preambles.

Abstract: This invention relates to a digital modulating method used for recording a PCM audio signal, computer data, and etc. on a recording medium such as an optical disc. The digital modulating method is constructed so that the minimum length between transition could be the maximum in encoding M bits into N bits (M<N), and can generate clock pulses with a simple circuit arrangement by satisfying the relationship N=.alpha.M, where .alpha. is an integer equal to or larger than 2.Further, by converting a predetermined unit of input data into a first code signal according to substantially the same conversion rule and selectively adding coupling bits of different bit number to each junction between a first code signal and an adjacent code signal, the digital modulating method is adaptable for various transmission systems with a simple arrangement.

Abstract: This invention reduces the Delta I noise on an integrated circuit chip by reducing the changes in current supply required for transitions in logic states of the input/output devices. The invention uses a 3/6 binary code for communicating between integrated circuit chips. This code uses six bits to represent the 16 hex code digits typically used for computer instructions. Three of the six bits are in a high logic state and three of the six bits are in a low logic state for all 16 hex code representations. Therefore, changing from any one logic state to another, does not change the overall current supply required by the six input/output devices. Groups of six input/output devices (corresponding to the 3/6 code) are located relatively close to each other with respect to the power supply pins which supply current to the six input/output devices. As a result, there is a high to low transition for every low to high transition over similar parasitic impedances on the input/output devices.

Abstract: In a data conversion method of converting source data of M bit unit to be recorded on a recording medium into conversion data of N (>M) bit unit, n, which is a number of inter-symbol interferences permitted in a transmission path, continuous codes in the codes of the conversion data are weighted with a weighting distribution decreasing linearly from a distribution center, the weighted n continuous codes are sequentially added to form the intermediate series, and then such conversion data that the sum of absolute values of differences of codes between the intermediate series (i.e., the code length) is more than a predetermined number of times as large as a reference value of the weighting coefficient is selected as a modulation code, whereby the pattern length between the code patterns can be made larger to thereby improve the recording density remarkably with using the present recording medium and recording and/or reproducing apparatus.

Abstract: A priority encoder for receiving input request signals at a number of input request terminals and for providing an N-bit output binary code word indicating the binary identification number of the highest-priority, currently-active input request terminal. Each output bit of the output binary code word is provided from a respective logic circuit. Whenever any one of a first group of input request terminals, which are identified as having a logical TRUE value in a particular bit position of the N-bit output binary code word, is active, all of a second group of input request terminals, having a logical FALSE value for the particular bit position, are disabled. Sequential operation of the logic circuits for each output bit is obtained by successively delaying enablement of a logic circuit until high-order logic circuits have completed operation.

Abstract: This method is characterized in that the data is encoded in the form of blocks of four bits in five-bit words, three bits (7) of each block being encoded according to the NRZ encoding method and one bit (8), according to the Manchester encoding method.

Abstract: A parallel analog to digital converter which uses a dual-rank arrangement of flash converters. The flash converters have Josephson junctions and act as a sample and hold circuit. The dual-rank arrangement allows a smaller number of comparators to be used than in a pure parallel conversion scheme, which also makes encoding the outputs of the flash converters less complex. The analog to digital converter includes an encoder which controls its output interferometers based on the net flux generated by combinations of input currents into the encoder.

Abstract: In a data modulating system, 12 bits of input data correspond to 15 channel bits of an output code. The input data of 12 bits are converted to the output code of 15 channel bits such that 7 channel bits in the output code provide code "1". The output code of 15 channel bits is divided into a first group of 7 channel bits and a second group of 8 channel bits. The number of bits in the first group providing code "1" the number of bits in the second group providing code "1" are respectively at 3 and 4, 4 and 3, or 2 and 5.

Abstract: An 8B:10B serial data transmission code is described, which provides an overall balance between ones and zeros, a code run bound of 4, and a worst case transition density of 40%. In addition, the code provides two special control characters which are unique in the coded bit stream and can be used for synchronization. The data can be encoded using a 256.times.8 ROM, and decoded using a 1024.times.6 ROM, with two bits being transmitted unencoded.

Abstract: A digital modulator converts M-bit data words to N-bit code words (N>M) each containing a specific number of bits `1`. The specific number is one of a plurality of predetermined numbers which are different by at least 3 from one another. A specific data word may be converted to either one of two code words having different numbers of bits `1` from each other so as to reduce DC components of a channel code constituted by the code words.

Abstract: A system for encoding/decoding an 8-bit binary code into/from a 4/11 channel code is disposed such that an 8-bit binary code is encoded into a 11-bit channel code by adding a 3-bit extension code as a parity code which keeps the number of "1"s in the channel code at four. When the 8-bit binary code cannot be encoded by this rule, it is converted to a temporary 8-bit code by a table encoder and then a 3-bit extension code is added. The 4/11 channel code is decoded referring to the 3-bit extension code, which indicates the encoding rule by which the 4/11 channel code has been generated. When the 4/11 channel code is detected to have been encoded by the bits-adding rule, an original 8-bit binary code is derived from the 4/11 code by removing the 3-bit extension code. When the 4/11 channel code has been encoded by the table-encoding rule, it is decoded by a table decoder.

Abstract: A code converter includes a signal converter converting an input digital signal into an intermediate digital signal of two's complement. A subtracter has a minuend input node, receiving lower bits of the intermediate digital signal, and a subtrahend input node. A digital integrator receives an output from the subtracter, a digital comparator receives an output from the digital integrator, a delay unit receives an output from the digital comparator to execute a one-sampling period delay. An output from the delay unit is applied to the subtrahend input node of the subtracter, and an adder receives the remaining upper bits of the intermediate digital signal and the output from the digital comparator, a converted output digital signal being produced from the adder.

Abstract: A data outputting circuit including absolute value conversion circuit for converting digital data that is inputted with a determined sampling period into absolute value data, a register for storing the largest of the absolute value data provided within a predetermined period of time, a transferring register for receiving data and trransferring the data every predetermined period of time, and a compressing circuit adapted to compress compressing the data applied to the transferring register, whereby the circuit scale is reduced, and the data transferring time or the number of transferring lines is decreased.

Abstract: A priority encoder having MxN input lines and M output lines included M N-bit input priority encoder units, a precharging device, and a zero detecting device. Each N-bit input priority encoder unit includes an N-bit priority detecting device, a memory, a selector, a carry signal generating device, and a control device. The control device controls the output of the N-bit input prioroity encoder in accordance with the outputs of the N-bit priority detecting device and the carry signal generating device.

Abstract: Programmable transcoding device which sequences of binary words of variable lengths corresponding to strings of characters in a first alphabet are transcoded into other sequences of binary words intelligible in a second alphabet. The device is connected to digital systems exchanging sequences of words via interfaces provided with files. A CPU connected to the interfaces via a switching device receives the incoming sequences, and delivers transcoded outgoing sequences of binary words. An exchange management unit monitors the data transfers in the device and regulates the flows of words between the device and the digital systems. A terminal or microcomputer can also equip the device so as to produce transcoding tables to be downloaded in an RAM of the CPU.

Abstract: An information-transmission system including an encoder for converting n-bit information words (D7, . . . , D0) into transmitted m-bit code words (C10, . . . , C0), and a decoder which reconverts the received code words (C'10, . . . , C'0) into information words (D*7, . . . , D*0) corresponding to the original information words. For a first group the encoder converts a first portion (D7, . . . , D3) into a first portion of a code word, such portion comprising q bits (C10, . . . , C5) thereof; and converts a second portion (D2, . . . , D0) of the information word into a second portion of the code word, such portion comprising s bits (C4, . . . , C0) thereof. For a second group the encoder converts a first portion (D7, . . . , D3) into a second portion comprising q bits (C'5, . . . , C'0) of a code word, and converts a second portion (D2, . . . , D0) of the information word into a first portion comprising s-bits of (C'10, . . . , C'6) such code word.

Abstract: A method and apparatus for generating signals representing a plurality (p) of n bit words corresponding to respective input signals. The apparatus comprises a basic word generator (7) for generating first signals representing m basic words (A-D) whereby the p words are the same as or are cyclic rearrangements of the n bits of the m basic words. Control means including combinatorial logic (33) determines the one of the p words corresponding to each input signal and generates corresponding control signals. Selection means including optical modulators (10-13, 20-25) are responsive to the control signals for selecting the appropriate first signal, if necessary after recycling by imposing selected delays, to constitute an output signal corresponding to the determined one of the p words.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.