Analog To Digital Conversion Followed By Digital To Analog Conversion Patents (Class 341/110)
  • Patent number: 10331282
    Abstract: In some aspects of the present disclosure, a touch-panel interface includes a plurality of receivers, wherein each of the receivers is coupled to one or more receive lines of a touch panel, and each of the receivers includes a switch capacitor network and an amplifier. The touch-panel interface also includes controller configured to control switches in the switch capacitor network of each of one or more of the receivers to operate each of the one or more of the receivers in one of a plurality of different receiver modes.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Mohamed Imtiaz Ahmed, Dustin Tarl Dunwell, William Martin Snelgrove, Ayaz Hasan, Matthew David James
  • Patent number: 10320994
    Abstract: Data files with digital envelops may be used for many new applications for cloud computing. The new applications include games and entertainments such as digital fortune cookies, and treasure hunting, unique techniques for digital right management, or even additional privacy and survivability on data storage and transport on cloud computing. Wavefront multiplexing/demultiplexing process (WF muxing/demuxing) embodying an architecture that utilizes multi-dimensional waveforms has found applications in data storage and transport on cloud. Multiple data sets are preprocessed by WF muxing before stored/transported. WF muxed data is aggregated data from multiple data sets that have been “customized processed” and disassembled into any scalable number of sets of processed data, with each set being stored on a storage site. The original data is reassembled via WF demuxing after retrieving a lesser but scalable number of WF muxed data sets.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: June 11, 2019
    Assignee: SPATIAL DIGITAL SYSTEMS, INC.
    Inventors: Donald C. D. Chang, Juo-Yu Lee
  • Patent number: 10298257
    Abstract: A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 21, 2019
    Assignee: NXP USA, INC.
    Inventors: Brandt Braswell, Douglas Alan Garrity, Paul Rene DeRouen
  • Patent number: 10291249
    Abstract: An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 14, 2019
    Assignee: Analog Devices, Inc.
    Inventor: Michael C. W. Coln
  • Patent number: 10263633
    Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 16, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, David Paul Singleton
  • Patent number: 10218369
    Abstract: Disclosed herein are some continuous time systems and methods. Some of the disclosed systems and methods use a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output, a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs, one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output, and an adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 26, 2019
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Sharvil Pradeep Patil, Yannis Tsividis, Yu Chen
  • Patent number: 10171103
    Abstract: A hardware compression architecture including a shift register including: a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage; a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match; logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 1, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Adir Zevulun, Noam Rom, Nir Shmuel
  • Patent number: 10164802
    Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 25, 2018
    Inventors: Albert Vareljian, Vassili Kireev
  • Patent number: 10148281
    Abstract: According to one embodiment, an analog-to-digital converter includes a first digital-to-analog converter, a comparator configured to digitally output based on a first clock signal, a clock generator configured to generate the first clock signal from an input clock signal, and a controller configured to control the first digital-to-analog converter. The clock generator sets a cycle of the first clock signal to a first cycle if the input clock signal is at a first logic level, and sets the cycle of the first clock signal to a second cycle shorter than the first cycle if the input clock signal is at a second logic level.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 4, 2018
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Daisuke Kurose
  • Patent number: 10129392
    Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 13, 2018
    Assignee: Global Tel*Link Corporation
    Inventor: Stephen Lee Hodge
  • Patent number: 10038575
    Abstract: In some embodiments, a DFE including: an input terminal configured to receive an input signal carrying a plurality of symbols; an adder circuit coupled to the input terminal of the DFE; a plurality of comparator circuits configured to receive respective threshold signals; a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, where: the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and the plurality of correction coefficients are independently adjusted based on a previously received symbol.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 31, 2018
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Steffan, Augusto Andrea Rossi, Emanuele Depaoli
  • Patent number: 10022542
    Abstract: In one aspect, the disclosure features systems for providing auditory signals to a subject. The systems include a sensor front-end circuit configured to be connected to an acoustic sensor and to convert analog signals received from the acoustic sensor to digital electric signals. The systems further include a sound processor circuit configured to be connected to the sensor front-end circuit and receive the electric signals provided by the sensor front end circuit. The sound processor includes multiple filters that spectrally decompose the received electrical signals into multiple spectral channels during operation of the system. The multiple spectral channels include at least a low frequency channel and a high frequency channel and the sound processor circuit is configured to operate the low frequency channel at a sample rate lower than a sample rate of the high frequency channel.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 17, 2018
    Assignees: Massachusetts Eye & Ear Infirmary, Massachusetts Institute of Technology
    Inventors: Marcus Yip, Anantha Chandrakasan, Konstantina Stankovic
  • Patent number: 10015014
    Abstract: Technologies for secure presence assurance include a computing device having a presence assertion circuitry that receives an input seed value and generates a cryptographic hash based on the received input seed value. The computing device further verifies the integrity of the presence assertion circuitry based on the generated cryptographic hash.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: David Johnston, David W. Grawrock
  • Patent number: 9966968
    Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: May 8, 2018
    Assignee: MAXLINEAR, INC.
    Inventors: Raja Pullela, Curtis Ling
  • Patent number: 9961632
    Abstract: A wireless user equipment (UE) device may include a receiver and transmitter. The UE device may dynamically vary the fidelity requirements imposed on the analog signal processing performed by the receiver and/or the transmitter in response factors such as: amount of signal interference (e.g., out-of-band signal power); modulation and coding scheme; number of spatial streams; extent of transmitter leakage; and size and/or frequency location of resources allocated to the UE device. Thus, the UE device may consume less power on average than a UE device that is designed to satisfy fixed fidelity requirements associated with a worst case reception scenario and/or a worst case transmission scenario.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: May 1, 2018
    Assignee: Apple Inc.
    Inventors: Konstantinos Sarrigeorgidis, Tarik Tabet, Moustafa M. Elsayed
  • Patent number: 9960805
    Abstract: Systems and methods for suppressing transmitter noise in a receive band of a co-located receiver that are suitable for wideband applications are disclosed. In one embodiment, a transmitter is configured to upconvert and amplify a digital transmit signal to provide an analog radio frequency transmit signal at an output of the transmitter that includes a desired signal in a transmit band of the transmitter and transmitter noise in a receive band of a main receiver. The main receiver is configured to amplify, downconvert, and digitize an analog radio frequency receive signal to provide a digital receive signal. The digital feedforward transmit noise cancellation subsystem is configured to process the digital transmit signal to generate a digital transmitter noise cancellation signal that is representative of the transmitter noise in the receive band and is subtracted from the digital receive signal to thereby provide a compensated digital receive signal.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Mark Wyville, Lars Johan Thorebäck, Spendim Dalipi
  • Patent number: 9935643
    Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 3, 2018
    Assignee: Marvell International Ltd.
    Inventors: Nick C. Chang, Kenneth Thet Zin Oo, Wyant Chan, Pierte Roo
  • Patent number: 9933276
    Abstract: Methods and apparatus disclosed herein implement or otherwise embody a technique that compensates for cyclic position errors in encoder-based position detection, wherein the cyclic position errors arise from the presence of harmonic components in the encoder signals relied upon for position determination. Using position-domain compensation for errors arising in the encoder domain offers computational simplicity and impressive compensation performance, even when compensating for a plurality of higher harmonics in the encoder signals, e.g., third harmonic, fifth harmonic, etc. Consequently, even high-precision position monitoring or control can use relatively inexpensive types of encoders known to output encoder signals having significant harmonic components.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 3, 2018
    Assignee: Delta Tau Data Systems, Inc.
    Inventors: Curtis Wilson, William Olson
  • Patent number: 9818448
    Abstract: Systems and methods for linking time-based media and temporal metadata provide single command control during editing of media having associated temporal metadata. A single control enables an editor to switch between monitoring both source media and its corresponding temporal metadata and monitoring both a pre-recorded version of the media and its corresponding temporal metadata. Another single control enables an editor to start and stop the recording of a source media track and its corresponding source temporal metadata. In one application, the editing is performed for media tracks having time-based spatial metadata for playback in immersive environments with the spatial metadata defining an apparent location of sound objects within the immersive environment.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: November 14, 2017
    Assignee: Avid Technology, Inc.
    Inventors: Connor E. Sexton, Steven H. Milne
  • Patent number: 9806730
    Abstract: A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that includes a plurality of switches coupled to receive differential digital control signals and to provide first and second differential current outputs, a current source coupled to an upper rail and to a first node of the switching circuit, a first current sink coupled to a lower rail and to a second node of the switching circuit, and an interference cancellation circuit coupled to substantially prevent a tail capacitance current from flowing through the first and second differential current outputs.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 31, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Eeshan Miglani, Sandeep Jhanwar
  • Patent number: 9806731
    Abstract: A signal calibration circuit and a signal calibration method are provided. The signal calibration circuit includes: an analog-to-digital conversion circuit, coupled to an output terminal of the circuit to be tested, obtaining an analog signal output by the circuit to be tested and transforming the analog signal into a digital signal; a calibration signal generation circuit, generating a calibration signal, modifying the calibration signal according to a first signal, and outputting a modified calibration signal; and a calibration circuit, coupled to the analog-to-digital conversion circuit and the calibration signal generation circuit, obtaining the digital signal and the calibration signal, calibrating the digital signal according to the modified calibration signal and outputting a calibrated digital signal. The first signal is a predetermined signal or the calibrated digital signal output by the calibration circuit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: October 31, 2017
    Assignee: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Cwei Wei, Yang Zhang
  • Patent number: 9800261
    Abstract: A third-order loop filter for a delta signal modulator comprises a single operational amplifier, and a resistor-capacitor network including a plurality of capacitors and a plurality of resistors which are connected to the operational amplifier, and satisfy a third-order transfer function.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 24, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young Kyun Cho, Bong Hyuk Park
  • Patent number: 9793915
    Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 17, 2017
    Assignee: MaxLinear, Inc.
    Inventors: Raja Pullela, Curtis Ling
  • Patent number: 9793983
    Abstract: Examples of a system and method for adaptively tuning a radio frequency (RF) front-end are generally described herein. In some examples, the frequency of a transmit signal of RF front-end circuitry is swept in at least a part of the RF transmit band. RF power in a receiver is detected as a function of the RF frequency of the transmit signal to determine a location of at least one tunable notch or other band stop element in the frequency domain. Information from the detected RF power is determined as a function of the RF frequency of the transmit signal. The RF front-end circuitry is adjusted to a selected frequency response using the determined information.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 17, 2017
    Assignee: Intel IP Corporation
    Inventors: Poul Olesen, Peter Bundgaard, Mikael Bergholz Knudsen
  • Patent number: 9787273
    Abstract: A method implemented by processing and other audio components of an electronic device provides a smart audio output volume control, which correlates a volume level of an audio output to that of an audio input that triggered generation of the audio output. According to one aspect, the method includes: receiving an audio input that triggers generation of an audio output response from the user device; determining an input volume level corresponding to the received audio input; and outputting the audio output response at an output volume level correlated to the input volume level. The media output volume control level of the device is changed from a preset normal level, including from a mute setting, to the determined output level for outputting the audio output. Following, the media output volume control level is automatically reset to a pre-set volume level for normal media output.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: October 10, 2017
    Assignee: Google Technology Holdings LLC
    Inventor: Boby Iyer
  • Patent number: 9767786
    Abstract: A system and method for quieting unwanted sound. As a non-limiting example, various aspects of this disclosure provide a system and method, for example implemented in a premises-based or home audio system, for quieting unwanted sound at a particular location.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: September 19, 2017
    Assignee: SOUND UNITED, LLC
    Inventors: Bradley M. Starobin, Matthew Lyons, Stuart W. Lumsden, Michael DiTullo
  • Patent number: 9749164
    Abstract: Systems, apparatus, and methods of asynchronous digital communication include at least one transmitter and/or at least one receiver communicatively coupleable to at least one communication interface for encoding and transmitting digital information as and/or receiving and decoding digital information from a transition between a first symbol and a second symbol, based on a predetermined relationship between the first symbol and the second symbol in such a way that the timing of the symbols is no longer relevant.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 29, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Grant Seaman Anderson, Charles Giona Sodini
  • Patent number: 9742424
    Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: August 22, 2017
    Assignee: Nanyang Technological University
    Inventors: Sunny Sharma, Chirn Chye Boon
  • Patent number: 9715885
    Abstract: This invention provides a signal processing apparatus for effectively detecting an abrupt change in an input signal. The signal processing apparatus includes a converter that converts an input signal into a phase component signal and an amplitude component signal in a frequency domain. The signal processing apparatus further includes a calculator that calculates feature amounts of the phase component signal and the amplitude component signal derived by the converter. The signal processing apparatus further includes a determiner that determines presence probability of an abrupt change in the input signal based on the feature amounts calculated by the calculator.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: July 25, 2017
    Assignee: NEC Corporation
    Inventors: Akihiko Sugiyama, Ryoji Miyahara
  • Patent number: 9705823
    Abstract: A port status synchronization method, related device, and system, where a physical layer (PHY) device or an external processor connected to the PHY device determines whether a first service interface of the PHY device changes, and when the first service interface changes, controls a second service interface of the PHY device to restart auto-negotiation and sends, using the second service interface, an auto-negotiation advertisement packet to a first device connected to the second service interface in order to trigger the first device to synchronize, according to the auto-negotiation advertisement packet, a status of the second service interface and a status of the first service interface such that performing port status negotiation and synchronization between a link layer (media access control (MAC)) device or the first device and the PHY device using a service interface is achieved, without a need of disposing a management data input/output (MDIO) interface.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 11, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yutao Li
  • Patent number: 9698811
    Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: July 4, 2017
    Assignee: MAXLINEAR, INC.
    Inventors: Kaveh Moazzami, Pawan Tiwari, Gaurav Chandra
  • Patent number: 9646597
    Abstract: An unmanned aerial vehicle (UAV) may emit masking sounds during operation of the UAV to mask other sounds generated by the UAV during operation. The UAV may be used to deliver items to a residence or other location associated with a customer. The UAV may emit sounds that mask the conventional sounds generated by the propellers and/or motors to cause the UAV to emit sounds that are pleasing to bystanders or do not annoy the bystanders. The UAV may emit sounds using speakers or other sound generating devices, such as fins, reeds, whistles, or other devices which may cause sound to be emitted from the UAV. Noise canceling algorithms may be used to cancel at least some of the conventional noise generated by operation of the UAV using inverted sounds, while additional sound may be emitted by the UAV, which may not be subject to noise cancelation.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: May 9, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Brian C. Beckman, Jack Erdozain, Jr., Fabian Hensel, David Lindskog, Sheridan Leigh Martin
  • Patent number: 9575920
    Abstract: Exemplary methods and systems are directed to transmitting a process map of a control or automation system via a gateway device. The gateway device includes at least one first functional unit connected to a higher-ranking control unit via a first communications link based on a primary field bus protocol, and at least one second functional unit connected to at least one field device via a second communications link based on a secondary field bus protocol. Binary signals are stored in corresponding registers and analog signals, which are in an integer format, are transmitted to the first functional unit such that the number of binary signals is reduced by packing the binary signals into data bytes. The data bytes are translated into corresponding telegrams that can be processed by the primary field bus protocol and with the analog signals are transmitted to the higher-ranking control unit.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: February 21, 2017
    Assignee: ABB AG
    Inventor: Muhamad-Ikhwan Ismail
  • Patent number: 9571120
    Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 14, 2017
    Assignee: Intel IP Corporation
    Inventors: Franz Kuttner, Antonio Passamani, Davide Ponton
  • Patent number: 9564915
    Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: February 7, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Wajid Hassan Minhass, Oeivind A. G. Loe
  • Patent number: 9564203
    Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 7, 2017
    Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.
    Inventors: Naohisa Nishioka, Chikara Kondo
  • Patent number: 9553602
    Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: January 24, 2017
    Assignee: Integrated Device Technology, inc.
    Inventors: I-chang Wu, Jagdeep Bal
  • Patent number: 9547037
    Abstract: A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Divya Pratap, Sung Jin Jo
  • Patent number: 9509321
    Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 29, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Philippe Deval, Gabriele Bellini, Patrick Besseux, Francesco Mazzilli
  • Patent number: 9509330
    Abstract: Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: November 29, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Takashi Oshima
  • Patent number: 9479150
    Abstract: A multi-phase clock circuit includes: a phase tuning circuit configured to receive a primitive N-phase clock including N primitive clocks of the same period but distinct phases and output a calibrated N-phase clock including N calibrated clocks in accordance with a first tuning signal, where N is integer greater than one; a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output clock in accordance with a multiplexing control signal; a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital code; and a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode select signal.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: October 25, 2016
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 9432037
    Abstract: Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Seung-Hyun Oh, Jong-Woo Lee, Thomas Byung-Hak Cho
  • Patent number: 9425814
    Abstract: Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive Approximation Register (SAR) to provide digital approximations of an input analog voltage to a Capacitor Digital-to-Analog Converter (DAC), which generates a voltage from the digital approximations. The two voltages are compared and the comparison value used as the input for the SAR. After successive approximations, a digital combiner generates the digital conversion value from the outputs of the Flash-assisted ADC and the SAR. In one aspect, the bit cycles required for conversion are reduced by using redundancy and recombination.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: August 23, 2016
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Ashutosh Verma
  • Patent number: 9419686
    Abstract: A receiver of a near field communication device includes a local oscillator, a first channel, and a second channel. The local oscillator may be configured to generate a first local oscillating signal. The first channel may be configured to process an input signal by mixing the input signal with the first local oscillating signal. The second channel may be configured to process the input signal by mixing the input signal with a second local oscillating signal that has a phase difference of 90 degrees with respect to the first local oscillating signal. Each of the first and second channels may include a comparator unit that includes a comparator configured to compare, in a comparator mode, an amplifier output signal with a reference voltage whose level increases in a step-wise manner and the comparator unit may be configured to set a level of the reference voltage to be used in a normal mode based on an output signal of the comparator.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hang-Seok Choi, Il-Jong Song, Jun-Ho Kim, Hyuk-Jun Sung, Min-Woo Lee
  • Patent number: 9397955
    Abstract: Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: July 19, 2016
    Assignee: Maxlinear, Inc.
    Inventor: Curtis Ling
  • Patent number: 9391627
    Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Nandan Srinivasa, Tharun Nagulu
  • Patent number: 9374105
    Abstract: A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 21, 2016
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventors: Daniel James Eddleman, Chad Thomas Steward
  • Patent number: 9362938
    Abstract: Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: June 7, 2016
    Assignee: QUALCOMM Technologies International, Ltd.
    Inventors: Hashem Zare-Hoseini, Dimitrios Mavridis
  • Patent number: 9363116
    Abstract: Embodiments provide an area, cost, and power efficient multi-service transceiver architecture. The multi-service transceiver architecture simplifies receiver/transmitter front ends needed for a multi-service architecture, by replacing significant portions of multiple receiver and/or transmitter front ends with a single ADC and/or DAC, respectively. In embodiments, a plurality of received service contents are combined into one composite analog/RF signal and applied to an ADC. The ADC converts the composite signal into a composite multi-service digital signal. Digital techniques are then used to separate the plurality of service contents into a plurality of respective digital streams that each can be independently demodulated. Similarly, in the transmit direction, a plurality of digital streams, including a plurality of service contents, are combined into one composite digital signal.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: June 7, 2016
    Assignee: Broadcom Corporation
    Inventors: Ray (Ramon) Gomez, Len Dauphinee
  • Patent number: 9312467
    Abstract: An apparatus for generating sinusoidal waves may include: a look-up table storage unit storing a look-up table including a plurality of sampling points determined based on a base frequency and a sampling frequency; a sinusoidal wave generating unit calculating an integer ratio of a target frequency to the base frequency and obtaining sampling points from the look-up table by reflecting the integer ratio so as to generate a sinusoidal wave; and a correction control unit calculating noise information in the generated sinusoidal wave, and controlling the sinusoidal wave generating unit to correct the sampling frequency if the noise information fails to meet a predetermined requirement.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 12, 2016
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Gyu Won Kim