Abstract: Mixed-signal circuitry including a set of capacitive digital-to-analogue converter, CDAC, units for carrying out digital-to-analogue conversion operations to convert respective digital values into corresponding analogue values; and control circuitry, where: each CDAC unit includes an array of capacitors at least some of which are configured to be individually-switched dependent on the digital values, the capacitors configured to have nominal capacitances; a given capacitor of the array of capacitors in each of the CDAC units is a target capacitor; the set of CDAC units includes a plurality of sub-sets of CDAC units; at least one of the target capacitors per sub-set of CDAC units is a variable capacitor, controllable by the control circuitry to have any one of a plurality of nominal capacitances defined by the configuration of that capacitor.

Abstract: Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

Abstract: There is provided a detection device including a light source, an avalanche diode, a first counter, a second counter and a processor. The light source emits light within a first interval, and is turned off within a second interval, a third interval and a fourth interval. The avalanche diode detects photons corresponding to the first interval, second, third and fourth intervals to trigger avalanche events. The first counter performs up-counting on the avalanche events in the first interval and performs down-counting on the avalanche events in the third interval to generate a first count value. The second counter performs up-counting on the avalanche events in the second interval and performs down-counting on the avalanche events in the fourth interval to generate a second count value. The processor calculates a time-of-flight according to the first count value and the second count value.

Abstract: A magnetic field measuring apparatus includes an A/D conversion unit, an integration unit, and a post-processing unit. The A/D conversion unit is configured to sample a signal at a predetermined sampling frequency and perform conversion into digital data, the signal being based on an output voltage from a superconducting quantum interference device configure to detect a magnetic field emanating from a living organism. The integration unit is configured to obtain a biological magnetic field signal based on a value obtained by integrating the digital data, the biological magnetic field signal indicating a magnetic field emanating from the living organism. The post-processing unit is configured to perform decimation processing on the biological magnetic field signal output from the integration unit.

Abstract: An AD converter includes: an accumulation conversion unit that performs a comparison of magnitudes of an input voltage V2 and an accumulated voltage V1 obtained by accumulating a unit voltage and outputs a comparison signal representing a result of the comparison; an accumulation comparison determination unit that repeatedly compares an accumulated voltage V1, obtained by repeating the comparison until the comparison signal changes and corresponding to an accumulated voltage V1 at which the comparison signal changes, and the input voltage V2 a predetermined number of times to determine an equivalent-state accumulation number in which a state probability that the comparison signal changes is equal to a threshold; and a control unit that determines conversion data of the input voltage using the equivalent-state accumulation number.

Abstract: A calibration system is disclosed. The calibration system includes a waveform generator configured to generate a periodic waveform and a control circuit in signal communication with the waveform generator. The control circuit includes an analog-to-digital converter configured to convert the periodic waveform to digital values and an electronic device in signal communication with the analog-to-digital converter. The electronic device is configured to verify calibration of (1) timing of the control circuit and (2) voltage levels of the control circuit based on the periodic waveform.

Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

Abstract: A semiconductor device includes a galvanic isolator; a transmitting circuit that transmits a transmission signal via the galvanic isolator; a receiving circuit that receives a received signal corresponding to the transmission signal via the galvanic isolator; an encoding circuit that encodes two input signals and generates the transmission signal; and a decoding circuit that decodes the two input signals from the received signals.

Abstract: A controller causes a calculation device to perform calculation that determines an operation of a moving object and generates digital signals that define the operations of actuators. The generated digital signals are output to a digital signal transmission path by a signal bus control IC. ICs attached to the actuators obtain digital signals that define the operations of the actuators from the digital signal transmission path and generate control signals for the actuators based on the operations defined by the digital signals.

Abstract: Embodiments of the disclosed technologies provide solutions for automatically reading digital electronic documents that contain tables and correctly extracting table data, rows and columns from the documents with high accuracy and high throughput. Embodiments are capable of converting a table portion of a read-only document to a searchable, editable data record using text rectangle (TR)-level numerical data that indicates probabilities of TRs belonging to canonicals and at least one convolutional neural network (CNN) that processes the TR-level numerical data to produce table-level numerical data.

Abstract: A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes analog-to-digital circuitry and digital-to-analog circuitry. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for downstream processes. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to the output port of the splitter board for the downstream processes.

Abstract: The current disclosure is related to a column and line digital-to-analog converter (DAC) with a hybrid coupler for generating quadrature analog signals. The DAC may include an array of unit power amplifiers (cells). A first portion of the cells of the array may be coupled to a first column decoder to receive in-phase components of digital signals and a second portion of the cells may be coupled to a second column decoder to receive quadrature components of the digital signals. The first portion of the cells of the array may generate in-phase components of analog signals and the second portion of the cells of the array may generate quadrature components of the analog signals. A hybrid coupler of the DAC may receive the in-phase and quadrature components of the analog signals with a similar phase, delay the quadrature components by a phase delay (e.g., 90 degrees), and output the resulting analog signals.

Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.

Abstract: A receiver is provided that includes a plurality of sub-rate receiver lanes each of which is configured to receive an analog receive signal from an analog front-end and produce digital sub-rate receiver data. The receiver includes one or more first digital-to-analog converters (DACs) (also referred to herein as “average” DACs) shared across the plurality of sub-rate receiver lanes, and one or more second DACs (also referred to herein as “mismatch cancellation” DACs) for each sub-rate receiver lane of the plurality of sub-rate receiver lanes. The one or more second DACs of a respective sub-rate receiver lane provide output to be combined with an output of a corresponding one of the one or more first DACs during processing of the analog receive signal in the respective sub-rate receiver lane to account for a sub-rate receiver lane specific offset with respect to a corresponding one of the one or more first DACs.

Abstract: Provided is an AD converter, including: an analog signal input circuit, configured to be input with an analog input signal, and output a first analog output signal based on the analog input signal and a second analog output signal based on the analog input signal at different timing; an integral circuit, configured to integrate the first analog output signal and the second analog output signal and output the first integral signal and the second integral signal; a predictive circuit, configured to predict an integral signal output after the output by the integral circuit based on the first integral signal and the second integral signal output by the integral circuit, and output a predictive integral signal; and a quantization circuit, configured to generate a digital signal with the predictive integral signal quantized.

Abstract: A voice communications computer system (“VCCS”) receives a ring signal from a call device having unverified device identification data. The VCCS identifies an audible frequency component and an electronic frequency component of the ring signal. The VCCS identifies a device identification characteristic or a geographic location characteristic based on the audible or electronic frequency components, and identifies a stored identification characteristic associated with the device identification data. Based on a comparison of the stored identification characteristic with the device identification characteristic or geographic location characteristic, the VCCS generates fraud estimation data. In some cases, the VCCS generates call status data based on the fraud estimation data. The VCCS provides the fraud estimation data or the call status data to a user interface device, which is configured to display data or perform a call action for a call associated with the ring signal.

Abstract: A multi-bit resolution sub-pipeline structure for measuring a jump magnitude of a transmission curve, comprising: a sub-analog-to-digital converter having n-bit resolution configured to quantize input analog voltage signals and output digital voltage signals; a sub-digital-to-analog converter having n-bit resolution configured to convert the digital voltage signals output by the sub-analog-to-digital converter into corresponding analog voltage signals; a decoder having n-bit resolution configured to decode an n-bit binary input signal; and a switched-capacitor amplification unit configured to, when in a normal mode, perform sampling and residue amplification on the input analog voltage signals; and when in a test mode, measure the jump magnitude of the transmission curve corresponding to each decision level. Magnitude measurement of a transmission curve is performed within 2n clock periods, th and a measurement result is sent to a back-end digital domain of the A/D converter for correction.

Abstract: Described herein is an apparatus and a method for a low noise infinite radio frequency (RF) delayed-locked loop (DLL). The apparatus comprises a phase detector having a first input configured to receive a first RF signal, a second input, and an output; an infinite phase shifter having a first input configured to receive a second RF signal, an input bus, and an output connected to the second input of the phase detector; and a controller having a first input connected to the output of the phase detector and an output bus connected to the input bus of the infinite phase detector, wherein the output of the infinite phase shifter comprises a low noise signal in phase alignment with the first RF signal.

Abstract: A digital microphone includes at least one integrator; a state detection and parameter control component directly coupled to an output of the integrator; and a signal processing component coupled to an output of the state detection and parameter control component, wherein a parameter of the signal processing component includes a first value in a first operational mode and a second value in a second operational mode different from the first operational mode.

Abstract: A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

Abstract: A semiconductor device with a high driving speed is provided. The semiconductor device includes first to fourth cells, a converter circuit, and first to fourth wirings. The first and second cells make a first current and a second current each corresponding to the product of first data and second data flow in the first wiring and the second wiring, respectively. The third and fourth cells make base currents in the same amount flow in the first and second wirings. The converter circuit outputs, from an output terminal thereof, a voltage corresponding to the differential current between the sum of the first current and the base current flowing in the first wiring and the sum of the second current and the base current flowing in the second wiring.

Abstract: The present invention relates in general to the field of hypnotherapy, and more specifically, to a hypnotherapy system for children that utilizes an interactive doll connected to a website and/or downloadable computer software application (“app”), and a method of hypnotherapy for children using the system. One aspect of the present disclosure includes an interactive doll that is configured to play a variety of hypnosis scripts to the child through an audio playback device. The hypnosis scripts may be downloaded to the audio playback device through the connected website/app, wherein the hypnosis scripts are directed to address particular behavioral or emotional issues in the child. The purpose of the invention is to provide a hypnotherapy system and method of hypnotherapy for children that may be conveniently administered to the child in a safe and familiar environment, such as in the child's home or bedroom, without requiring the presence of a hypnotherapist.

Abstract: An exemplary incremental two-step capacitance-to-digital converter (CDC) with a time-domain sigma-delta modulator (TD??M) includes a voltage-controlled oscillator (VCO)-based integrator that can be used in a low-order loop configuration. Example prototypes are disclosed, which when fabricated in 40-nm CMOS technology, provides CDC resolution of 0.29 fF while dissipating only 0.083 nJ per conversion.

Abstract: An isolator of embodiments includes a ?? analog-digital converter configured to convert an analog signal into a digital signal of one bit and transmit the digital signal of one bit as normal data, a time direction multiplexing circuit configured to perform time direction multiplexing of alternately performing conversion of the normal data into a digital differential signal and transmission of the digital differential signal, and transmission of a special signal different from the normal data, and an insulated transmission circuit configured to transmit the digital differential signal and the special signal transmitted from the time direction multiplexing circuit via an insulating layer.

Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.

Abstract: Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.

Abstract: A method including applying a first excitation voltage to an electrode of a touch sensor which charges a capacitive node associated with the electrode from a first voltage level to a second voltage level that is greater than the first voltage level. A first measurement measures a charge to change from the first voltage level to the second voltage level. A second excitation voltage is applied to the electrode which charges the capacitive node from the second voltage level to a third voltage level that is greater than the second voltage level. The capacitive node is discharged from the third voltage level to a fourth voltage level that is less than the second voltage level. A second measurement measures a charge to change from the third voltage level to the fourth voltage level. A measured charge signal is generated based on the first measurement and the second measurement.

Abstract: An object is to provide a display system with a novel structure and a vehicle. The display system includes a display and a control IC. The control IC includes a frame memory, an arithmetic circuit, and a memory circuit. The display has a curved display surface. The frame memory has a function of holding first image data dedicated to displaying an image on a flat surface. The memory circuit has a function of storing shape data on the display. The arithmetic circuit has a function of converting first coordinates of the curved display surface into second coordinates of the flat surface included in the first image data, by performing arithmetic operation in accordance with the shape data. The arithmetic circuit has a function of outputting the first image data stored in the frame memory to the display as second image data on the basis of the second coordinates.

Abstract: A generation unit generates a plurality of pieces of segment data, and appends an index to each of the plurality of pieces of segment data in a predetermined order. Each piece of the segment data corresponds to each predetermined time period of video data. A reception unit receives, from an external apparatus, an acquisition request which is for the external apparatus to acquire segment data and designate an index of the segment data. In a case where an index of segment data which is generated after a lapse of a predetermined time period or longer from a time when the acquisition request is received by the reception unit is designated by the acquisition request, the generation unit appends the index designated by the acquisition request to the segment data regardless of the predetermined order.

Abstract: Disclosed is a sample and hold circuit and method capable of amplifying an input signal. The method includes: in a sample phase, receiving a first (second) input signal with top electrodes of first (second) capacitors, and receiving the second (first) input signal with all bottom electrode(s) of at least a part of the first (second) capacitors; in a hold phase, stopping receiving the first (second) input signal with the top electrodes of the first (second) capacitors, and receiving a first (second) group of reference signals with the bottom electrodes of the first (second) capacitors, so that the first (second) capacitors provide a first (second) sample voltage on the top electrodes of the multiple first (second) capacitors through charge redistribution, wherein the first and second input signals are a pair of differential signals and they are opposite to each other.

Abstract: Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

Abstract: A solid state imaging element (100) includes: a successive approximation type analog-digital conversion circuit (140) converting an analog pixel signal received from a pixel of a pixel array portion (110) to a digital code; and a first noise detection circuit (130-1) connected to a DAC (Digital to Analog Converter) output node inside the successive approximation type analog-digital conversion circuit (140) and detecting power noise supplied to the pixel of the pixel array portion (110) to output a detection result to the DAC.

Abstract: An output buffer of a super source follower for driving a reference ramp signal of a column-parallel single slope type ADC of a solid-state imaging device is made as a class AB feedback configuration for controlling a feedback variable current source with a signal obtained by amplifying a current fluctuation flowing through an amplification transistor by an amplifier, and thereby, the upper limit of the drain voltage of the amplification transistor is not limited by the voltage between the gate and the source of the feedback variable current source.

Abstract: A signal analysis method comprising: receiving an input signal, the input signal comprising a symbol sequence; receiving samples of a reference signal based on a known sample rate, the reference signal comprising the same symbol sequence as the input signal; determining symbol points of the symbol sequence based on the samples; determining measurement times based on the symbol points; and determining at least one signal quality parameter at the measurement times, wherein the at least one signal quality parameter is indicative of a signal quality of the input signal. Further, a measurement system is described.

Abstract: An audio processing apparatus includes a first input port, a second input port, a first processor that processes an audio signal input to the first input port and that includes a first adjuster which adjusts acoustic characteristics of the audio signal, a second processor that processes an audio signal input to the second input port, and output ports having a first particular output port. In a first operation mode, the first adjuster is set in an effective state and each of an audio signal as processed by the first processor and an audio signal as processed by the second processor is output from one or more of the output ports. In a second operation mode, the first adjuster is set in an ineffective state and an audio signal as processed by the first processor is output from the first particular output port.

Abstract: This transmitter is provided with: a digital delay circuit which delays a 1-bit digital RF signal on the basis of another 1-bit digital RF signal; an amplifier which amplifies a signal output by the digital delay circuit; and a band-pass filter which allows signals in a prescribed frequency band, from among signals output by the amplifier, to pass. A signal output by the band-pass filter is input into a corresponding one antenna element from among a plurality of antenna elements, and controls the directionality of a beam formed by the plurality of antenna elements.

Abstract: A method for data transfer includes establishing a first wireless connection between a transceiver and a handheld device, the transceiver initially operating in an peripheral role and the handheld device operating in a central role; switching a role of both the transceiver and the handheld device in response to establishing the first wireless connection, the transceiver module switching from the peripheral role to the central role, and the handheld device from the central role to the peripheral role; and establishing a second wireless connection between the transceiver and the handheld device subsequent to the switching.

Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs). The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

Abstract: An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.

Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.

Abstract: A method of processing an analog signal includes receiving, into signal processing circuitry from compensation circuitry, an offset compensation signal, the offset compensation signal having (i) a polarity opposite a polarity of a gain error of the signal processing circuitry and (ii) a magnitude equal to a nominal compensation value plus a deviation. The method includes generating, by the signal processing circuitry, an output signal based on an analog signal received into the signal processing circuitry, including applying the offset compensation signal to an intermediate signal generated by the signal processing circuitry. The method includes scaling the output signal based on the deviation between the magnitude of the offset compensation signal and the nominal compensation value.

Abstract: A digital signal may be converted into a spiking analog signal. A different constant current may be applied to each of a plurality of switch circuits. Each bit of the digital signal may be applied to a corresponding one of the plurality of switch circuits. Each switch circuit may apply the corresponding constant current to a common output when the corresponding bit has a predetermined value. Each switch circuit may not apply the corresponding constant current to the common output when the corresponding bit does not have the predetermined value. A common current may be applied at the common output to a spiking neuron circuit.

Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: A sampling device comprises a clock source that provides a clock frequency, a converter with a receiving port for receiving the clock frequency, and a re-sampler located in a digital domain of the sampling device. The clock source is configured to vary the clock frequency over time. The clock source is configured to forward the clock frequency to the converter in order to change a sampling rate of the converter in dependency of the clock frequency. An output sample rate of the sampling device is fixed.

Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). A method of operating an electronic device in a wireless communication system is provided. The method includes inputting training signals into a first loopback route and a second loopback route, determining a loopback gain and a loopback phase, based on a first training signal passing through the first loopback route and a second training signal passing through the second loopback route, determining a frequency domain compensation filter, based on the loopback gain and the loopback phase, determining an FIR filter and a DC offset, based on the frequency domain compensation filter, and compensating for a transmission signal and a reception signal, based on the FIR filter and the DC offset.

Abstract: Methods and systems for an asynchronous successive approximation register analog-to-digital converter with word completion may include a successive approximation register (SAR) analog-to-digital converter (ADC) including a switched capacitor digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector. The SAR ADC may sample a received analog electrical signal using the DAC, and convert the electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator. If the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit. The converting may be initiated using a conversion enable clock pulse generated in the first SAR ADC. The metastability flag may be generated when a conversion enable pulse overlaps with a sampling clock pulse.

Abstract: An encoding and decoding method for an optical isolation amplifier including an encoder, an optical driver, a light source, an optical detector, and a decoder, and employing sigma-delta modulation technology is provided. The method includes: generating a plurality of first pulses, each having a predetermined pulse width, through the encoder when an input digital signal experiences an input pulse rising or falling edge; outputting an encoded signal having the plurality of first pulses to the optical driver; driving the light source through the optical driver, according to the plurality of first pulses, so as to output an encoded optical signal; generating a detected signal through the optical detector detecting the encoded optical signal, and the detected signal has a plurality of second pulses; and duplicating the input digital signal of the encoder through the decoder, according to the detected signal having the plurality of second pulses.

Abstract: Systems and methods may be used to process and output information related to a non-speech vocalization, for example from a user attempting to mimic a non-speech sound. A method may include determine a mimic quality value associated with an audio file by comparing a non-speech vocalization to a prerecorded audio file. For example, the method may include determining an edit distance between the non-speech vocalization and the prerecorded audio file. The method may include assigning a mimic quality value to the audio file based on the edit distance. The method may include outputting the mimic quality value.