Analog To Digital Conversion Followed By Digital To Analog Conversion Patents (Class 341/110)
  • Patent number: 11190201
    Abstract: An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 30, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsuan-Ting Ho, Liang-Wei Huang, Shih-Hsiung Huang
  • Patent number: 11150133
    Abstract: A method of processing an analog signal includes receiving, into signal processing circuitry from compensation circuitry, an offset compensation signal, the offset compensation signal having (i) a polarity opposite a polarity of a gain error of the signal processing circuitry and (ii) a magnitude equal to a nominal compensation value plus a deviation. The method includes generating, by the signal processing circuitry, an output signal based on an analog signal received into the signal processing circuitry, including applying the offset compensation signal to an intermediate signal generated by the signal processing circuitry. The method includes scaling the output signal based on the deviation between the magnitude of the offset compensation signal and the nominal compensation value.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 19, 2021
    Assignee: ams Sensors Germany GmbH
    Inventors: Dalibor Stojkovic, Predrag Micakovic
  • Patent number: 11100389
    Abstract: A digital signal may be converted into a spiking analog signal. A different constant current may be applied to each of a plurality of switch circuits. Each bit of the digital signal may be applied to a corresponding one of the plurality of switch circuits. Each switch circuit may apply the corresponding constant current to a common output when the corresponding bit has a predetermined value. Each switch circuit may not apply the corresponding constant current to the common output when the corresponding bit does not have the predetermined value. A common current may be applied at the common output to a spiking neuron circuit.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: August 24, 2021
    Assignee: ELECTRONIC WARFARE ASSOCIATES, INC.
    Inventors: Dirk Niggemeyer, Lester A. Foster, III
  • Patent number: 11070225
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 20, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 11050495
    Abstract: The disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). A method of operating an electronic device in a wireless communication system is provided. The method includes inputting training signals into a first loopback route and a second loopback route, determining a loopback gain and a loopback phase, based on a first training signal passing through the first loopback route and a second training signal passing through the second loopback route, determining a frequency domain compensation filter, based on the loopback gain and the loopback phase, determining an FIR filter and a DC offset, based on the frequency domain compensation filter, and compensating for a transmission signal and a reception signal, based on the FIR filter and the DC offset.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 29, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tuan Manh Dao, Yuichi Aoki, Yonghoon Kim
  • Patent number: 11050430
    Abstract: A sampling device comprises a clock source that provides a clock frequency, a converter with a receiving port for receiving the clock frequency, and a re-sampler located in a digital domain of the sampling device. The clock source is configured to vary the clock frequency over time. The clock source is configured to forward the clock frequency to the converter in order to change a sampling rate of the converter in dependency of the clock frequency. An output sample rate of the sampling device is fixed.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: June 29, 2021
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Gregor Feldhaus, Alexander Roth
  • Patent number: 11025265
    Abstract: Methods and systems for an asynchronous successive approximation register analog-to-digital converter with word completion may include a successive approximation register (SAR) analog-to-digital converter (ADC) including a switched capacitor digital-to-analog converter (DAC), a word completion block, a comparator, and a metastability detector. The SAR ADC may sample a received analog electrical signal using the DAC, and convert the electrical signal to an n-bit digital signal by evaluating bits from a most significant bit to a least significant bit using the comparator. If the metastability detector determines that a time to evaluate one of the bits is longer than a threshold time, the metastability detector generates a metastability flag for each such bit. The converting may be initiated using a conversion enable clock pulse generated in the first SAR ADC. The metastability flag may be generated when a conversion enable pulse overlaps with a sampling clock pulse.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 1, 2021
    Assignee: Luxtera LLC
    Inventor: Oleksiy Zabroda
  • Patent number: 11025268
    Abstract: An encoding and decoding method for an optical isolation amplifier including an encoder, an optical driver, a light source, an optical detector, and a decoder, and employing sigma-delta modulation technology is provided. The method includes: generating a plurality of first pulses, each having a predetermined pulse width, through the encoder when an input digital signal experiences an input pulse rising or falling edge; outputting an encoded signal having the plurality of first pulses to the optical driver; driving the light source through the optical driver, according to the plurality of first pulses, so as to output an encoded optical signal; generating a detected signal through the optical detector detecting the encoded optical signal, and the detected signal has a plurality of second pulses; and duplicating the input digital signal of the encoder through the decoder, according to the detected signal having the plurality of second pulses.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: June 1, 2021
    Assignee: LITE-ON SINGAPORE PTE. LTD.
    Inventors: You-Fa Wang, Yu-wei Wang, Meng-Tong Tan
  • Patent number: 10965625
    Abstract: Systems and methods may be used to process and output information related to a non-speech vocalization, for example from a user attempting to mimic a non-speech sound. A method may include determine a mimic quality value associated with an audio file by comparing a non-speech vocalization to a prerecorded audio file. For example, the method may include determining an edit distance between the non-speech vocalization and the prerecorded audio file. The method may include assigning a mimic quality value to the audio file based on the edit distance. The method may include outputting the mimic quality value.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 30, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Derrick Fu, Kati Amanda London, James Bigbee Garver, Joseph Edwin Johnson, Jr., Ying Wang, Oussama Elachqar, Zhiying Zhang
  • Patent number: 10957328
    Abstract: This application relates to transfer of microphone data from a microphone (101, 102, 102a, 201) to a processing module, such as voice biometric authentication module (111) in a secure manner, such that the receiving module can trust that the received audio is genuine. An authentication module (203) is configured to receive microphone data (DM) representative of an audio signal received at the microphone (201), and generate from the microphone data, authentication data (DA) for certifying that the microphone data did pass via the authentication module. The first authentication data (DA) comprises information relating to distinguishing characteristics of the audio content of the microphone data and may, for instance be an acoustic fingerprint of the audio content. The authentication data, may be cryptographically signed or encrypted and sent with the microphone audio to allow a receiver to verify that the audio is genuine and the content has not been substantially altered.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: March 23, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Michael Page, Thomas Ivan Harvey, Vitaliy Sapozhnykov
  • Patent number: 10938398
    Abstract: An analog-to-digital converter (ADC) includes a first operator configured to subtract an analog value from an analog signal; an amplifier configured to amplify an output of the first selector; a filter configured to filter an output of the amplifier; a quantizer configured to generate a digital bit stream from an output of the filter; and a digital-to-analog converter (DAC) configured to output the analog value according to the digital bit stream.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 2, 2021
    Assignee: Seoul National University R&DB Foundation
    Inventors: Suhwan Kim, Junsoo Cho, Youngtae Yang
  • Patent number: 10917099
    Abstract: Disclosed are a method and a device for improving an output accuracy of a digital-to-analog converter. The method includes: calculating an output error of the digital-to-analog converter based on output accuracy and an input error of the digital-to-analog converter; obtaining at least one of the output error, comparing the at least one output error against a preset threshold, and adjusting an integer input value of the digital-to-analog converter according to a comparison result.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: February 9, 2021
    Assignee: GUANGDONG DAPU TELECOM TECHNOLOGY CO., LTD.
    Inventors: Hui Zhang, Zhong Yi, Jianbo Lu, Wencai Qiu
  • Patent number: 10911780
    Abstract: In a process of coding multi-viewpoint images, the process is performed at a high speed while the amount of data is suppressed. A distance estimating unit that estimates a distance from a camera array including a plurality of camera units up to a subject, a determination unit that determines the number of first camera units independently coding image data among the plurality of camera units and an arrangement of the first camera units in the camera array based on the distance estimated by the distance estimating unit, and a control unit that operates each of the camera units as the first camera unit or as a second camera unit coding image data of the own camera unit by referring to image data of the first camera unit based on the number and the arrangement of the first camera units determined by the determination unit are included.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: February 2, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koji Ishibashi
  • Patent number: 10877512
    Abstract: The present disclosure relates to an audio data transmission method and apparatus. The method includes: determining a frequency of sampling of audio data to be processed as a clock frequency of a first clock signal; determining a clock frequency of a second clock signal according to the clock frequency of the first clock signal, a number of slots of the audio data to be processed and a preset audio data occupied bit width; determining a duration of a high level in each cycle of the first clock signal according to the clock frequency of the second clock signal and the number of slots; and outputting the processed audio data according to a pulse code modulation (PCM) timing determined by the clock frequency of the first clock signal, the clock frequency of the second clock signal and the duration of the high level in each cycle of the first clock signal.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: December 29, 2020
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventor: Tao Jin
  • Patent number: 10862497
    Abstract: A successive approximation analog-to-digital converter (SAR ADC) and an operation method thereof are provided. The SAR ADC, which alternately operates in a sampling phase and a comparison and switching phase, includes a switch-capacitor digital-to-analog converter (DAC), a comparator, a successive approximation register and a control circuit. The switch-capacitor DAC including multiple capacitors. The control circuit is configured to (A) control a top plate of a first capacitor and a top plate of a second capacitor to be coupled to an analog input signal during the sampling phase; (B) control the first capacitor and the second capacitor to be active and inactive, respectively, in the comparison and switching phase according to a reference code after the sampling phase finishes; and (C) switch a terminal voltage of at least one of the capacitors during the comparison and switching phase according to the comparison results of the comparator.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 8, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Sheng-Hsiung Lin
  • Patent number: 10838385
    Abstract: Method for automatic switching of a communication resistor of a HART device in or out, wherein the method comprises steps as follows: transmitting a test signal on an electrical current loop; reading from the electrical current loop a test voltage signal, which is based on the transmitted test signal; comparing the test voltage signal with a reference signal; connecting the communication resistor into the electrical current loop when the test voltage signal exceeds the reference signal.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: November 17, 2020
    Assignee: Endress+Hauser Process Solutions AG
    Inventors: Fabian Bihler, Marc Fiedler
  • Patent number: 10840932
    Abstract: A noise-shaping successive approximation analog-to-digital converter (NS-SAR ADC) using a passive noise-shaping technique with 1-input-pair SAR comparator is introduced. A residue sampling and integration circuit is coupled between a DAC and the comparator, for sampling a residue voltage generated by the DAC and charge-sharing of the sampled residue voltage. A first integral capacitor is coupled between a first input terminal of a comparator and a first output terminal of a DAC. After a first residue capacitor samples a residue generated by the DAC, the first residue capacitor is coupled to the first integral capacitor for charge-sharing of the residue voltage.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: November 17, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ying-Zu Lin, Chin-Yu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu
  • Patent number: 10832627
    Abstract: A display apparatus, a source driver of the display apparatus and an operating method of the source driver are provided. The display apparatus includes a display panel, at least one gate driver and a plurality of source drivers. The display panel includes a plurality of source lines and a plurality of gate lines. A plurality of output terminals of the gate driver are coupled to the gate lines in one-to-one manner. A plurality of output terminals of the source drivers are coupled to the source lines in one-to-one manner to provide a plurality of source driving voltages to the source lines. The source driving voltages include different coarse compensation voltages. The coarse compensation voltages are respectively configured based on distances between the source drivers which control the source lines and input terminals of the gate lines of the display panel.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: November 10, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jhih-Siou Cheng, Yi-Chuan Liu
  • Patent number: 10797661
    Abstract: A capacitive-coupled chopper instrumentation amplifier includes a first chopper, a first gain stage, a capacitive isolation stage electrically coupled between inputs of the first gain stage and the first chopper, a second gain stage, a second chopper electrically coupled between outputs of the first gain stage and inputs of the second gain stage, clamping circuitry electrically coupled between the inputs of the first gain stage and a reference voltage rail, and a controller. The controller is configured to (a) detect a change in a first common-mode voltage exceeding a threshold value, the first common-mode voltage being a common-mode voltage at the inputs of the amplifier, and (b) in response to detecting the change in the first common-mode voltage exceeding the threshold value, cause the clamping circuitry to clamp the inputs of the first gain stage to the reference voltage rail.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 6, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Yuan Chen, Daihong Fu, Jun Wu
  • Patent number: 10763879
    Abstract: Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 1, 2020
    Assignee: XILINX, INC.
    Inventor: Pedro W. Neto
  • Patent number: 10742228
    Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: August 11, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10742801
    Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: August 11, 2020
    Assignee: Global Tel*Link Corporation
    Inventor: Stephen Lee Hodge
  • Patent number: 10735018
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10725346
    Abstract: A liquid crystal display includes first and second voltage divider reference lines, first and second pixel electrodes, and first and second switching circuits. The first and second voltage divider reference lines are on different layers and extend in different directions. The first pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, that receives a voltage lower than a voltage to be applied to the first sub-pixel electrode. The second pixel electrode includes a third sub-pixel electrode and a fourth sub-pixel electrode, that receives a voltage lower than a voltage to be applied to the third sub-pixel electrode. The first switching circuit is connected to the first voltage divider reference line, and the second switching circuit is connected to the second voltage divider reference line.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang Yong No, Kwi Hyun Kim
  • Patent number: 10713108
    Abstract: Explicit and implicit feedback information, that is indicative of an issue in a deployed computing system, is collected. Information identifying attempted resolutions for the issue is collected as well. A knowledge base is generated that identifies issues and successful resolutions for those issues. During runtime, issues are detected, either explicitly or implicitly, and the knowledge base is accessed to determine whether a resolution has already been identified. If so, it can be proactively provided to the computing system to address the issue.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 14, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Satish J. Thomas, Murtaza Muidul Huda Chowdhury, Shefy Manayil Kareem
  • Patent number: 10699628
    Abstract: An object is to provide a display system with a novel structure and a vehicle. The display system includes a display and a control IC. The control IC includes a frame memory, an arithmetic circuit, and a memory circuit. The display has a curved display surface. The frame memory has a function of holding first image data dedicated to displaying an image on a flat surface. The memory circuit has a function of storing shape data on the display. The arithmetic circuit has a function of converting first coordinates of the curved display surface into second coordinates of the flat surface included in the first image data, by performing arithmetic operation in accordance with the shape data. The arithmetic circuit has a function of outputting the first image data stored in the frame memory to the display as second image data on the basis of the second coordinates.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda
  • Patent number: 10693486
    Abstract: An apparatus and method for an asynchronous successive approximation analog-to-digital converter that includes a digital-to-analog converter, a comparator with adjustable integration time electrically coupled to the digital-to-analog converter, and control circuitry electrically coupled to the digital-to-analog converter and the comparator, the control circuitry configured to adjust an integration time of the comparator one or more times during a conversion cycle.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 23, 2020
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventor: Yen-Jen Ko
  • Patent number: 10680596
    Abstract: A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Lei Sun, Ganesh Kiran, Seyed Arash Mirhaj
  • Patent number: 10672492
    Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating an input data stream according to the differential signal; sampling a clock signal according to a plurality of turning points of the input data stream and outputting a sampling signal; and outputting a bit data stream corresponding to the input data stream according to the sampling signal.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 2, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Chih-Ming Chen
  • Patent number: 10558189
    Abstract: A safety control system for switching on and safely switching off at least one actuator, including at least one input module for evaluating an input signal of a safety transmitter and for generating an output signal, and at least one output module for the safe actuation of the at least one actuator as a function of the output signal of the input module. The input signal has different signal parameters as a function of the type of safety transmitter. Furthermore, the safety control system includes a setting unit having a memory in which the signal parameters for the input module are stored, and the input module evaluates the input signal as a function of the signal parameters.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: February 11, 2020
    Assignee: PILZ GMBH & CO. KG
    Inventors: Thilo Hutt, Dietmar Seizinger, Marco Kluge, Stephan Lehmann
  • Patent number: 10554181
    Abstract: An electronic circuit comprises a comparator circuit including an input circuit stage and an output circuit stage, and an input stage supply circuit coupled to a circuit supply rail and the input circuit stage. The input stage supply circuit includes a voltage generator circuit and a regulating circuit. The voltage generator circuit includes a replicate circuit of a portion of the input circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit. The regulating circuit generates a regulated input stage supply using the generated voltage.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 4, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Debopam Banerjee, Maitrey Kamble, Sandeep Monangi, Michael C. W. Coln
  • Patent number: 10555102
    Abstract: According to some embodiments of the present invention there is provided a method of using an earphone output speaker as a microphone for a phone call between two and/or more participants, or for measuring biometric data of a user. The method may comprise playing a received signal to an electro-acoustic output transducer of an earphone. The method may comprise instructing an audio processing circuit of a local client terminal to record an audio signal from the same electro-acoustic output transducer. The method may comprise calculating a voice signal and/or a biometric measurement based on a function combining the recorded audio signal, the received signal, and filtration coefficients, using a processing unit of the local client terminal. The method may comprise sending the voice signal and/or a biometric measurement through an output interface of the local client terminal.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 4, 2020
    Assignee: Bugatone Ltd.
    Inventors: Edmund Ben-Ami, Noam Petrank
  • Patent number: 10547478
    Abstract: Disclosed are a method for signal modulation based on pulse density modulation and an apparatus therefore. The method for signal modulation is performed in an apparatus for modulating a signal based on pulse density modulation and includes performing pulse density modulation on an analog signal input to the apparatus through a pulse density modulator of the apparatus, converting a bandwidth of the pulse density modulated signal into a bandwidth required for the apparatus through a correlative encoder of the apparatus, transmitting the bandwidth converted signal to a radio frequency (RF) unit of the apparatus based on an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) converter of the apparatus, filtering a frequency band of the bandwidth converted signal and outputting the frequency band filtered signal via the RF unit.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 28, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Hyun Jang, Sun Woo Kong, Kwang Seon Kim, Myung Don Kim, Hui Dong Lee
  • Patent number: 10541700
    Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Narasimhan Rajagopal, Shagun Dusad, Viswanathan Nagarajan, Visvesvaraya Appala Pentakota
  • Patent number: 10541466
    Abstract: A mobile terminal and manufacture of same are provided. The mobile terminal includes: an antenna; a first case at which the antenna is disposed; a second case coupled to the first case; a main PCB disposed at one side of the second case; and a sub-PCB disposed at an opposite side of the second case, the sub-PCB being connected to the main PCB through a cable, wherein the sub-PCB is electrically coupled with the antenna when the first case and the second case are coupled together.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju Hwan Yun
  • Patent number: 10524082
    Abstract: Methods and apparatus are provided for automatically adjusting, by an audio device, the SPL of its audio output. As described herein, the SPL is adjusted based on approximated noise in an ear canal of occluded ears as determined by an accelerometer measuring the user's motion. According to aspects, the audio device adjusts a tone of the signal by adjusting the SPL of a set of frequencies and also adjusts the overall gain of the full frequency spectrum of the audio signal. The tone may be adjusted more quickly as compared to the overall broadband gain.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: December 31, 2019
    Assignee: BOSE CORPORATION
    Inventors: Grace Carroll, Dale McElhone, Christopher R. Paetsch
  • Patent number: 10484001
    Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.
    Type: Grant
    Filed: December 15, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rishi Soundararajan, Visvesvaraya Pentakota, Anand Jerry George
  • Patent number: 10469965
    Abstract: In embodiments of the present invention improved capabilities are described for digitally transmitting audio that is converted from analog audio received from analog media pickup devices in a live performance venue by a stage box to a base unit over off-the-shelf twisted pair cable while sending pre-amplification control signals and power over the cable to the stage box. Audio for the performance venue is remotely managed from a virtual audio engineering mixing board that wirelessly communicates audio control commands to the stage box from a handheld computing device.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: November 5, 2019
    Assignee: En Technology Corporation
    Inventor: Fred W. Heineman
  • Patent number: 10444299
    Abstract: A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 15, 2019
    Assignee: Allegro MicroSystems, LLC
    Inventors: Hernán D. Romero, Octavio H. Alpago
  • Patent number: 10447956
    Abstract: Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: October 15, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Nobutaka Shimamura, Kazuhisa Suzuki
  • Patent number: 10425014
    Abstract: An AC/DC converter including: an H bridge; an inductance in series with an input of the bridge; an inductance in series with an output of the bridge; and a circuit capable of controlling the bridge alternately to a first configuration where first and second diagonals of the bridge are respectively conductive and non-conductive, and to a second complementary configuration, the circuit being capable, during a phase of transition between the first and second configurations, of: turning on a first switch of the second diagonal; turning off a first switch of the first diagonal when the current flowing through this switch takes a zero value; turning on the second switch of the second diagonal; and turning off the second switch of the first diagonal when the current flowing through this switch takes a zero value.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 24, 2019
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Léo Sterna, Othman Ladhari, Jean-Paul Ferrieux, David Frey, Pierre-Olivier Jeannin
  • Patent number: 10417460
    Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 17, 2019
    Assignee: AREANNA INC.
    Inventor: Behdad Youssefi
  • Patent number: 10404259
    Abstract: A circuit device includes a register that stores result data, a D/A converter that executes D/A conversion on the result data so as to output a D/A conversion voltage, a comparator that compares an input voltage with the D/A conversion voltage, and a processing circuit that executes an update process on the result data through a determination process based on a comparison result from the comparison portion, so as to obtain A/D conversion result data of the input voltage, in which the processing circuit executes the determination process on an MSB side of the A/D conversion result data in a first determination period, and executes the determination process on an LSB side of the A/D conversion result data in a second determination period longer than the first determination period.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: September 3, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Shinnosuke Kano
  • Patent number: 10404304
    Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 3, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Raja Pullela, Sheng Ye, Morten Damgaard
  • Patent number: 10331282
    Abstract: In some aspects of the present disclosure, a touch-panel interface includes a plurality of receivers, wherein each of the receivers is coupled to one or more receive lines of a touch panel, and each of the receivers includes a switch capacitor network and an amplifier. The touch-panel interface also includes controller configured to control switches in the switch capacitor network of each of one or more of the receivers to operate each of the one or more of the receivers in one of a plurality of different receiver modes.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Mohamed Imtiaz Ahmed, Dustin Tarl Dunwell, William Martin Snelgrove, Ayaz Hasan, Matthew David James
  • Patent number: 10320994
    Abstract: Data files with digital envelops may be used for many new applications for cloud computing. The new applications include games and entertainments such as digital fortune cookies, and treasure hunting, unique techniques for digital right management, or even additional privacy and survivability on data storage and transport on cloud computing. Wavefront multiplexing/demultiplexing process (WF muxing/demuxing) embodying an architecture that utilizes multi-dimensional waveforms has found applications in data storage and transport on cloud. Multiple data sets are preprocessed by WF muxing before stored/transported. WF muxed data is aggregated data from multiple data sets that have been “customized processed” and disassembled into any scalable number of sets of processed data, with each set being stored on a storage site. The original data is reassembled via WF demuxing after retrieving a lesser but scalable number of WF muxed data sets.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: June 11, 2019
    Assignee: SPATIAL DIGITAL SYSTEMS, INC.
    Inventors: Donald C. D. Chang, Juo-Yu Lee
  • Patent number: 10298257
    Abstract: A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 21, 2019
    Assignee: NXP USA, INC.
    Inventors: Brandt Braswell, Douglas Alan Garrity, Paul Rene DeRouen
  • Patent number: 10291249
    Abstract: An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: May 14, 2019
    Assignee: Analog Devices, Inc.
    Inventor: Michael C. W. Coln
  • Patent number: 10263633
    Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 16, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, David Paul Singleton
  • Patent number: RE47601
    Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: September 10, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Bernd Schafferer, Bing Zhao