Abstract: A noise-shaping successive approximation analog-to-digital converter (NS-SAR ADC) using a passive noise-shaping technique with 1-input-pair SAR comparator is introduced. A residue sampling and integration circuit is coupled between a DAC and the comparator, for sampling a residue voltage generated by the DAC and charge-sharing of the sampled residue voltage. A first integral capacitor is coupled between a first input terminal of a comparator and a first output terminal of a DAC. After a first residue capacitor samples a residue generated by the DAC, the first residue capacitor is coupled to the first integral capacitor for charge-sharing of the residue voltage.

Abstract: Method for automatic switching of a communication resistor of a HART device in or out, wherein the method comprises steps as follows: transmitting a test signal on an electrical current loop; reading from the electrical current loop a test voltage signal, which is based on the transmitted test signal; comparing the test voltage signal with a reference signal; connecting the communication resistor into the electrical current loop when the test voltage signal exceeds the reference signal.

Abstract: A display apparatus, a source driver of the display apparatus and an operating method of the source driver are provided. The display apparatus includes a display panel, at least one gate driver and a plurality of source drivers. The display panel includes a plurality of source lines and a plurality of gate lines. A plurality of output terminals of the gate driver are coupled to the gate lines in one-to-one manner. A plurality of output terminals of the source drivers are coupled to the source lines in one-to-one manner to provide a plurality of source driving voltages to the source lines. The source driving voltages include different coarse compensation voltages. The coarse compensation voltages are respectively configured based on distances between the source drivers which control the source lines and input terminals of the gate lines of the display panel.

Abstract: A capacitive-coupled chopper instrumentation amplifier includes a first chopper, a first gain stage, a capacitive isolation stage electrically coupled between inputs of the first gain stage and the first chopper, a second gain stage, a second chopper electrically coupled between outputs of the first gain stage and inputs of the second gain stage, clamping circuitry electrically coupled between the inputs of the first gain stage and a reference voltage rail, and a controller. The controller is configured to (a) detect a change in a first common-mode voltage exceeding a threshold value, the first common-mode voltage being a common-mode voltage at the inputs of the amplifier, and (b) in response to detecting the change in the first common-mode voltage exceeding the threshold value, cause the clamping circuitry to clamp the inputs of the first gain stage to the reference voltage rail.

Abstract: Apparatus and associated methods relate to a clock generation circuit which generates asynchronous clock signals for a successive approximation ADC architecture based on time-interleaved comparators. In an illustrative example, a circuit may include (a) a first comparator configured to receive an input signal and generate a first ready signal to indicate a comparison decision being complete, (b) a second comparator configured to receive the input signal and generate a second ready signal to indicate a comparison decision being complete, and (c) a clock generation circuit coupled to receive the first and the second ready signals and generate a first clock for the first comparator and a second clock for the second comparator. The first and the second clock signals may be in anti-phase. Thus, each comparator may have enough time to reach a valid comparison in each successive approximation cycle, and kickback noises at comparator' inputs may be advantageously reduced.

Abstract: An analog to digital converter (ADC) is disclosed. The ADC includes a DAC which generates a first signal based on an analog input and a digital input word, and a comparator which generates a comparator output having a value corresponding with a sign of a difference between first and second signals. During a first time period, the second signal is equal to a reference signal, the first signal is equal to an analog input, and the comparator generates a first comparator output. During a second time period, the second signal is equal to the reference signal, the first signal is equal to a the analog input plus a predetermined signal, and the comparator generates a second comparator output. A SAR logic circuit generates the digital input word for the DAC based on the first and second comparator outputs.

Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.

Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi

Abstract: A liquid crystal display includes first and second voltage divider reference lines, first and second pixel electrodes, and first and second switching circuits. The first and second voltage divider reference lines are on different layers and extend in different directions. The first pixel electrode includes a first sub-pixel electrode and a second sub-pixel electrode, that receives a voltage lower than a voltage to be applied to the first sub-pixel electrode. The second pixel electrode includes a third sub-pixel electrode and a fourth sub-pixel electrode, that receives a voltage lower than a voltage to be applied to the third sub-pixel electrode. The first switching circuit is connected to the first voltage divider reference line, and the second switching circuit is connected to the second voltage divider reference line.

Abstract: Explicit and implicit feedback information, that is indicative of an issue in a deployed computing system, is collected. Information identifying attempted resolutions for the issue is collected as well. A knowledge base is generated that identifies issues and successful resolutions for those issues. During runtime, issues are detected, either explicitly or implicitly, and the knowledge base is accessed to determine whether a resolution has already been identified. If so, it can be proactively provided to the computing system to address the issue.

Abstract: An object is to provide a display system with a novel structure and a vehicle. The display system includes a display and a control IC. The control IC includes a frame memory, an arithmetic circuit, and a memory circuit. The display has a curved display surface. The frame memory has a function of holding first image data dedicated to displaying an image on a flat surface. The memory circuit has a function of storing shape data on the display. The arithmetic circuit has a function of converting first coordinates of the curved display surface into second coordinates of the flat surface included in the first image data, by performing arithmetic operation in accordance with the shape data. The arithmetic circuit has a function of outputting the first image data stored in the frame memory to the display as second image data on the basis of the second coordinates.

Abstract: An apparatus and method for an asynchronous successive approximation analog-to-digital converter that includes a digital-to-analog converter, a comparator with adjustable integration time electrically coupled to the digital-to-analog converter, and control circuitry electrically coupled to the digital-to-analog converter and the comparator, the control circuitry configured to adjust an integration time of the comparator one or more times during a conversion cycle.

Abstract: A bootstrapped switch circuit includes an auxiliary loop circuit for assisting the boosting of a bootstrap voltage in a main loop circuit having a bootstrapped switch transistor. The boosted bootstrap voltage switches on the bootstrapped switch transistor so that an input voltage signal may conduct through the bootstrapped switch transistor to charge a sampling node.

Abstract: A data sampling circuit module, a data sampling method and a memory storage device are provided. The method includes: receiving a differential signal and generating an input data stream according to the differential signal; sampling a clock signal according to a plurality of turning points of the input data stream and outputting a sampling signal; and outputting a bit data stream corresponding to the input data stream according to the sampling signal.

Abstract: A safety control system for switching on and safely switching off at least one actuator, including at least one input module for evaluating an input signal of a safety transmitter and for generating an output signal, and at least one output module for the safe actuation of the at least one actuator as a function of the output signal of the input module. The input signal has different signal parameters as a function of the type of safety transmitter. Furthermore, the safety control system includes a setting unit having a memory in which the signal parameters for the input module are stored, and the input module evaluates the input signal as a function of the signal parameters.

Abstract: According to some embodiments of the present invention there is provided a method of using an earphone output speaker as a microphone for a phone call between two and/or more participants, or for measuring biometric data of a user. The method may comprise playing a received signal to an electro-acoustic output transducer of an earphone. The method may comprise instructing an audio processing circuit of a local client terminal to record an audio signal from the same electro-acoustic output transducer. The method may comprise calculating a voice signal and/or a biometric measurement based on a function combining the recorded audio signal, the received signal, and filtration coefficients, using a processing unit of the local client terminal. The method may comprise sending the voice signal and/or a biometric measurement through an output interface of the local client terminal.

Abstract: An electronic circuit comprises a comparator circuit including an input circuit stage and an output circuit stage, and an input stage supply circuit coupled to a circuit supply rail and the input circuit stage. The input stage supply circuit includes a voltage generator circuit and a regulating circuit. The voltage generator circuit includes a replicate circuit of a portion of the input circuit stage to generate a voltage that is less than a voltage of the circuit supply rail and varies with the voltage of the circuit supply rail and device parameters of the replicate circuit. The regulating circuit generates a regulated input stage supply using the generated voltage.

Abstract: Disclosed are a method for signal modulation based on pulse density modulation and an apparatus therefore. The method for signal modulation is performed in an apparatus for modulating a signal based on pulse density modulation and includes performing pulse density modulation on an analog signal input to the apparatus through a pulse density modulator of the apparatus, converting a bandwidth of the pulse density modulated signal into a bandwidth required for the apparatus through a correlative encoder of the apparatus, transmitting the bandwidth converted signal to a radio frequency (RF) unit of the apparatus based on an electrical-to-optical (E/O) converter and an optical-to-electrical (O/E) converter of the apparatus, filtering a frequency band of the bandwidth converted signal and outputting the frequency band filtered signal via the RF unit.

Abstract: A mobile terminal and manufacture of same are provided. The mobile terminal includes: an antenna; a first case at which the antenna is disposed; a second case coupled to the first case; a main PCB disposed at one side of the second case; and a sub-PCB disposed at an opposite side of the second case, the sub-PCB being connected to the main PCB through a cable, wherein the sub-PCB is electrically coupled with the antenna when the first case and the second case are coupled together.

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Abstract: Methods and apparatus are provided for automatically adjusting, by an audio device, the SPL of its audio output. As described herein, the SPL is adjusted based on approximated noise in an ear canal of occluded ears as determined by an accelerometer measuring the user's motion. According to aspects, the audio device adjusts a tone of the signal by adjusting the SPL of a set of frequencies and also adjusts the overall gain of the full frequency spectrum of the audio signal. The tone may be adjusted more quickly as compared to the overall broadband gain.

Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.

Abstract: In embodiments of the present invention improved capabilities are described for digitally transmitting audio that is converted from analog audio received from analog media pickup devices in a live performance venue by a stage box to a base unit over off-the-shelf twisted pair cable while sending pre-amplification control signals and power over the cable to the stage box. Audio for the performance venue is remotely managed from a virtual audio engineering mixing board that wirelessly communicates audio control commands to the stage box from a handheld computing device.

Abstract: Analog-to-digital converter (ADC) circuitry may receive multiple analog signals and output corresponding digital signals. During the conversion process, comparators may receive the analog signals and a ramp waveform and compare the two inputs to generate logic signals. The logic signals correspond to digital signals that are outputted by ADC circuitry. To enable offset distribution capabilities, offset distribution circuitry may be selectively coupled to the inputs of the comparators. The offset distribution circuitry may include switches that couples a voltage supply providing reference voltages to the comparators. The reference voltages may be conveyed via a capacitor to the comparators as offset voltages. The offset voltages may provide may be different for different ADC units to offset power consumption of different ADC units and reduce power surges in power sources coupled to ADC circuitry.

Abstract: A sensor circuit is provided with a chopper-stabilized amplifier circuit configured to receive a signal from at least one magnetic sensing element, a sigma-delta modulator (SDM) configured to receive a signal from the chopper-stabilized amplifier circuit, and a feedback circuit configured to reduce ripple in a signal generated by the chopper-stabilized amplifier circuit. The feedback circuit includes a demodulator to demodulate a signal from the SDM in a digital domain by inverting a bit stream of the signal from the SDM according to a frequency chopping rate, a digital integrator configured to integrate an output signal of the demodulator to form an integrated signal, and a digital-to-analog converter (DAC) configured to convert the integrated signal to an analog signal and provide the analog signal to the chopper-stabilized amplifier circuit.

Abstract: An AC/DC converter including: an H bridge; an inductance in series with an input of the bridge; an inductance in series with an output of the bridge; and a circuit capable of controlling the bridge alternately to a first configuration where first and second diagonals of the bridge are respectively conductive and non-conductive, and to a second complementary configuration, the circuit being capable, during a phase of transition between the first and second configurations, of: turning on a first switch of the second diagonal; turning off a first switch of the first diagonal when the current flowing through this switch takes a zero value; turning on the second switch of the second diagonal; and turning off the second switch of the first diagonal when the current flowing through this switch takes a zero value.

Abstract: Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. This Abstract is not intended to limit the scope of the claims.

Abstract: A circuit device includes a register that stores result data, a D/A converter that executes D/A conversion on the result data so as to output a D/A conversion voltage, a comparator that compares an input voltage with the D/A conversion voltage, and a processing circuit that executes an update process on the result data through a determination process based on a comparison result from the comparison portion, so as to obtain A/D conversion result data of the input voltage, in which the processing circuit executes the determination process on an MSB side of the A/D conversion result data in a first determination period, and executes the determination process on an LSB side of the A/D conversion result data in a second determination period longer than the first determination period.

Abstract: Methods and systems for a baseband cross-bar may comprise receiving one or more radio frequency (RF) signals in a wireless communication device via antennas coupled to a plurality of receiver paths in the wireless device. The received RF signals may be converted to baseband frequencies. One or more of the down-converted signals may be coupled to receiver paths utilizing a baseband cross-bar. The baseband cross-bar may comprise a plurality of switches, which may comprise CMOS transistors. In-phase and quadrature signals may be processed in the one or more of the plurality of receiver paths. The one or more RF signals comprise cellular signals and/or global navigation satellite signals. A single-ended received RF signal may be converted to a differential signal in one or more of the plurality of receiver paths. The baseband cross-bar may be controlled utilizing a reduced instruction set computing (RISC) processor.

Abstract: In some aspects of the present disclosure, a touch-panel interface includes a plurality of receivers, wherein each of the receivers is coupled to one or more receive lines of a touch panel, and each of the receivers includes a switch capacitor network and an amplifier. The touch-panel interface also includes controller configured to control switches in the switch capacitor network of each of one or more of the receivers to operate each of the one or more of the receivers in one of a plurality of different receiver modes.

Abstract: Data files with digital envelops may be used for many new applications for cloud computing. The new applications include games and entertainments such as digital fortune cookies, and treasure hunting, unique techniques for digital right management, or even additional privacy and survivability on data storage and transport on cloud computing. Wavefront multiplexing/demultiplexing process (WF muxing/demuxing) embodying an architecture that utilizes multi-dimensional waveforms has found applications in data storage and transport on cloud. Multiple data sets are preprocessed by WF muxing before stored/transported. WF muxed data is aggregated data from multiple data sets that have been “customized processed” and disassembled into any scalable number of sets of processed data, with each set being stored on a storage site. The original data is reassembled via WF demuxing after retrieving a lesser but scalable number of WF muxed data sets.

Abstract: A method for Signal-to-Noise and Distortion Ratio (SNDR) improvement through optimal Digital-to-Analog-Converter (DAC) element selection includes randomizing an order of a plurality of unit elements of a DAC, wherein each of the unit elements is controlled by a respective one of a plurality of digital inputs of the DAC. The plurality of digital inputs is sequentially asserted over at least a subset of a full set of the digital inputs to generate a plurality of analog values of an output of the DAC. A first SNDR of the DAC is measured from the plurality of analog values. A maximum SNDR, corresponding to an optimal order, is determined from the first SNDR and at least one previously measured SNDR. The optimal order of the unit elements of the DAC is stored in a memory to define connections between the digital inputs and the respective unit elements based on the optimal order.

Abstract: An analog-to-digital converter (ADC) circuit comprises a first digital-to-analog (DAC) circuit and a second DAC circuit, wherein the first and second DAC circuits include weighted bit capacitors and reservoir capacitors; a sampling circuit configured to sample a differential input voltage onto the weighted bit capacitors and to sample a reference voltage onto the reservoir capacitors; a comparator circuit operatively coupled to outputs of the first and DAC circuits; and logic circuitry configured to: initiate successive bit trials of weighted bit capacitors to convert the input voltage to a digital value by comparing an output of the first DAC circuit and an output of second DAC circuit using the comparator circuit; and apply charge of the reservoir capacitors to the bit capacitors to reduce the comparator differential input voltage and reduce an error between the input common mode offset and the comparator common mode offset.

Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).

Abstract: Disclosed herein are some continuous time systems and methods. Some of the disclosed systems and methods use a continuous-time analog-to-digital converter (ADC) configured to receive an analog input and to generate an ADC output, a continuous-time digital signal processor configured to receive the ADC output and generate one or more digital outputs, one or more digital-to-analog converters configured to receive the one or more digital outputs, each digital-to-analog converter configured to receive a corresponding digital output and generate an analog output, and an adder configured to receive the analog outputs of the one or more digital-to-analog converters and to generate a summed analog output.

Abstract: A hardware compression architecture including a shift register including: a plurality of sequentially coupled stages and a window stage coupled at an output end of the shift register, the shift register configured to receive an uncompressed data stream at an input end and output the uncompressed data from the window stage; a plurality of comparators each coupled to receive a data value held in a corresponding stage of the shift register and a data value held in the window stage, each of the comparators being configured to output a comparison result indicating whether the received stage value and the window stage data value match; logic, coupled to the comparators to receive the comparison results, to selectively compute one or more indexes based on the comparisons; and an encoder coupled to receive the one or more indexes and output, based on the one or more indexes, a position of a matching data value and a length of a matching sequence of data values.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: According to one embodiment, an analog-to-digital converter includes a first digital-to-analog converter, a comparator configured to digitally output based on a first clock signal, a clock generator configured to generate the first clock signal from an input clock signal, and a controller configured to control the first digital-to-analog converter. The clock generator sets a cycle of the first clock signal to a first cycle if the input clock signal is at a first logic level, and sets the cycle of the first clock signal to a second cycle shorter than the first cycle if the input clock signal is at a second logic level.

Abstract: A system for detecting inmate to inmate conference calls in a correctional facility is disclosed herein. The system includes a database and a conference call detection server, wherein the conference call detection server is configured to monitor a plurality of inmate communications, convert an audio signal of each inmate communication to a frequency domain signal, identify frequency data comprising one or more frequency peaks and corresponding frequency values in the frequency domain signal for each inmate communication, generate a record comprising the frequency data for each inmate communication, resulting in a plurality of records, store the plurality of records in the database, detect an inmate to inmate conference call by matching a frequency subset of a new inmate communication with frequency data in a detected record in the database, and verify the inmate to inmate conference call by matching audio with voice biometric samples.

Abstract: In some embodiments, a DFE including: an input terminal configured to receive an input signal carrying a plurality of symbols; an adder circuit coupled to the input terminal of the DFE; a plurality of comparator circuits configured to receive respective threshold signals; a plurality of slicer circuits coupled to respective comparator circuits of the plurality of comparator circuits; and a plurality of multiplier circuits coupled to respective slicer circuits of the plurality of slicer circuits, the plurality of multiplier circuits configured to multiply respective correction coefficients of a plurality of correction coefficients times respective outputs of respective slicer circuits to produce respective multiplication results of a plurality of multiplication results, where: the adder circuit is configured to subtract the plurality of multiplication results from the input signal, and the plurality of correction coefficients are independently adjusted based on a previously received symbol.

Abstract: In one aspect, the disclosure features systems for providing auditory signals to a subject. The systems include a sensor front-end circuit configured to be connected to an acoustic sensor and to convert analog signals received from the acoustic sensor to digital electric signals. The systems further include a sound processor circuit configured to be connected to the sensor front-end circuit and receive the electric signals provided by the sensor front end circuit. The sound processor includes multiple filters that spectrally decompose the received electrical signals into multiple spectral channels during operation of the system. The multiple spectral channels include at least a low frequency channel and a high frequency channel and the sound processor circuit is configured to operate the low frequency channel at a sample rate lower than a sample rate of the high frequency channel.

Abstract: Technologies for secure presence assurance include a computing device having a presence assertion circuitry that receives an input seed value and generates a cryptographic hash based on the received input seed value. The computing device further verifies the integrity of the presence assertion circuitry based on the generated cryptographic hash.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: A wireless user equipment (UE) device may include a receiver and transmitter. The UE device may dynamically vary the fidelity requirements imposed on the analog signal processing performed by the receiver and/or the transmitter in response factors such as: amount of signal interference (e.g., out-of-band signal power); modulation and coding scheme; number of spatial streams; extent of transmitter leakage; and size and/or frequency location of resources allocated to the UE device. Thus, the UE device may consume less power on average than a UE device that is designed to satisfy fixed fidelity requirements associated with a worst case reception scenario and/or a worst case transmission scenario.

Abstract: Systems and methods for suppressing transmitter noise in a receive band of a co-located receiver that are suitable for wideband applications are disclosed. In one embodiment, a transmitter is configured to upconvert and amplify a digital transmit signal to provide an analog radio frequency transmit signal at an output of the transmitter that includes a desired signal in a transmit band of the transmitter and transmitter noise in a receive band of a main receiver. The main receiver is configured to amplify, downconvert, and digitize an analog radio frequency receive signal to provide a digital receive signal. The digital feedforward transmit noise cancellation subsystem is configured to process the digital transmit signal to generate a digital transmitter noise cancellation signal that is representative of the transmitter noise in the receive band and is subtracted from the digital receive signal to thereby provide a compensated digital receive signal.

Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.

Abstract: Methods and apparatus disclosed herein implement or otherwise embody a technique that compensates for cyclic position errors in encoder-based position detection, wherein the cyclic position errors arise from the presence of harmonic components in the encoder signals relied upon for position determination. Using position-domain compensation for errors arising in the encoder domain offers computational simplicity and impressive compensation performance, even when compensating for a plurality of higher harmonics in the encoder signals, e.g., third harmonic, fifth harmonic, etc. Consequently, even high-precision position monitoring or control can use relatively inexpensive types of encoders known to output encoder signals having significant harmonic components.

Abstract: Systems and methods for linking time-based media and temporal metadata provide single command control during editing of media having associated temporal metadata. A single control enables an editor to switch between monitoring both source media and its corresponding temporal metadata and monitoring both a pre-recorded version of the media and its corresponding temporal metadata. Another single control enables an editor to start and stop the recording of a source media track and its corresponding source temporal metadata. In one application, the editing is performed for media tracks having time-based spatial metadata for playback in immersive environments with the spatial metadata defining an apparent location of sound objects within the immersive environment.

Abstract: A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that includes a plurality of switches coupled to receive differential digital control signals and to provide first and second differential current outputs, a current source coupled to an upper rail and to a first node of the switching circuit, a first current sink coupled to a lower rail and to a second node of the switching circuit, and an interference cancellation circuit coupled to substantially prevent a tail capacitance current from flowing through the first and second differential current outputs.

Abstract: The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).