Abstract: A signal calibration circuit and a signal calibration method are provided. The signal calibration circuit includes: an analog-to-digital conversion circuit, coupled to an output terminal of the circuit to be tested, obtaining an analog signal output by the circuit to be tested and transforming the analog signal into a digital signal; a calibration signal generation circuit, generating a calibration signal, modifying the calibration signal according to a first signal, and outputting a modified calibration signal; and a calibration circuit, coupled to the analog-to-digital conversion circuit and the calibration signal generation circuit, obtaining the digital signal and the calibration signal, calibrating the digital signal according to the modified calibration signal and outputting a calibrated digital signal. The first signal is a predetermined signal or the calibrated digital signal output by the calibration circuit.

Abstract: A third-order loop filter for a delta signal modulator comprises a single operational amplifier, and a resistor-capacitor network including a plurality of capacitors and a plurality of resistors which are connected to the operational amplifier, and satisfy a third-order transfer function.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: Examples of a system and method for adaptively tuning a radio frequency (RF) front-end are generally described herein. In some examples, the frequency of a transmit signal of RF front-end circuitry is swept in at least a part of the RF transmit band. RF power in a receiver is detected as a function of the RF frequency of the transmit signal to determine a location of at least one tunable notch or other band stop element in the frequency domain. Information from the detected RF power is determined as a function of the RF frequency of the transmit signal. The RF front-end circuitry is adjusted to a selected frequency response using the determined information.

Abstract: A method implemented by processing and other audio components of an electronic device provides a smart audio output volume control, which correlates a volume level of an audio output to that of an audio input that triggered generation of the audio output. According to one aspect, the method includes: receiving an audio input that triggers generation of an audio output response from the user device; determining an input volume level corresponding to the received audio input; and outputting the audio output response at an output volume level correlated to the input volume level. The media output volume control level of the device is changed from a preset normal level, including from a mute setting, to the determined output level for outputting the audio output. Following, the media output volume control level is automatically reset to a pre-set volume level for normal media output.

Abstract: A system and method for quieting unwanted sound. As a non-limiting example, various aspects of this disclosure provide a system and method, for example implemented in a premises-based or home audio system, for quieting unwanted sound at a particular location.

Abstract: Systems, apparatus, and methods of asynchronous digital communication include at least one transmitter and/or at least one receiver communicatively coupleable to at least one communication interface for encoding and transmitting digital information as and/or receiving and decoding digital information from a transition between a first symbol and a second symbol, based on a predetermined relationship between the first symbol and the second symbol in such a way that the timing of the symbols is no longer relevant.

Abstract: An analog-to-digital converter (ADC) is provided, having two comparators, two digital-to-analog converters (DACs), and an adder circuit. The ADC receives an input value and, over a plurality of conversion cycles of the ADC, generates an output value representative of the input value. Each respective DAC generates a plurality of threshold levels, which are defined, at least in part, by predetermined redundancy levels that are binary-scaled. The comparator arrangement provides an output code in a respective conversion cycle and, for at least two adjacent conversion cycles, the two comparators collectively provide 2-bit output codes. The adder circuit provides a plurality of output bits of the output value, and is capable of overlapping and adding a first significant bit of the 2-bit output code provided for a predetermined conversion cycle with a second significant bit of the 2-bit output code provided for a previous conversion cycle to generate one output bit.

Abstract: This invention provides a signal processing apparatus for effectively detecting an abrupt change in an input signal. The signal processing apparatus includes a converter that converts an input signal into a phase component signal and an amplitude component signal in a frequency domain. The signal processing apparatus further includes a calculator that calculates feature amounts of the phase component signal and the amplitude component signal derived by the converter. The signal processing apparatus further includes a determiner that determines presence probability of an abrupt change in the input signal based on the feature amounts calculated by the calculator.

Abstract: A port status synchronization method, related device, and system, where a physical layer (PHY) device or an external processor connected to the PHY device determines whether a first service interface of the PHY device changes, and when the first service interface changes, controls a second service interface of the PHY device to restart auto-negotiation and sends, using the second service interface, an auto-negotiation advertisement packet to a first device connected to the second service interface in order to trigger the first device to synchronize, according to the auto-negotiation advertisement packet, a status of the second service interface and a status of the first service interface such that performing port status negotiation and synchronization between a link layer (media access control (MAC)) device or the first device and the PHY device using a service interface is achieved, without a need of disposing a management data input/output (MDIO) interface.

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

Abstract: An unmanned aerial vehicle (UAV) may emit masking sounds during operation of the UAV to mask other sounds generated by the UAV during operation. The UAV may be used to deliver items to a residence or other location associated with a customer. The UAV may emit sounds that mask the conventional sounds generated by the propellers and/or motors to cause the UAV to emit sounds that are pleasing to bystanders or do not annoy the bystanders. The UAV may emit sounds using speakers or other sound generating devices, such as fins, reeds, whistles, or other devices which may cause sound to be emitted from the UAV. Noise canceling algorithms may be used to cancel at least some of the conventional noise generated by operation of the UAV using inverted sounds, while additional sound may be emitted by the UAV, which may not be subject to noise cancelation.

Abstract: Exemplary methods and systems are directed to transmitting a process map of a control or automation system via a gateway device. The gateway device includes at least one first functional unit connected to a higher-ranking control unit via a first communications link based on a primary field bus protocol, and at least one second functional unit connected to at least one field device via a second communications link based on a secondary field bus protocol. Binary signals are stored in corresponding registers and analog signals, which are in an integer format, are transmitted to the first functional unit such that the number of binary signals is reduced by packing the binary signals into data bytes. The data bytes are translated into corresponding telegrams that can be processed by the primary field bus protocol and with the analog signals are transmitted to the higher-ranking control unit.

Abstract: A digital to analog converter circuit includes a plurality of digital to analog converter cells. The digital to analog converter circuit further includes a control circuit configured to control an operation of a digital to analog converter cell of the plurality of digital to analog converter cells based on a first phase component of a digital signal comprising information to be transmitted during a first time interval and based on a second phase component of the digital signal comprising information to be transmitted during a second time interval.

Abstract: A method includes resetting an output timing adjustment circuit in each of a plurality of DRAM devices to a default output timing data value, measuring a default delay from read command to read data for each of the plurality of DRAM devices, identifying a slowest DRAM device having a maximum default delay from read command to read data among the plurality of DRAM devices, writing an output timing data value to the output timing adjustment circuit in each of the plurality of DRAM devices to set the delay from read command to read data for each respective DRAM device to an amount substantially equal to the maximum default delay, and reading data from any one of the plurality of DRAM devices with a delay from read command to read data substantially equal to the maximum default delay.

Abstract: An integrated circuit (IC) includes an analog-to-digital converter (ADC). The ADC includes an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in response to a trigger signal. The ADC core circuit further provide the digital signal as an output of the ADC. The ADC further includes internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period has expired.

Abstract: Methods and apparatuses are described to convert analog signals to digital signals using a local charge averaging capacitor array (LCACA) in an analog-to-digital converter (ADC.) An apparatus includes a comparator. The comparator is configured with a first high input, a first low input, and is configure to receive a clock signal. A logic/latch block is configured to receive the clock signal and an output from the comparator. The logic/latch block is configured to output a control signal and a digital N-bit output signal. A local charge-averaging capacitor array (LCACA) is configured to receive the control signal and a reference voltage. An output of the LCACA is coupled to the first low input. The first LCACA is divided into a high sub-array and a low sub-array. The high sub-array is pre-charged to a high reference voltage and the low sub-array is pre-charged to a low reference voltage. The high reference voltage is greater than the low reference voltage.

Abstract: A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller.

Abstract: A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.

Abstract: Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal.

Abstract: A multi-phase clock circuit includes: a phase tuning circuit configured to receive a primitive N-phase clock including N primitive clocks of the same period but distinct phases and output a calibrated N-phase clock including N calibrated clocks in accordance with a first tuning signal, where N is integer greater than one; a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output clock in accordance with a multiplexing control signal; a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital code; and a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode select signal.

Abstract: Provided is an apparatus for analog-digital converting that includes a Most Significant Bit (MSB)-Digital Analog Converter (DAC) for converting a digital signal into an analog signal, a trim capacitor, a Least Significant Bit (LSB)-DAC, coupled to the trim capacitor, for converting a digital signal into an analog signal, a bridge capacitor connecting the MSB-DAC and the LSB-DAC, a comparator for measuring a voltage value at the MSB-DAC and LSB-DAC and outputting a result of comparing with a sampled voltage value, and a controller for generating first measurement data by digital converting a first measurement value output from the comparator by applying a reference voltage to a unit capacitor of the MSB-DAC, for generating second measurement data by digital converting a second measurement value output from the comparator by applying the reference voltage to the LSB-DAC, and controlling the trim capacitor by comparing the first and second measurement data.

Abstract: Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive Approximation Register (SAR) to provide digital approximations of an input analog voltage to a Capacitor Digital-to-Analog Converter (DAC), which generates a voltage from the digital approximations. The two voltages are compared and the comparison value used as the input for the SAR. After successive approximations, a digital combiner generates the digital conversion value from the outputs of the Flash-assisted ADC and the SAR. In one aspect, the bit cycles required for conversion are reduced by using redundancy and recombination.

Abstract: A receiver of a near field communication device includes a local oscillator, a first channel, and a second channel. The local oscillator may be configured to generate a first local oscillating signal. The first channel may be configured to process an input signal by mixing the input signal with the first local oscillating signal. The second channel may be configured to process the input signal by mixing the input signal with a second local oscillating signal that has a phase difference of 90 degrees with respect to the first local oscillating signal. Each of the first and second channels may include a comparator unit that includes a comparator configured to compare, in a comparator mode, an amplifier output signal with a reference voltage whose level increases in a step-wise manner and the comparator unit may be configured to set a level of the reference voltage to be used in a normal mode based on an output signal of the comparator.

Abstract: Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer.

Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.

Abstract: A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.

Abstract: Embodiments provide an area, cost, and power efficient multi-service transceiver architecture. The multi-service transceiver architecture simplifies receiver/transmitter front ends needed for a multi-service architecture, by replacing significant portions of multiple receiver and/or transmitter front ends with a single ADC and/or DAC, respectively. In embodiments, a plurality of received service contents are combined into one composite analog/RF signal and applied to an ADC. The ADC converts the composite signal into a composite multi-service digital signal. Digital techniques are then used to separate the plurality of service contents into a plurality of respective digital streams that each can be independently demodulated. Similarly, in the transmit direction, a plurality of digital streams, including a plurality of service contents, are combined into one composite digital signal.

Abstract: Methods of measuring capacitance error in a successive approximation register (SAR) analog to digital converter (ADC) are described, including a method in which said ADC includes a register and a digital to analog converter (DAC), and the method comprises connecting a first capacitance associated with a first bit of the DAC between a first reference voltage and a second reference voltage, connecting a first set of one or more capacitances associated with one or more other bits of the DAC between the first reference voltage and a third reference voltage, connecting the first capacitance between a first node and the third reference voltage, connecting the first set of one or more capacitances between the first node and the second reference voltage, and measuring a voltage at the first node to determine a representation of a difference between the first capacitance and a total capacitance of the first set of one or more capacitances.

Abstract: An apparatus for generating sinusoidal waves may include: a look-up table storage unit storing a look-up table including a plurality of sampling points determined based on a base frequency and a sampling frequency; a sinusoidal wave generating unit calculating an integer ratio of a target frequency to the base frequency and obtaining sampling points from the look-up table by reflecting the integer ratio so as to generate a sinusoidal wave; and a correction control unit calculating noise information in the generated sinusoidal wave, and controlling the sinusoidal wave generating unit to correct the sampling frequency if the noise information fails to meet a predetermined requirement.

Abstract: An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch.

Abstract: A method can include receiving an initial waveform and generating, testing, and evaluating the performance of an initial child set of waveforms based on an initial parent set of waveforms from the initial waveform. The method can also include determining whether a termination condition has been met based on the evaluating and, if so, providing an optimized waveform. If the termination condition has not been met, the method can also include generating subsequent child sets of waveforms based on the previous child set(s).

Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Abstract: A method and an apparatus embodying the method for fast convolution of a signal with a one-sided exponential function is disclosed. Additionally, a method and a system embodying the method for fast convolution of a signal with complex exponential function localized around an origin by an exponential function envelope utilizing the method and a system embodying the method for fast convolution of a signal with a one-sided exponential function is disclosed.

Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.

Abstract: An electronic system includes a configurable processing device. The configurable processing device includes a processor that performs digital processing, a first input that receives digital signal, a first output that sends digital signal and a converter that converts between analog and digital signals. The converter includes a delta-sigma modulator.

Abstract: Techniques for the identification of a spike-processing circuit are provided. An exemplary method includes receiving spike trains corresponding to a circuit input over a time period, and selecting a number of spikes for each of input spike trains over a predetermined time window. Each of the selected spikes can be replaced with a sampled reproducing kernel to obtain a plurality of signals, and each obtained signal can correspond to one of the input spike trains. Each of the obtained signals can be passed through a plurality of receptive fields or filters to obtain an aggregate filter output signal. The filter output signal can be encoded into an output spike train, and the output spike train can correspond to a response of the circuit to the plurality of input spike trains.

Abstract: Methods for manufacturing multiple bottom port, surface mount microphones, each containing a micro-electro-mechanical system (MEMS) microphone die, are disclosed. Each surface mount microphone features a substrate with metal pads for surface mounting the package to a device's printed circuit board and for making electrical connections between the microphone package and the device's printed circuit board. The surface mount microphones are manufactured from a panel of unsingulated substrates, each substrate having an acoustic port, and each MEMS microphone die is substrate-mounted and acoustically coupled to its respective acoustic port. Individual covers are joined to the panel of unsingulated substrates, and each individual substrate and cover pair cooperates to form an acoustic chamber for its respective MEMS microphone die. The completed panel is singulated to form individual MEMS microphones.

Abstract: An imaging apparatus including a pixel, a current source, and a signal processing circuit. The pixel outputs signal charge, obtained by imaging, as a pixel signal. The current source is connected to a transmission path for the pixel signal and has a variable current. The signal processing circuit performs signal processing on a signal depending on an output signal to the transmission path and performs control so that a current of the current source is changed in accordance with the result of signal processing.

Abstract: A selector selects an analog audio signal input to one input port from among analog audio signals input to multiple input ports according to an instruction from the user. An analog gain control circuit amplifies the analog audio signal received from the selector, with a corresponding one of the gains set for the respective input ports. An analog gain control circuit is configured to gradually change its gain when the gain is switched. An A/D converter converts an output signal of the analog gain control circuit into a digital audio signal. A first audio signal processing circuit is monolithically integrated on a signal semiconductor substrate.

Abstract: Embodiments of the present invention may provide accuracy enhancement techniques to improve ADC SNRs. For example, regular bit trials from a most significant bit (MSB) to predetermined less significant bit of a digital word and extra bit trials may be performed. The results of the regular and extra bit trials may be combined to generate a digital output signal. A residue error may be measured, and the digital output signal may be adjusted based on the measured residue error.

Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analog-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analog converter, wherein: the first switching-circuitry unit is configured to sample an input analog signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analog signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of dock signals have the same specifications as one another.

Abstract: A fieldbus adaptor connected between a fieldbus that handles a digital signal and a field device that handles an analog signal, the fieldbus adaptor comprising a first connection unit detachably connected to the fieldbus, a second connection unit detachably connected to the field device, and a conversion unit provided between the first connection unit and the second connection unit, the conversion unit bidirectionally converting the digital signal handled by the fieldbus and the analog signal handled by the field device.

Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

Abstract: Multi-stage parallel super-high-speed ADC and DAC of a logarithmic companding law has a voltage follower switch having zero voltage drop, and also has a lossless threshold switch group, wherein a quantization voltage of A/D conversion or D/A conversion is directly obtained through voltage-dividing resistance thereof. The ADC and DAC simplify a conversion process and reduce a conversion error. The ADC and DAC provide multi-stage multi-bit parallel super-high-speed A/D conversion and D/A conversion with logarithmic companding law of a high conversion rate and the low conversion error.

Abstract: Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

Abstract: An impedance matching transmission circuit for a transducer has a transmission medium connected to the transducer. A transmitting circuit is connected to the transmission medium with the transmitting circuit terminating in a reference circuit element. The transmitting circuit comprises an analog to digital converter having an analog input connected to the reference circuit element, and having a digital output. A digital to analog converter receives the digital output and generates an analog output signal in response thereto. A driver circuit is connected to the transmission medium and receives the analog output signal and supplies a driver signal to the transmission medium.

Abstract: Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.