Abstract: The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic.

Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

Abstract: A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal.

Abstract: A device for processing data adapted for being converted between an analog format and a digital format, the device having a scrambling unit adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format.

Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.

Abstract: A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based o

Abstract: Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator.

Abstract: Disclosed herein is a delta-sigma modulator including: a plurality of integrators configured to be connected in cascade to the input of an analog signal; a quantifier configured to quantify an output signal from the final-stage integrator among the plurality of integrators so as to output a digital signal; a zero-order feedback path configured to compensate for an internal loop delay in the output of the quantifier; and a voltage output type digital-analog converter configured to be located on the zero-order feedback path and to convert the output digital signal from the quantifier into an analog signal, wherein the voltage output type digital-analog converter is connected in capacity to the final-stage integrator and switches an output amplitude in accordance with a calibration code that is supplied.

Abstract: A signal processing circuit includes a production part configured to produce a first analog signal, an A/D conversion part configured to convert the first analog signal output from the production part to a first digital signal, a processing part configured to process the first digital signal output from the A/D conversion part into a second digital signal, and a D/A conversion part configured to convert the second digital signal to a second analog signal and output the second analog signal via an output terminal.

Abstract: The present invention relates to a multi-bit digital to analogue converter (DAC) and to a delta-sigma analogue to digital converter employing such a DAC. The DAC has a multi-bit input, a plurality of elements for processing an input signal received at the input and a selector for selecting, based on the input signal, one or more of the DAC elements to process the signal. The DAC has control means for controlling the selector such that if the input to the DAC is below a predetermined level for a predetermined period of time the selector is operative to select only a single one of the DAC elements to process the input signal. Also disclosed is a delta-sigma analogue to digital converter (ADC) employing such a DAC.

Abstract: A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.

Abstract: A ??0 modulator includes: a plurality of integrators cascaded to an input of an analog signal; a quantizer for quantizing an output signal of the integrator at a last stage and outputting a resultant digital signal; a DA converter for feedback for converting the digital signal obtained by the quantizer into an analog signal and supplying the analog signal to an input side of at least the integrator at a first stage; and an adder, arranged at an input stage side of the integrator at the last stage, for adding an output of the integrator at a preceding stage of the integrator at the last stage to at least one path signal supplied from at least another path via a first resistor having at least a first coefficient. The integrator at the last stage includes an operational amplifier, an integration capacitor, and a second resistor having a second coefficient.

Abstract: An apparatus includes a clock source and an oversampled continuous-time digital-to-analog converter. Noise signal is added to the clock signal as the clock signal is generated and/or routed. The oversampled continuous-time digital-to-analog converter includes a sigma-delta modulator to perform noise shaping on input data samples and provide intermediate data samples; a filter to filter the intermediate data samples and generate filtered samples, the filter having a transfer function that has a stop band at a frequency range that includes the frequency of the noise signal or a component of the noise signal; and a continuous-time digital-to-analog converter to convert the filtered samples to an output analog signal.

Abstract: A method of reproducing an original analog signal modified by a distortion and sampled. The distortion may be linear or nonlinear, and the samples may be either ideal or non-ideal. The method determines a stationary point of a cost function based on an error vector. The method iteratively computes approximated analog signals until the approximated analog signals converge to the original analog signal. The method may utilize Fr?chet derivatives and Moore-Penrose pseudo inverse transformations in order to iteratively compute the original analog signal. An apparatus performing said method is also disclosed.

Abstract: In accordance with an embodiment, a proximity sensor includes a driver, a photodiode (PD), an analog-to-digital converter (ADC) with analog-to-digital-to-analog (ADA) feedback, and a controller. The driver is adapted to selectively drive a light source. The photodiode (PD) is adapted to produce a photodiode current signal (Idiode) indicative of an intensity of light detected by the PD, where the light detected by the PD can include ambient light and/or light transmitted by the light source that was reflected off an object proximate the PD. The controller is adapted to control the driver and the ADC with ADA feedback. A digital output of the ADC with ADA feedback is indicative of a proximity of an object to the PD with at least a majority of the ambient light detected by the PD rejected.

Abstract: An image sensor includes a pixel array including a plurality of pixels which are arranged in a matrix of a plurality of rows and columns and each of the plurality of pixels being configured to convert intensity of incident light into an electrical image signal; and an extended counting analog-to-digital converter configured to perform a first analog-to-digital conversion to provide a digital signal from an output signal of the pixel array, to obtain a residue using the output signal of the pixel array and the digital signal, and to perform a second analog-to-digital conversion using the residue.

Abstract: This A/D convertor includes: a first D/A conversion unit configured to sample an analog input signal, and to generate a first difference signal by performing successive comparison of the analog input signal based on a reference voltage; a precharge capacitor unit configured to hold the reference voltage; a first comparing unit configured to compare the first difference signal with a reference value to generate a first digital signal; and an amplifying unit configured to calculate by using the first difference signal and the reference voltage to generate a residual signal.

Abstract: A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n-1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n-1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n-1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n-1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.

Abstract: An offset cancellation circuit for canceling an offset voltage in an amplifier is provided herein. The offset cancellation circuit includes a current source configured to provide an offset current, a switching stage comprising first and second switches, and a cascode stage. The cascode stage comprises a first cascode device configured to receive the offset current from the first switch and inject the offset current into a first differential end of the amplifier, and a second cascode device configured to receive the offset current from the second switch and inject the offset current into a second differential end of the amplifier. Offset voltages are common to many differential circuits as a result of mismatch. The injection of current by the offset cancellation circuit can reduce or eliminate an offset voltage, while the cascode stage can prevent parasitic capacitance associated with the offset cancellation circuit from creating further mismatch.

Abstract: An analog-to-digital converter includes a first switch circuit, a first integrator, a second switch circuit, a second integrator, a quantizer and a digital-to-analog converter. The first switch circuit receives an external analog signal, outputs the analog signal in reverse phase, and outputs the analog signal in positive phase. The first integrator receives and integrates the analog signal with cross-coupling. The second switch circuit outputs an output of the first integrator and a common mode output potential of the first integrator. The second integrator samples and integrates an output of the second switch circuit. The quantizer single-bit-quantizes an output of the second integrator to provide the output as a digital signal output. The digital-to-analog converter receives an output of the quantizer and provides the output as an analog signal output. Each of the first and second integrators receives and integrates an output of the digital-to-analog converter with cross-coupling.

Abstract: A device for receiving a RF signal (1; 21) with loop-through output (16) is provided. The device comprises: an input (3) receiving a RF input signal (2); an analog-digital converter (8) converting the RF input signal (2) to a digital signal (9); a digital signal processing unit (10) digitally processing the digital signal (9); a digital-analog converter (14) converting the processed digital signal (13) to a loop-through RF signal (15) corresponding to the RF input signal (2); and a loop-through output (16) outputting the loop-through RF signal (15).

Abstract: A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The chopping circuit is configured to receive the digital output signals and provide error signals that represent ripple error in the digital output signals. The integrator circuit is configured to accumulate the error signals and provide an accumulated error signal. The digital to analog converter circuit is configured to convert the accumulated error signal into an analog signal that is received by the second circuit to reduce the ripple error.

Abstract: A sigma-delta (??) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ?? modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ?? LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ?? difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.

Abstract: Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.

Abstract: Disclosed is a pipelined analog-to-digital converter which includes a digital correction circuit configured to measure and correct a pipelined conversion stage gain error and an offset error due to a finite voltage gain operational amplifier and capacitor mismatch. The pipelined analog-to-digital converter includes a pipelined conversion stage error measuring and correcting circuit measuring and correcting an error generated from an conversion stage, so that an error of a conversion stage is minimized and a chip realization area and power consumption are reduced.

Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

Abstract: An analog-to-digital converter that uses a comparator based asynchronous binary search is described. The architecture includes a self-clocked (asynchronous) hierarchical binary tree of comparators, each arranged for being provided with a predetermined threshold. The input signal is applied in parallel to all comparators as is the case with flash converters, but the clock is applied to (at least) one comparator only, for example to the first or root comparator. The at least one comparator is further arranged for controlling at least one other comparator of the plurality of comparators.

Abstract: A filtering analog to digital converter (ADC) includes an integrator receiving at its input an analog input signal. A filtering capacitor at the input of the integrator filters out a large portion of out-of-band interferers in the analog input signal. The integrator produces an output that is quantized to produce a digital output. A feedback path between the quantizer output and the integrator input includes a digital to analog converter (DAC).

Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.

Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.

Abstract: The SAR control circuit of the successive approximation register A/D converter changes the digital value by the first conversion frequency in a first conversion range according to the comparison result signal, and outputs the digital value. When it is determined that the sample and hold value is out of the first conversion range according to the determination signal, the range setting circuit sets a second conversion range different from the first conversion range.

Abstract: An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter 13, an input 15 receives an analog signal to be A/D converted. An output 17 provides at least a part of a digital signal SD having a predetermined number of bits representing the analog signal SA. In response to an analog signal SA, a sub-A/D conversion circuit 19 generates a signal SDP representing one or a plurality of bit values of the digital signal SD and feeds the signal SDP to the output 17. An input 21 a of a control circuit 21 is connected to an output 19a of the sub-A/D conversion circuit 19 and provides a control signal SCONT corresponding to the signal SDP. The control signal SCONT has a waveform including a transition from a voltage level L1 to a voltage level L2 and a transition from the voltage level L2 to the voltage level L1.

Abstract: Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.

Abstract: A quantization circuit includes a quantizer and a compensation circuit. The quantizer includes a voltage-to-phase converter and a phase difference digitization block. The voltage-to-phase converter is arranged for generating a phase signal according to an input voltage. The phase difference digitization block is arranged for generating a quantization output according to a phase difference between a phase of the phase signal and a reference phase input. The compensation circuit is arranged for applying compensation to the phase difference digitization block according to the quantization output.

Abstract: An analog-to-digital conversion device which converts an analog input signal into a digital signal and output it includes a signal characteristic detection unit for detecting a predetermined characteristic of the input signal; a control signal generation unit for setting a resolution based on the signal characteristic detected by the signal characteristic detection unit, generating a control signal that indicates only an operation required for performing the analog-to-digital conversion at the resolution, and outputting it; and an analog-to-digital conversion unit for restricting the operation based on the control signal and converting the input signal into the digital signal at the set resolution.

Abstract: An A/D converter circuit includes a comparison circuit that performs a process to compare an added signal of a sampled signal of an input signal and a code signal with a D/A output signal, or a process to compare the sampled signal with an added signal of the D/A output signal and the code signal, a control circuit that outputs output data obtained based on successive approximation result data and the code data as A/D conversion data of the input signal, a first D/A converter circuit that D/A converts the data for successive approximation, a second D/A converter circuit that D/A converts code data that changes over time, and a correction section that performs a correction process, to correct the successive approximation result data so as not to overflow due to code shifting using the code data.

Abstract: An apparatus includes processor and a control interface. The processor is adapted to in a first mode of operation, operate as part of one of a wireless receiver and a wireless transmitter and in a second mode of operation. The processor also processes a first audio band signal to generate a second audio band signal. The control interface selects one of the first and second modes of operation.

Abstract: A method and apparatus for distributing events. In one embodiment, the method includes a bus concurrently transmitting a first event-signal and a first event-identification (event-ID); wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur. The first event-ID corresponds to the first event-signal.

Abstract: A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses signal samples resulting from analog to digital conversion of an analog signal received via an antenna. The RF unit transfers the compressed signal samples over the serial data link to the base station processor where they are decompressed prior to the normal signal processing operations. For the downlink, the base station processor compresses signal samples and transfers the compressed signal samples over the serial data link to the RF unit. The RF unit decompresses the compressed samples and converts the decompressed samples to an analog signal for transmission over an antenna. Compression and decompression can be incorporated into operations of conventional base stations and distributed antenna systems.

Abstract: A communication device and the method thereof are disclosed in embodiments of the present invention. The communication device includes a level determining module, an digital to analog converter and an analog to digital converter. The level determining module determines a plurality of voltage levels and voltage intensity thereof according to an estimating signal to generate a first digital signal. The digital to analog converter converts the first digital signal into a pulse shaped analog signal according to the plurality of voltage levels and voltage intensity thereof. The analog to digital converter converts a first difference signal into a second digital signal wherein the first difference signal equals the result of subtracting the pulse shaped analog signal from a receiving signal.

Abstract: A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

Abstract: A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.

Abstract: A system that includes a multiplexer having an output selectively coupled to a plurality of inputs, a bus coupled to the output of the multiplexer, and first and second circuits configured to generate first and second digital signals, respectively. The first digital signal is related to a rotational angle of a crankshaft at a first point in time, and the second digital signal is related to a value of parameter at the first point in time, wherein the parameter is one other than the rotational angle of the crankshaft. The first and second circuits are coupled directly or indirectly to first and second inputs of the multiplexer.

Abstract: Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor.

Abstract: A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

Abstract: A linearity enhancement circuit is disclosed which includes: a first shift amount creation block creating a first shift amount in keeping with the immediately preceding output code of an n-bit A/D converter; a first shifter circuit bit-shifting input code data by the first shift amount that has been supplied, the first shifter circuit further outputting the bit-shifted input code data; a register storing the output of the first shifter circuit in order to output the stored data as the input code data to the first shifter circuit thereby forming a loop circuit in conjunction with the first shifter circuit, the register further outputting the stored code data as a second shift amount; and a second shifter circuit bit-shifting the output code of the A/D converter by the second shift amount that has been supplied, the second shifter circuit further outputting the bit-shifted output code to an n-bit D/A converter.

Abstract: A method and apparatus are provided for Fast Data Weighted Average (DWA) double-sampling modulators with minimal loop delay supporting improved stability. Quantization and DEM are accomplished within non-overlap time. By this reduction in time delay, power can be saved for analog integrators. The DC signal of partitioned DWA is removed by alternating reference voltages, and there is no additional delay as the alternation is performed at the comparator inputs. Embodiments employ an oversampling ratio (OSR) of 8 and a 15-level quantizer.

Abstract: An apparatus and method of scheduling signals. In one embodiment, the method includes a first circuit receiving a first plurality of reference values. The first circuit selects a reference value from the first plurality according to a first reference identifier (ID) that is stored in memory. The first circuit compares the selected reference value to a first match value.

Abstract: An active noise control system generates an anti-noise signal to drive a speaker to produce sound waves to destructively interfere with an undesired sound in a targeted space. The speaker is also driven to produce sound waves representative of a desired audio signal. Sound waves are detected in the target space and a representative signal is generated. The representative signal is combined with an audio compensation signal to remove a signal component representative of the sound waves based on the desired audio signal and generate an error signal. The active noise control adjusts the anti-noise signal based on the error signal. The active noise control system converts the sample rates of an input signal representative of the undesired sound, the desired audio signal, and the error signal. The active noise control system converts the sample rate of the anti-noise signal.

Abstract: In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.