Abstract: In one embodiment, an apparatus comprises a first capacitor system and a second capacitor system. Each capacitor system is removably coupled to the same portion of an analog to digital converter (ADC) and the same sensing circuit. Each capacitor system stores charge received through the sensing circuit when coupled to the sensing circuit and provides the charge received through the sensing circuit to the ADC for conversion into a digital value when coupled to the ADC. When the control signals are in a first state, the first capacitor system receives charge through the sensing circuit and the second capacitor system is coupled to the portion of the ADC. When the one or more control signals are in a second state, the second capacitor system is coupled to the sensing circuit to receive charge through the sensing circuit and the first capacitor system is coupled to the portion of the ADC.

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: The analog-to-digital converter includes a signal processing unit generating an operational amplifier output voltage in response to an input voltage and a DAC output voltage in a first period and generating the operational amplifier output voltage in respose to a feedbacked operational amplifier output voltage and the DAC output voltage in a second period; a control unit generating a DAC control signal by comparing the operational amplifier output voltage with a first reference voltage to obtain high order M-bits of data in the first period, and generating the DAC control signal by comparing the operational amplifier output voltage with second and third reference voltages to obtain low order N-bits of data in the second period; and a digital analog converter generating the DAC output voltage in response to the DAC control signal.

Abstract: A data conversion device is provided with a data converting means that sequentially converts first data into second data of the number of second bits, wherein an analog signal is quantized into the first data by the number of first bits, and the first and second data can be first and second maximum values, respectively. The data converting means is comprised of a first conversion means (steps 21 and 23) that, when a value of the fast data is not the first maximum value, converts the first data to the second data by adding 0 to a lower bit side of the first data and a second conversion means (steps 21 and 24-26) that converts the first data to the second data so that, when a value of the first data is the fast maximum value, a value can be made larger, in accordance with a value be-fore or after the first data, than the data of the number of second bits obtained by adding 0 to the lower bit side of the first data.

Abstract: A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Abstract: An analog-to-digital converter is provided and comprises a most significant bit (MSB) conversion module, a successive approximation register analog-to-digital converter (SAR ADC) module, and an operation module. The MSB conversion module receives an analog signal to be converted, and converts the analog signal to an MSB with M bits, and obtains a redundancy signal. The SAR ADC module is coupled to the MSB conversion module. The SAR ADC receives the redundancy signal and processes the redundancy signal to be a least significant bit (LSB) with N bits. The operation module is coupled to the MSB conversion module and the SAR ADC module. The operation module receives the MSB with the M bits and the LSB with the N bits and generates a first digital signal with (M+N) bits. Each of M and N is positive, and (M+N) is a positive integer.

Abstract: A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption.

Abstract: A reconfigurable analog-to-digital (ADC) modulator structure that includes a plurality of ADC structures being coupled to each other through their respective noise quantization transfer functions. Each ADC structure receives as input an analog signal and each ADC structure outputting a plurality of first output signals. An adder module receives the first output signals and performs addition on the first output signals and generates a second output signal. A division module receives the second output signal and performs division on the second output signal by a predetermined factor.

Abstract: A multi-input-multi-output-system (MIMO) is provided that includes a first input signal and a second input signal. A plurality of analog-to-digital converter (ADC) cell structures receive as input a combination of the first input signal and the second input signal as well as a combination of quantization noise signals from the respective other ADC cell structures of the plurality of ADC cell structures. The ADC cell structures generate a plurality of first output signals and the noise quantization signals. A plurality of adder modules receive the first output signals and performing either addition or subtraction on a selected combination of the first output signals, the adder modules generate a plurality of second output signals. A plurality of division modules receive the second output signals and perform a division operation on the second output signals by a predetermined factor. The division modules generate a plurality of final output signals of the MIMO.

Abstract: An analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal and for outputting a digital representation of said analog input signal is described.

Abstract: A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.

Abstract: A circuit including an analog-to-digital converter (ADC). The ADC is configured to receive an analog feedback signal and an analog input signal and generate a digital output. The circuit further includes a noise shaper. The noise shaper is configured to truncate the digital output and generate a noise shaper output having a lower number of bits than the digital output, and to shape quantization noise generated during truncation. The circuit further includes a pulse width modulation digital-to-analog converter (PWM DAC). The PWM DAC configured to process the truncated digital output of the noise shaper output and generate a PWM DAC output.

Abstract: A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

Abstract: A SAR ADC is provided. A DAC provides an intermediate analog signal according to an analog input signal, a most significant bit capacitance and a plurality of significant bit capacitances smaller than the most significant bit capacitance. A first switched capacitor array selectively provides the most significant bit capacitance or the significant bit capacitances according to a select signal. Sum of the significant bit capacitances is equal to the most significant bit capacitance. The second switched capacitor array provides the significant bit capacitances when the first switched capacitor array provides the most significant bit capacitance, and provides the most significant bit capacitance when the first switched capacitor array provides the significant bit capacitances. A comparator provides a comparison result according to the intermediate analog signal. A SAR logic provides an digital output signal according to the comparison result.

Abstract: A current input analog-to-digital converter and a corresponding current measurement circuit is disclosed. In accordance with one example of the invention, an analog-to-digital conversion circuit includes a register for storing a digital register value and a digital-to-analog converter that is configured to provide a reference current at a circuit node which is set in accordance to the digital register value. The electric potential of the input node is responsive to the reference current set. A comparator circuit is configured to compare the potential of the circuit node with at least one threshold, thus assessing whether the potential of the circuit node is at least approximately at a desired value. Control circuitry is responsive to the comparator circuit and is configured to adjust the digital register value stored in the register and to adjust the reference current until the comparator indicates that the potential of the circuit node does not deviate from the desired value.

Abstract: A dynamically reconfigurable electrical interface is disclosed that can be used in various applications, including avionics communications. In one embodiment, a first switch receives an input signal and routes it to the applicable signal conditioning path unit that conditions the input signal, after which a second switch routes it to an amplifier. The amplifier provides an amplified signal to an analog-to-digital converter that generates a corresponding numerical value based on the voltage of the amplified signal that is analyzed by a processor to determine information conveyed by the input signal based on a particular electrical interface. Multiple distinct interfaces can be accommodated by on one more processors accessing instructions sets for processing information corresponding to a particular electrical interface.

Abstract: An analog-to-digital converter system that includes a pipeline of successively-cascaded signal converters, each operating alternatively in a first circuit configuration and a second circuit configuration, an error estimator coupled to the pipeline to receive the digitized error for estimating an amplifier gain of the present signal converter stage, and a code aligner/corrector that temporally aligns and corrects the digital codes received from the successively-cascaded signal converters to provide a digital out of the ADC system.

Abstract: An on-chip DC voltage generator and hardware efficient method provide for generating linear DC voltages with a programmable negative temperature coefficient. A temperature-dependent DC voltage is digitally derived from an on-chip temperature readout, a programmable digital word to control the temperature coefficient and a programmable digital word to adjust the digital level. The digital result is applied to a resistor string digital to analog converter (DAC) to generate an analog DC voltage with a negative temperature slope. Additionally, another programmable digital word for trimming allows convergence at a given temperature of voltages having a common level but different temperature coefficients. These voltages can be applied to the word line in the flash memory and track the threshold voltage of the memory cell, which has a negative temperature coefficient, such that the difference between the gate voltage and the threshold voltage is constant over temperature.

Abstract: An uncalibrated converter element in an analog-digital converter may be replaced with two or more smaller elements having an effective total net value that is equal to that of the uncalibrated converter element. In an exemplary case where the element is capacitor, one or more of these smaller capacitors may be independently calibrated by switching the smaller capacitor between two voltages, such as a reference voltage and ground, and then calculating a difference of corresponding digital output codes generated by the backend ADC with previously calibrated capacitors associated with lesser significant bits. The total capacitance of the uncalibrated capacitor may be apportioned between the smaller capacitors so that the individual maximum charge contribution of each smaller capacitor to the converter output together with any expected manufacturing variance does not exceed the aggregated contribution of the previously calibrated capacitors.

Abstract: An analog to digital converting device includes a first digital conversion (ADC) circuit configured to convert an inputted analog signal into a first digital signal, a first multiplying digital to analog converting (MDAC) circuit configured to amplify a difference between a first converted signal and the inputted analog signal, a second ADC circuit configured to convert an output of the first MDAC circuit into a second digital signal, a second MDAC circuit configured to amplify difference between a second converted signal converted from the second digital signal and the output of the first MDAC circuit, a third ADC circuit configured to convert an output of the second MDAC circuit into a third digital signal, and a common amplifying circuit shared by the first and the second MDAC circuits, wherein the common amplifying circuit consumes current based on which MDAC circuit the common amplifying circuit operates with.

Abstract: A comparator offset correction device opens an open switch 205 and closes a short-circuit switch 204 in offset correction of a comparator 201. In this state, a controller 203 allows the comparator 201 to repeat, more than once, the operation of comparing reference voltages 101 input to two input terminals with each other. The filter 202 outputs a frequency signal obtained by smoothing a plurality of comparison results. Based on the frequency signal from the filter 202, the controller 203 outputs a threshold value control signal to the comparator 201 so that the ratio of a high-level voltage to a low-level voltage in the results of the comparison in the comparator 201 is 50%. Thus, even when a current which will be input may differ from a current which is currently input due to, for example, the influence of noise, the threshold value offset amount is normally corrected.

Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.

Abstract: An active noise control system generates an anti-noise signal to drive a speaker to produce sound waves to destructively interfere with an undesired sound in a targeted space. The speaker is also driven to produce sound waves representative of a desired audio signal. Sound waves are detected in the target space and a representative signal is generated. The representative signal is combined with an audio compensation signal to remove a signal component representative of the sound waves based on the desired audio signal and generate an error signal. The active noise control adjusts the anti-noise signal based on the error signal. The active noise control system converts the sample rates of an input signal representative of the undesired sound, the desired audio signal, and the error signal. The active noise control system converts the sample rate of the anti-noise signal.

Abstract: An analog-to-digital converter with a resolution booster is provided. The analog-to-digital converter may include a successive approximation analog-to-digital converter, a resolution booster, and an output combiner. The successive approximation analog-to-digital converter may be configured to convert an analog signal into digital data. The resolution booster may be selectively activated to enhance the resolution of the successive approximation analog-to-digital converter, and the output combiner may be configured to combine the respective outputs of the successive approximation analog-to-digital converter and the resolution booster.

Abstract: Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps.

Abstract: A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit.

Abstract: A plurality of cameras is placed so that those optical axes become parallel to the Z-axis and are in relative position t on the XY plane. Multi-view video compression coding apparatus determines depth distance Z and unit normal vector (nx, ny, nz) of the arbitrary point in the surface of the object, moves the first block by disparity vector based on t and Z, transforming the first block by linear transformation matrix based on t, Z and n, then, matching the first block to block of the second picture. Then, while changing Z and n arbitrarily, the second block of the second picture which is most similar to the first block is searched for. And the apparatus derives a prediction error between the first block and the second block, codes the prediction error, and adds Z and n to coded data.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator circuit comprises, a first pad associated with a first terminal of an oscillator and a second pad associated with a second terminal of the oscillator. The oscillator is configured to generate an oscillating signal and communicate the oscillating signal from the second terminal to a clock distributor coupled to the second pad. The oscillator circuit further comprises an oscillator gain element comprising an output node coupled to the first pad and an input node coupled to the second pad. The oscillator circuit also comprises a digital-to-analog converter (DAC) coupled to the first pad. The oscillator circuit additionally comprises a switching circuit coupled to the gain element. The switching circuit is configured to enable the gain element when the oscillator comprises a resonator and disable the gain element when the oscillator comprises a voltage controlled oscillating module.

Abstract: A switched-capacitor circuit (10, 32 or 32A) samples a first signal (VIN+) onto a first capacitor (C1 or CIN1) by switching a top plate thereof via a summing conductor (13) to a first reference voltage (VSS) and switching a bottom plate thereof to the first signal. A second signal (VIN?) is sampled onto a second capacitor (C3 or CIN3) by switching a top plate thereof to the second signal and switching a bottom plate thereof to the first reference voltage. After the sampling, the top plate of the second capacitor is coupled to the top plate of the first capacitor. The bottom plate of the second capacitor is coupled to the first reference voltage.

Abstract: An exemplary delta-sigma modulator loop applied to convert a continuous-time input signal into a discrete-time output signal. The delta-sigma modulator loop includes a conversion unit, a sampling unit, a quantization unit, a compensation unit, and a digital-to-analog converter unit. The conversion unit converts an error signal relevant to the input signal through a transfer function to generate a converted signal. The sampling unit samples the converted signal to generate a sampling signal. The quantization unit quantizes the sampling signal to obtain the output signal. The compensation unit receives the output signal and compensates a time delay of the received output signal to generate a compensation signal. The digital-to-analog converter unit is electrically coupled to the compensation unit and the conversion unit to convert the compensation signal to generate a feedback signal for regulating the error signal.

Abstract: Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: A system and method are provided for operating first and second components in first and second domains. In one embodiment, the method includes: generating a plurality of clock signals shifted relative to one another; operating a first component in a first domain using a first one of the plurality of clock signals; operating a second component in a second domain using a second one of the plurality of clock signals selected using a selection component; and comparing a present output of the second component to a stored value, determining whether a variation between the present output and the stored value is greater than a threshold, and, if the variation is greater than the threshold, using a controller to cause the selection component to select a third clock signal from the plurality of clock signals that is shifted relative to the second clock signal to drive the second component.

Abstract: A system including a first circuit, a second circuit, and a feedback circuit. The first circuit is configured to provide input signals. The second circuit is configured to receive the input signals and provide digital output signals that correspond to the input signals. The feedback circuit includes a chopping circuit, an integrator circuit, and a digital to analog converter circuit. The digital to analog converter circuit is configured to convert an error signal into an analog signal that is received by the second circuit to reduce ripple error.

Abstract: A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: An on-chip DC voltage generator and hardware efficient method provide for generating linear DC voltages with a programmable negative temperature coefficient. A temperature-dependent DC voltage is digitally derived from an on-chip temperature readout, a programmable digital word to control the temperature coefficient and a programmable digital word to adjust the digital level. The digital result is applied to a resistor string digital to analog converter (DAC) to generate an analog DC voltage with a negative temperature slope. Additionally, another programmable digital word for trimming allows convergence at a given temperature of voltages having a common level but different temperature coefficients. These voltages can be applied to the word line in the flash memory and track the threshold voltage of the memory cell, which has a negative temperature coefficient, such that the difference between the gate voltage and the threshold voltage is constant over temperature.

Abstract: A device monitoring unit obtains, through respective digital communication routes, a combination of a digital setting value for an analog output value to an analog communication route in a field device, a digital value of an AD converting device in an input/output unit, and one of the digital setting values stored in a memory of the input/output unit, to check the status of the communication through the analog communication route based on the values obtained.

Abstract: A pipeline stage of a pipelined analog-to-digital converter (ADC) circuit can include an ADC to convert an analog input to a digital output, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, where a succeeding pipeline portion can convert the amplified analog residue to at least one second digital output and a digitized residue. A mapping circuit can selectively exchange inputs between a selected one of the first plurality of DACs and one of the second plurality of DACs, and a calibration signal circuit can provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs.

Abstract: An impedance matching transmission circuit for a transducer has a transmission medium connected to the transducer. A transmitting circuit is connected to the transmission medium with the transmitting circuit terminating in a reference circuit element. The transmitting circuit comprises an analog to digital converter having an analog input connected to the reference circuit element, and having a digital output. A digital to analog converter receives the digital output and generates an analog output signal in response thereto. A driver circuit is connected to the transmission medium and receives the analog output signal and supplies a driver signal to the transmission medium.

Abstract: An active noise control system generates an anti-noise signal to drive a speaker to produce sound waves to destructively interfere with an undesired sound in a targeted space. The speaker is also driven to produce sound waves representative of a desired audio signal. Sound waves are detected in the target space and a representative signal is generated. The representative signal is combined with an audio compensation signal to remove a signal component representative of the sound waves based on the desired audio signal and generate an error signal. The active noise control adjusts the anti-noise signal based on the error signal. The active noise control system converts the sample rates of an input signal representative of the undesired sound, the desired audio signal, and the error signal. The active noise control system converts the sample rate of the anti-noise signal.

Abstract: An audio testing system is configured for receiving an audio signal from the an audio emitting device. The system samples the audio signal and obtains sampling points from the audio signal for determining if the audio signal has been distorted. A related method is also disclosed.

Abstract: The present invention provides an analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic.

Abstract: A transceiver includes a processor and an analog-to-digital converter. The processor is adapted to in a transmit mode of the transceiver, generate a modulated signal in response to a first digital signal. In a receive mode of the transceiver, the processor is adapted to generate a demodulated signal in response to a second digital signal. The analog-to-digital converter provides the first digital signal in the transmit mode and provides the second digital signal in the receive mode.

Abstract: A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal.

Abstract: A device for processing data adapted for being converted between an analog format and a digital format, the device having a scrambling unit adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format.

Abstract: A tracking analog-to-digital converter “ADC” with a self-controlled variable clock comprises: a digital register; a digital-to-analog converter “DAC” coupled to said digital register providing an analog feedback signal; a comparator coupled to an analog input signal and said analog feedback signal and providing a comparison signal based on a comparison between said analog input signal and said analog feedback signal, said comparison signal being coupled to the digital register; a means for determining comparator readiness to determine if said comparator is ready, indicating that said comparison signal can be reliably read, said means for determining comparator readiness further comprising a determination of a comparison ready indicator; a means for clocking to generate a clock signal to drive said digital register in response to said means for determining comparator readiness determining that said comparator is ready; and said digital register being configured to count in response to said clock signal based o

Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.

Abstract: Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator.

Abstract: A signal processing circuit includes a production part configured to produce a first analog signal, an A/D conversion part configured to convert the first analog signal output from the production part to a first digital signal, a processing part configured to process the first digital signal output from the A/D conversion part into a second digital signal, and a D/A conversion part configured to convert the second digital signal to a second analog signal and output the second analog signal via an output terminal.