Abstract: An apparatus for inserting delay according to an embodiment includes a signal generating circuit, a plurality of carry elements, and a delay chain circuit. The delay chain circuit includes one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs. Each of the plurality of enable inputs is provided in a respective one of the delay modules. The delay chain circuit is configured to generate an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay, and is configured to provide the selected amount of delay to the signal generating circuit, which is configured to incorporate the delay into the start signal.

Abstract: A delta-sigma A/D converter includes a loop filter including a resonant filter, a quantizer, and a feedback D/A converter. The resonant filter includes a resonator including a resistor and a capacitor, and a feedback path through which an output of the resonator is positively fed back to an input of the resonator. The resonant filter operates as an oscillator or a filter under the on/off control of a first switch. At least one of the resistor and the capacitor of the resonator is configured to allow a resistance value or a capacitance value thereof to be adjusted based on a third external signal.

Abstract: Circuit arrangement, including a first resistor, a second resistor, a current source and an analog-to-digital converter. The second resistor is thermally coupled to the first resistor. The current source is coupled to the second resistor. The analog-to-digital converter is configured to receive a first voltage measured via the first resistor as a voltage to be digitized, and is configured to receive a second voltage measured via the second resistor as a reference voltage of the analog-to-digital converter.

Abstract: An analog-to-digital conversion loop adapted to generate a digital output signal corresponding to a low-pass filtered replica of an analog input signal, including an analog adder configured to receive the input analog signal and an analog feedback signal, adapted to generate an analog error signal corresponding to the difference between the analog input signal and the analog feedback signal; an analog-to-digital converter having a nonlinear input-output conversion characteristic defining a larger quantization step the more the input to be converted differs from a null value, configured to receive the analog error signal and to generate a corresponding digital error signal a digital integrator configured to receive the digital error signal, configured to generate the digital output signal corresponding to the time integration of the digital error signal; a digital-to-analog converter, configured to receive the digital output signal and to generate the analog feedback signal as analog replica of the digital out

Abstract: A method and a corresponding device for calibrating an interleaved analog-to-digital converter (ADC) involve injecting a pulsed, substantially-random signal into a plurality of channels in the ADC. After the substantially-random signal is injected, a gain correlation value is determined for each channel, which value indicates a degree of correlation between the injected substantially-random signal and an output of the respective channel. The gain correlation values are then compared to determine a degree of mismatch between the channels. At least one of the channels is calibrated as a function of the determined degree of mismatch.

Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.

Abstract: A system and a method of generating an external parameter value for a separately excited motor controller are disclosed, the system including: a digital signal processor to convert a received analog electrical signal into a digital signal and to scale the digital signal, so as to generate a parameter value in conformity with a data format of the system; an external parameter generating module to adjust the parameter value with a calibration coefficient to obtain the external parameter value; the calibration coefficient being generated by a calibration coefficient generating module and being pre-stored in a calibration coefficient storing module; and a calibration coefficient generating module to read the parameter value generated by the digital signal processor and obtain an actual measuring value as a reference parameter value, to calculate a difference value between the parameter value from the digital signal processor and the reference parameter value, and to generate the calibration coefficient from a rat

Abstract: A circuit for testing digital-to-analog (DAC) and analog-to-digital converters (ADC) is provided. The circuit applies a code pattern having a plurality of sequential values to the digital to analog converter. A plurality of built-in test switches (BTS) couple at least one tap voltage from the DAC to a test bus and to the ADC as a variable reference input voltage. In one form, the circuit uses incremental digital codes to test for defects in a resistor string, a switch array, and a decode logic that form part of the DAC. In another form, the circuit uses the tap voltages from the DAC to test the comparators that form part of the ADC. Instead of performing time-consuming analog to digital conversions, the functionality of the above mentioned circuitry is tested by varying the code pattern around a reference point and by selecting the appropriate combination of BTS switches.

Abstract: An ADC which samples an analog input signal at a sampling frequency and converts the analog input signal to a digital output signal, has N analog digital converter (ADC) channels which convert the analog input signal into the digital output signal by time interleaving, a channel synthesizer which synthesizes channel digital signals output respectively by the ADC channels to generate the digital output signal, an adaptive filter provided at at least one output of the ADC channels, and a correction circuit which generates a coefficient of the adaptive filter in accordance with the digital output signal. The correction circuit calculates a DC component of an image signal component, from among an analog input signal component and the image signal component corresponding to error, both being included in the digital output signal, and calculates the coefficient such that the DC component is suppressed on the basis of the DC component.

Abstract: A signal generating circuit, may include an analog signal generator having an output and a control input, the analog signal generator configured to generate at the output an analog output signal in accordance with a timing parameter; an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the analog signal generator, the ADC configured to generate a sequence of signal values dependent on the analog signal received at the input; a configurable digital signal generator comprising an output and a control input, the digital signal generator configured to generate a digital output signal in accordance with signal parameters received at the control input; and a control circuit having an input coupled to the output of the ADC.

Abstract: The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error.

Abstract: A method may include measuring a frequency difference between an actual frequency and an expected frequency associated with a frequency control calibration signal value for each of a plurality of frequency control calibration signal values during a calibration phase. The method may additionally include generating integral non-linearity compensation values based on the frequency differences measured The method may further include generating the applied frequency control signal based on a frequency control calibration signal value received by the digital-to-analog converter during the calibration phase. The method may also include generating a compensated frequency control signal value based on a frequency control signal value received by the integral non-linearity compensation module and an integral non-linearity compensation value associated with the frequency control signal value during an operation phase of the wireless communication element.

Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.

Abstract: A method and circuit to perform noise shaped splitting of a digital input signal may include using multiple layers to process the input signal. In the first layer, the most significant bits of the input signal may be distributed to a plurality of branches. Dynamic element matching may be performed using the least significant bits of the input signal. Based on the results of the dynamic element matching, values may be added to the plurality of branches. If there is insufficient data activity, dynamics enhancement may be performed to increase the data activity. The output signals of each of the plurality of branches in the first layer may be provided to a second layer, in which these steps can be repeated on each of the output signals. The outputs of the second layer may be provided to a plurality of three level unit elements.

Abstract: A method for evaluating capacitor weighting of an analog-to-digital (ADC) is provided. An equivalent weighting value of each composed capacitor in each sub-capacitor-array may be obtained by adding the switch device to the ADC which enables each sub-capacitor-array in a digital-to-analog (DAC) to be measured by each other. The ADC can calculate and then obtain a correct digital output by using the calibrated equivalent weighting and successive approximation result of each input signal.

Abstract: A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal.

Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract: A system and method of reducing the effects of nonidealities of ADCs in multipath converters is disclosed. The system and method employs a variety of measure and correction blocks to determine statistical properties of the output stream of the multipath converter and to apply corrections to the operation of the subconverters of the multipath converter based upon differences in the measured statistics and expected target values, either explicit or implicit, for those statistics. A variety of examples of possible measure and configuration blocks are disclosed, as is the cascading of the measure and correction blocks to correct multiple errors in the output of the multipath converter. Feedforward (purely digital) and feedback (analog and digital) solutions are both disclosed.

Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.

Abstract: An ADC has ADC channels converting an analog input signal into an digital output signal in a time interleave manner; a channel combiner combining channel digital signals respectively output by the ADC channels and generate the digital output signal; an adaptive filter provided at one of the plurality of ADC channels; and a correction circuit detecting a skew error in the digital output signal, generating a coefficient of the adaptive filter according to the skew error for setting it in the filter. According to the skew error, in a first setting, the correction circuit sets the coefficient such that the adaptive filter phase-shifts to one direction a phase of the channel digital signal and, in a second setting, the correction circuit sets the coefficient such that the adaptive filter phase-shifts to an opposite direction and sets a coefficient with which the skew error is suppressed to a desired level.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: A method and a corresponding device reduce the convergence time of a correlation algorithm that uses random signals injected into an analog-to-digital converter (ADC) as input to the algorithm. The method and device involve, at a processor of a pipelined ADC, injecting a random signal into each of a plurality of stages in the pipeline and obtaining digital values generated in response to the random signals. Noise components of residue signals in the plurality of stages are calculated as a function of the digital values and values of the random signals. The noise components correspond to the random signals.

Abstract: A pipeline analog-to-digital converter is disclosed. An example of a pipeline analog-to-digital converter comprises a plurality of stages. Each of the plurality of stages comprises an analog-to-digital conversion circuit comprising a comparator configured to produce an n-bit digital domain output; and a switchable conductance digital-to-analog conversion circuit operatively coupled to the comparator and configured to switch between at least two conductance values in response to a value of the n-bit digital domain output.

Abstract: An exemplary integrated circuit for performing time skew extraction includes a first subtractor, an array of subtractors separate from the first subtractor, and an array of averaging circuits. Inputs of the first subtractor are coupled to outputs of a plurality of channels of an interleaved analog-to-digital-converter and computes distances between samples of a signal that are measured consecutively by pairs of channels in the plurality of channels. At least some averaging circuits in the array of averaging circuits compute an average of those of the distances that correspond to a respective one of the pairs of channels; one averaging circuit in the array of averaging circuits computes an average of all of the distances. Each subtractor in the array of subtractors computes a difference between an average computed by one of the at least some of the averaging circuits and the average of all of the distances.

Abstract: An example digital-to-analog converter includes a reference scaling circuit receiving a first reference current and generating a second reference current. A first plurality of current sources is coupled to a summing node with a current of a first one of the first plurality of current sources proportional to the first reference current. A current of a second one of the first plurality of current sources is substantially equal to twice the current of the first one of the first plurality of current sources. A second plurality of current sources is coupled to the summing node. A current of a first one of the second plurality of current sources is proportional to the second reference current. A current of a second one of the second plurality of current sources is substantially equal to twice the current of the first one of the second plurality of current sources.

Abstract: The invention concerns a sigma-delta switched capacitor analog to digital converter (ADC) having: an input line for receiving a signal to be converted; first, second and third inputs for respectively receiving first, second and third test voltages; and switching circuitry adapted to apply, during a test mode of the sigma-delta ADC, a ternary test signal to the input line by periodically selecting, based on a digital test control signal, one of the first, second or third test voltages to be applied to the input line.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: The present disclosure relates to a calibration circuit for an analog-to-digital converter (ADC). The calibration circuit includes a digital-to-analog converter (DAC) configured to generate a calibration voltage from a digital input, and a DC feedback control circuit. The DC feedback control circuit includes an ADC driver configured to operate in both an ADC calibration mode and in an ADC operation mode such that dynamic parameters of the ADC driver are unchanged when the ADC driver is operating in the ADC calibration mode and when the ADC driver is operating in the ADC operation mode. The DC feedback control circuit is also configured to: receive the calibration voltage from the DAC; modify the calibration voltage by cancelling offsets in the calibration voltage; and provide the modified calibration voltage to the ADC.

Abstract: A sampling circuit includes a continuous section which is a circuit for transmitting a continuous signal; a digital section for transmitting a signal which is sampled and quantized; and a sampling and holding section for transmitting a signal which is sampled but not quantized between the continuous section and the digital section. The sampling and holding section includes capacitors for accumulating charge generated by an input signal and plural switches for accumulating the charge in the capacitors. The plural switches receive plural clock signals having different operation timings and perform an ON/OFF operation in response to the supplied clock signals.

Abstract: An image processing system includes a pixel array including a plurality of regular pixel columns and at least one test pixel column, a plurality of column analog-to-digital converters (ADCs) configured to correspond to the regular pixel columns and convert analog input signals into digital signals, and a switching block configured to provide output signals of the regular pixel columns to input ends of the corresponding column ADCs in a normal mode, and provide in common an output signal of the test pixel column to the input ends of the column ADCs in a test mode, wherein the test pixel column generates signals having a minute voltage different from one row to another row.

Abstract: Circuits, methods, non-transitory storage media can be configured to reduce calibration errors in a signal converter. A digital-to-analog converter can include a calibration circuit configured to calibrate a digital-to-analog converter (DAC) bit element using a residual error from a previously calibrated digital-to-analog converter (DAC) bit element. The residual error can be stored in memory.

Abstract: A method and apparatus for controlling the effective gain of an ADC when the ADC is occasionally or continuously calibrated using the statistics of the input signal and when the statistics are not stationary.

Abstract: A reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. Samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

Abstract: A method of background calibration of aperture center errors in a data communication system is provided. In an implementation, in response to detection of a low sampler output (“0”) in between two high sampler outputs (“1”), the method includes: calculating a signal derivative of an ADC output signal at the time of the detected low output; and adjusting timing at a selected sampler based on the calculated signal derivative. In an example implementation, the method includes watching for bubbles in the thermometer code output, and estimating the first derivative of the signal at the time of the bubble, then estimating the sign of the errors. In an example implementation, the errors are used in a control loop to reduce the aperture center error.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of ?1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract: A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref/2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.

Abstract: When an enable signal representing an offset calibration mode is received, a continuous time delta-sigma modulation apparatus generates a first signal using first and second pulse signals representing outputs of the continuous time delta-sigma modulation apparatus and an operation frequency of the continuous time delta-sigma modulation apparatus, generates first and second output bits by performing a counting operation according to a counting method that is determined according to a pulse signal of first and second comparators, applies a voltage corresponding to the first output bit to a body of a first transistor of a primary integrator, and applies a voltage corresponding to the second output bit to a body of a second transistor of the primary integrator.

Abstract: A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.

Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator includes a multi-stage loop filter, a quantizer, and a digital-to-analog converter. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. Each stage of the multi-stage loop filter includes a feedback network. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. The digital-to-analog converter receives the digital output signal and converts the digital output signal to a compensation signal. The digital-to-analog converter provides the compensation signal to a plurality of internal nodes in the feedback network of the last stage of the multi-stage loop filter.

Abstract: A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.

Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

Abstract: An apparatus and method for inserting delay into a start signal of a metastable ring oscillator chain-based time-to-digital circuit (TDC). Included therein is a signal generating circuit that generates the start signal, a plurality of carry elements connected as a chain, each of the carry elements having an input to receive a stop signal, a delay chain circuit including one or more delay modules selected from the plurality of carry elements, at least one feedback line connected between at least one of the delay modules and the signal generating circuit, and a plurality of enable inputs each provided in a respective one of the delay modules. The delay chain circuit generates an amount of delay based on a delay selection signal that is received at the enable inputs and that selects the amount of delay. The delay chain circuit additionally provides the selected amount of delay to the signal generating circuit, which incorporates the delay into the start signal.

Abstract: Embodiments of the present invention may provide an improved apparatus and method for correcting timing errors associated with process, voltage, and temperature effects in asynchronous successive approximation register (SAR) analog-to-digital converters (ADC). A SAR ADC may include a timer comprising programmable timing circuits that may ensure that the different components of the SAR ADC are operating according to a timing scheme. Operation of the timing circuits may vary with process, voltage, and temperature, which may adversely affect the timing/accuracy of the SAR ADC. The ADC may include a reference circuit provided on the same integrated circuit as the SAR ADC that may provide a timing reference for the timing circuits. If the reference circuit indicates that the timing circuits are operating faster or slower than ideal, timing values within the timing circuits may be revised to compensate for such variations.

Abstract: A method and device for testing a digital-to-analog converter is provided. The method may include configuring a decoder to address an individual unit cell of a plurality of unit cells of a digital-to-analog converter. The configured decoder may select a particular unit cell of the plurality of unit cells for testing. The selected unit cell may have digital and analog circuitry. A bias current of the selected unit cell may be increased. The increased bias current of the selected unit cell may be greater during the testing than during normal operation. A test logic signal may be applied to the selected unit cell. In response to the test logic signal, an output signal may be output from the selected unit cell logic circuitry of the digital-to-analog converter. A device may include logic circuitry configured to select an individual unit cell for testing and a current generating circuitry.

Abstract: A method for encoding an audio signal including: processing a selected subset of a lower series of samples forming a lower frequency spectral band of the audio signal and a higher series of samples forming a higher frequency spectral band of the audio signal to parametrically encode the higher series of samples forming the higher frequency spectral band by identifying a sub-series of the lower series of samples.

Abstract: A sigma-delta converter may include a filter coupled to a first summation circuit and a second summation circuit. A multi bit quantizer may be coupled to the second summation circuit. A single bit digital-to-analog converter (DAC) may be included that defines a feedback path between the multi-bit quantizer and the first summation circuit. A feed-forward coefficient circuit defining a feed forward path between the first summation circuit and the second summation circuit may be included.