Trimming Control Circuits Patents (Class 341/121)
  • Patent number: 11777513
    Abstract: A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: October 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karthikeyan Gunasekaran, Snehasish Roychowdhury, Rakesh Manjunath, Aswath V S, Sthanunathan Ramakrishnan, Sarma Sudareswara Gunturi, Rahul Sharma, Jagannathan Venkataraman, Nagarajan Viswanathan
  • Patent number: 11031949
    Abstract: An analog-to-digital converter comprises a first integrator (40), a first converter input (19), a first reference voltage input (34), a capacitor array (68) comprising capacitor elements (171), and a rotation frequency control unit (37) providing a rotation signal (SRO) with at least two different values of a rotation frequency (fR). A first subset of capacitor elements (171) of the capacitor array (68) is coupled to the first converter input (19) and to an input side of the first integrator (40) in a first phase and is coupled to the first reference voltage input (34) and to the input side of the first integrator (40) in a second phase as a function of the rotation signal (SRO).
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: June 8, 2021
    Assignee: AMS AG
    Inventors: Jose Manuel García González, Rafael Serrano Gotarredona
  • Patent number: 10957237
    Abstract: A semiconductor device with lower power consumption or a display device including the semiconductor device is provided. A circuit to which an N-bit signal is input includes a first digital-to-analog converter circuit to which an upper M-bit signal is input, a second digital-to-analog converter circuit to which a lower (N?M)-bit signal is input, and an amplifier circuit. The amplifier circuit includes a first transistor and a second transistor. An output terminal of the first digital-to-analog converter circuit is electrically connected to a gate of the first transistor. An output terminal of the second digital-to-analog converter circuit is electrically connected to a substrate potential of the second transistor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. An output terminal of the amplifier circuit is electrically connected to a gate of the second transistor.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: March 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Hiroyuki Miyake
  • Patent number: 10340941
    Abstract: A digital-to-analog converter (DAC) includes a first stage comprising a plurality of first circuit arms coupled together, each first circuit arm including a resistor. A second stage includes a plurality of second circuit arms coupled together, each second circuit arm comprising a first resistor and a pair of series-connected resistors. The first resistors of the second circuit arms are connected in series. A current digital-to-analog converter (IDAC) trim circuit is connected to a plurality, but not all, of the second circuit arms of the second stage. The IDAC trim circuit includes a plurality of first current sources. Each first current source is coupled to a respective node between a pair of the series-connected resistors of a corresponding second circuit arm, and each of the first current sources is configured to produce a same current level as the other first current sources.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gautam Salil Nandi
  • Patent number: 10291207
    Abstract: A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, ?6 dB) relative to the maximum resistance value. Coarse increments of ?6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 14, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Alexandru Aurelian Ciubotaru, Robert C. Glenn
  • Patent number: 9641186
    Abstract: Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.
    Type: Grant
    Filed: June 6, 2015
    Date of Patent: May 2, 2017
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Alan L. Westwick
  • Patent number: 9625500
    Abstract: An A/D converter has an analog input terminal, an analog output terminal, a digital output terminal, a first resistance comprising one end connected to the analog input terminal or a reference voltage line and another end connected to a first node, a second resistance comprising one end connected to the first node and another end connected to the analog output terminal, an operational amplifier comprising a first input terminal connected to the first node, a second input terminal connected to the reference voltage line or the analog input terminal, and an output terminal connected to the analog output terminal, a quantizer comprising an input terminal connected to the analog input terminal and an output terminal connected to the digital output terminal, and a DA converter comprising an input terminal connected to the digital output terminal and an output terminal connected to the first node.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 18, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kentaro Yoshioka, Tetsuro Itakura, Masanori Furuta
  • Patent number: 9548752
    Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATION
    Inventors: Neeraj Shrivastava, Supreet Joshi, Himanshu Varshney, Jafar Sadique Kaviladath, Visvesvaraya Pentakota, Shagun Dusad
  • Patent number: 9331709
    Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 3, 2016
    Assignee: LINEAR TECHNOLOGY CORPORATION
    Inventor: Jesper Steensgaard-Madsen
  • Patent number: 9086450
    Abstract: A capacitor measurement circuit for measuring a capacitance of a test capacitor includes a first transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; and a current-measuring device configured to measure a first charging current and a second charging current of the test capacitors. The first and the second charging currents flow to the test capacitor in opposite directions.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Tar Liu, Chih-Chiang Chang, Chu-Fu Chen, Ping-Hsiang Huang
  • Patent number: 9035810
    Abstract: A system and method are provided for measuring current sources, such as might be useful in the calibration of a digital-to-analog converter (DAC). The method provides a first plurality of current sources. Each current source is engageable to supply a current representing a corresponding nominal value. The method selectively enables current source combinations of current. In response to measuring the current source combinations, current difference values are found, and the current source nominal values are adjusted using the current difference values. In one aspect, a reference current source is provided having a reference first value, and the current source nominal values are adjusted with respect to the reference first value. The current sources may have corresponding nominal digital values adjusted using measured digital difference values.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 19, 2015
    Assignee: IQ—Analog Corporation
    Inventors: Mikko Waltari, Costantino Pala
  • Patent number: 9013338
    Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 21, 2015
    Inventor: Benjamin H. Ashmore, Jr.
  • Patent number: 9007242
    Abstract: A delta-sigma modulator and corresponding method are disclosed. In one implementation, the delta-sigma modulator includes a multiplexer for receiving an analog input signal and a common mode signal and outputting a multiplexed signal in accordance with a selection signal; a summing circuit for receiving the multiplexed signal and an analog feedback signal and outputting an error signal; a loop filter for receiving the error signal and outputting a filtered signal; a quantizer for receiving the filtered signal and outputting a raw digital output signal; a digital-to-analog converter for receiving the raw digital output signal and outputting the analog feedback signal along with a rotated digital output signal in accordance with a phase indicator and a rotation number; and a calibration logic for receiving the rotated digital output signal and a mode indicator and outputting the selection signal, the phase indicator, the rotation number, and a calibrated digital output signal.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: April 14, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 8907828
    Abstract: A method for testing the material of a test object (8) in a nondestructive manner, said test object being moved relative to a probe (1) at a variable relative speed, comprises the following steps: detecting a probe signal (US) by means of the probe (1), subjecting the probe signal (US) to analog-to-digital conversion in order to generate a digitized probe signal (USD) in the form of a sequence of digital words with a predefined, in particular constant, word repetition rate, n-stage decimation of the word repetition rate of the digitized probe signal (USD) or of a digital demodulation signal (UM) derived from the digitized probe signal by means of n cascaded decimation stages (5_1 to 5_n), where n?2, selecting an output signal (UA_1 to UA_n) of one of the n decimation stages (5_1 to 5_n) depending on the instantaneous relative speed and filtering the selected output signal by means of a digital filter (7), which is clocked with the word repetition rate of the selected output signal.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: December 9, 2014
    Assignee: Institut Dr. Foerster GmbH & Co. KG
    Inventors: Bernhard Holzmayer, Michael Halter
  • Patent number: 8866651
    Abstract: An analog-to-digital converter includes an input terminal to which an analog input voltage is input, a digital-to-analog converter unit, a comparator that compares the analog input voltage and an output voltage of the digital-to-analog converter unit with each other, a successive approximation register that stores a conversion result output from the comparator, a generator unit that generates added digital data and subtracted digital data, the added digital data and the subtracted digital data being obtained by adding and subtracting the conversion result to and from the conversion result retained by the successive approximation register, respectively, and a determination unit that determines whether or not a failure is occurring, by using a result of the comparison between the analog input voltage and output levels obtained by the digital-to-analog converter unit converting the added digital data and the subtracted digital data.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyuki Arai, Isao Sezaki
  • Patent number: 8836557
    Abstract: A method for signal processing includes accepting an analog signal, which consists of a sequence of pulses confined to a finite time interval. The analog signal is sampled at a sampling rate that is lower than a Nyquist rate of the analog signal and with samples taken at sample times that are independent of respective pulse shapes of the pulses and respective time positions of the pulses in the time interval. The sampled analog signal is processed.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Technion Research & Development Foundation Ltd.
    Inventors: Yonina Eldar, Ewa Matusiak
  • Patent number: 8791847
    Abstract: A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: July 29, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Peijun Wang, Robert S. Jones
  • Patent number: 8786482
    Abstract: In one embodiment, an integrated circuit includes a pin and a current source for driving current through the pin into an external resistor such as a resistor on a circuit board to generate a pin voltage. The integrated circuit includes an analog-to-digital converter for converting the pin voltage into a digital value, such as an address for the integrated circuit.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Lattice Semiconductor Corporation
    Inventors: Robert Bartel, Spiro Sassalos
  • Patent number: 8717208
    Abstract: An image processor includes a readout arranged to read out an M-bit image data word from an image sensor pixel array and an adder arranged to add a noise contribution to the image data word to obtain a dithered M-bit word. A dither processor is arranged to derive correction data having a word size of M+1 bits from a combination of a plurality of M-bit reference words. The noise contribution are derived from said correction data, wherein different correction data are derived for different groups of pixels, each different group of pixels is associated with a specific pixel value DC shift.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventor: John Kevin Moore
  • Patent number: 8681027
    Abstract: A digital receiver includes: an analog-to-digital (AD) converter (102) for setting discrimination levels in accordance with a discrimination level control signal and converting an analog input signal into a digital signal based on the set discrimination levels; a discrimination level adjusting circuit (104) for generating the discrimination level control signal and outputting the discrimination level control signal to the AD converter; a signal quality monitoring portion (108) for generating a transfer function correction control signal, which is information about a transfer function of the AD converter; and a transfer function correcting circuit (106) for performing signal processing on the digital signal so as to cancel a gap between the transfer function of the AD converter and an initial transfer function based on the transfer function correction control signal.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: March 25, 2014
    Assignee: NEC Corporation
    Inventors: Junichi Abe, Hidemi Noguchi
  • Patent number: 8648740
    Abstract: The invention provides a testing apparatus. In one embodiment, the testing apparatus receives a plurality of bit signals output by an analog-to-digital converter, and comprises a plurality of frequency counters and a comparison module. The frequency counters respectively calculate a plurality of transition frequencies of the values of the bit signals. The comparison module respectively compares the transition frequencies with a plurality of ideal transition frequencies to obtain a plurality of error frequencies. The performance analysis module estimates a performance value of the analog-to-digital converter according to the error frequencies.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: February 11, 2014
    Assignee: Silicon Motion, Inc.
    Inventor: Hung-Sheng Chang
  • Patent number: 8547256
    Abstract: An ADC code given in response to input of an analog input value to an A/D converter circuit is measured at a site where an A/D converter unit is used to measure a user-measured value. A user-set value calculating part calculates a user offset value and a user gain value on the basis of one user-measured value, a factory offset value, and a factory gain value, and stores the calculated user offset value and the user gain value in a nonvolatile memory.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: October 1, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Haruyuki Kurachi
  • Patent number: 8502714
    Abstract: A method for calibrating at least one analog-to-digital converting circuit includes: during a wafer level probe testing, inputting at least one calibration signal provided by a wafer level testing machine into the analog-to-digital converting circuit to generate at least one digital signal; and calibrating the analog-to-digital converting circuit according to at least the digital signal. The analog-to-digital converting circuit is applied to a video system or an audio system.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventors: Chien-Ming Chen, Chen-Yu Hsiao
  • Patent number: 8497791
    Abstract: A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: July 30, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Okumura, Ryusuke Sahara, Mitsugu Kusunoki
  • Patent number: 8446304
    Abstract: The invention provides a digital background calibration system and method for a successive approximation analog-to-digital converter comprising a digital to analog converter (DAC) having a plurality of weighted capacitors to be calibrated; means for splitting each of said weighted capacitors into a plurality of sub-capacitors and at least one redundant capacitor; means for multiplying the voltage level of at least one of the sub-capacitors with a PN sequence; and means for calibrating the weighted capacitor from the multiplied sub-capacitor and the redundant capacitor.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 21, 2013
    Assignee: University of Limerick
    Inventor: Anthony Gerard Scanlan
  • Patent number: 8441382
    Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: May 14, 2013
    Assignee: STMicroelectronics Pvt. Ltd.
    Inventors: Puneet Mahajan, Anand Singh Rawat, Anil Kumar
  • Patent number: 8421659
    Abstract: A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: April 16, 2013
    Assignee: Dialog Semiconductor GmbH
    Inventor: Hans Martin von Staudt
  • Patent number: 8421658
    Abstract: A Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) predicts compensation values for use in a future cycle. A compensation value is applied to capacitors in a calibration Y-side capacitor array to compensate for capacitance errors in a binary-weighted X-side capacitor array. Two compute engines pre-calculate predicted-0 and predicted-1 compensation values for a next bit to be converted. At the end of the current cycle when the comparator determines the current bit, the comparator also controls a mux to select one of the two predicted compensation values. Thus the compensation value is available at the beginning of the next bit's cycle, eliminating a long calculation delay. The compensation value for the first bit to be converted, such as the MSB, is calculated during calibration. Compensation values for other bits are data-dependent. Calibration values are accumulated during calibration to generate the first conversion compensation value for the first bit to be converted.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: April 16, 2013
    Assignee: Hong Kong Applied Science & Technology Research Institute Company, Ltd.
    Inventors: Hok Mo Yau, Tin Ho (Andy) Wu, Kam Chuen Wan, Yat To (William) Wong
  • Patent number: 8350737
    Abstract: A flash analog to digital converter and a method and system for dynamically calibrating the flash analog to digital converter. The analog to digital converter may include a track and hold circuit and a plurality of comparators. The analog to digital converter may also include an under-sampling circuit configured to convert a digitized reference signal into an under-sampled digitized reference signal with a frequency of the calibration frequency divided by a positive number M. The under-sampling circuit may be further configured to calibrate a subsequent signal based on the under-sampled digitized reference signal.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mihai A. T. Sanduleanu, Jean-Oliver Plouchart
  • Patent number: 8314725
    Abstract: In one embodiment, an analog-to-digital conversion in an integrated circuit is evaluated by an on-die testing circuit. For example, the on-die test circuit 370 can characterize one or both of the linearity and monotonicity of the digital-to-analog conversion. The value of a conversion output for a digital input code may be compared to the value of a prior conversion output of a prior step to provide digital difference values for each step of a sweep of digital input codes. Digital difference values may be compared to one or more predetermined limits to provide one or more pass/fail tests on-board the die. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Paola Zepeda, David E. Duarte, Gregory F. Taylor, Atul Maheshwari
  • Patent number: 8314726
    Abstract: A circuit and method for providing a digital output indicative of the time at which an event occurred is disclosed. In one aspect, the circuit includes a fine timing circuit configured to determine in which sub-interval of a clock period the event occurred, and a correction circuit configured to correct an erroneous offset between a first and second clock signals in the fine timing circuit. The correction circuit includes a synch circuit configured to determine in which half of the clock period the event occurred so as to correct for erroneous offset in the fine timing circuit.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: November 20, 2012
    Assignee: IMEC
    Inventors: Francesco Cannillo, Patrick Merken, Munir Abdalla Mohamed, Osman Allam
  • Patent number: 8253612
    Abstract: A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N?1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: August 28, 2012
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8248280
    Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 21, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Sanyi Zhan, Daniel J. Cooley, Ligang Zhang
  • Publication number: 20120206283
    Abstract: A trim DAC wherein the digital input bits to the trim DAC are controlled by a state machine to produce an analog output that is within a least significant bit of the digital input bits. An undersize factor between digital input bits is used to assist in finding a trim solution for major transitions of the digital input bits. Trim solutions are stored in a nonvolatile memory associated with the state machine to be used in creating an accurate analog output.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 16, 2012
    Inventor: Hans Martin von Staudt
  • Patent number: 8228220
    Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: July 24, 2012
    Inventor: Benjamin H. Ashmore, Jr.
  • Patent number: 8134485
    Abstract: An analog to digital converting device has a first converter nonlinearly converting an analog level into a first digital value every first sampling period, shorter than a second sampling period, with low precision, a second converter linearly converting the analog level into a second digital value every second sampling period with high precision, and a controller determining a correction equation by using the second digital value having a high precision in each second sampling period so as to renew the equation every second sampling period, and correcting the first digital values, obtained in each second sampling period, to corrected digital values according to the corresponding correction equation to output the corrected digital value as a digital value, obtained by substantially linearly converting the analog level, every first sampling period.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 13, 2012
    Assignee: Denso Corporation
    Inventor: Hiroshi Tamura
  • Patent number: 8130323
    Abstract: A video signal processing system including a digital signal processing (DSP) module, a digital offset module coupled to the DSP module, a gain module, and a digital to analog converter (DAC) coupled to the DSP module and to the gain module, wherein the DAC is configured to cause the gain module to provide multiple gain signals having predetermined first values to the DAC, cause, for each of the multiple gain signals, a digital input signal value to the DAC to be ramped up, determine, for each of the multiple gain signals, a lowest digital input signal value that causes an output voltage of the DAC to be at least as high as a reference voltage, and determine a second gain value that will cause the DAC to provide a desired DAC output voltage in response to the DAC receiving a reference DAC input value.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: March 6, 2012
    Assignee: ATI Technologies, Inc.
    Inventor: Brett Hilder
  • Patent number: 8120517
    Abstract: A digital-analog conversion circuit includes a correction unit that adds a correction bit to a lower-order bit of externally input first digital input data and outputs second digital input data, and a conversion unit that receives the second digital input data and outputs an analog value, and the correction unit generates the second digital input data by manipulating data of a lower-order bit of the second digital input data around a point at which an error between the analog value and an expected value set for the first digital input data becomes larger than a preset value.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Wataru Saito
  • Patent number: 8106800
    Abstract: An approach for calibrating a signal reconstruction system. A signal may be input to a low-pass filter. An output of the filter may be converted to a digital signal which goes to a processor which outputs a reconstruction of the signal to the filter. The reconstruction may be based on an expression that maintains the accuracy of the reconstruction. The expression may include information about samples of the input signal and a low value of the reconstruction. The expression may permit initial calibration and then maintenance of the calibration. The calibration may include compensating for inexpensive components of the filter which have values significantly different than indicated values and/or have large drifts over temperature changes.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: January 31, 2012
    Assignee: Honeywell International Inc.
    Inventor: Dean C. Matsen
  • Publication number: 20110298642
    Abstract: A current is generated from a reference voltage using an operational amplifier. The current is mirrored by a current mirror circuit to obtain a reference current. For example, the current mirror circuit includes a plurality of PMOS transistors. Based on the result of measurement of the reference current by an external monitor, the connection destination of the gate voltage of each of a plurality of mirror destination current source transistors is switched by an analog switch circuit between a power supply and the gate of a mirror source current source transistor, thereby changing the number of mirror destination current source transistors which are turned on, to change a current minor ratio. Thus, the current can be trimmed.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke NOMASAKI, Takeshi OKUMOTO
  • Patent number: 8035538
    Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Analog Devices, Inc.
    Inventors: Lawrence H. Edelson, Michael P. Daly, Trey A. Roessig
  • Patent number: 8031092
    Abstract: Methods and systems are described relating to dual-mode based digital background calibration of pipelined ADCs, for gain variations and device mismatches. Errors caused by gain insufficiency, nonlinearity, and capacitor mismatches are corrected by operating one ADC in two circuit configurations. These two modes are so arranged that their digital outputs differ in the presence of gain nonlinearity, gain insufficiency, and capacitor mismatches. The output difference is measured by randomly choosing one of the two operation modes at each sampling clock and digitally correlating the resulting digital output sequence. The measured output difference, which represents ADC errors, is used to remove the errors.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 4, 2011
    Assignee: President and Fellows of Harvard College
    Inventor: Nan Sun
  • Patent number: 7973686
    Abstract: An integrated circuit device includes a plurality of data line driver circuits, a first correction D/A conversion circuit, and a plurality of D/A conversion circuits. Each of the data line driver circuits includes an operational amplifier, an input capacitor, and a first correction capacitor. Each of the D/A conversion circuits outputs an output signal to the input capacitor. The first correction D/A conversion circuit outputs a correction output voltage to the first correction capacitors to correct data signals output from the data line driver circuits.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: July 5, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Motoaki Nishimura
  • Patent number: 7973688
    Abstract: An analog to digital converter (ADC) structure and method includes a photonic filter bank having at least two filters. The at least two filters are configured to create a corresponding spectral tributary from an input signal at a target rate, and the at least two filters are configured to exhibit orthogonality properties between respective tributaries. An optical/electrical (O/E) converter is coupled to each of the at least two filters in a respective spectral tributary to convert an optical input to an electrical output. An analog to digital converter (ADC) is coupled to each of the O/E converters in a respective spectral tributary to sample the electrical output at a fraction of a target rate and to convert a sampled analog electrical output into a digital signal. A synthesis filter is coupled to each of the ADCs in a respective spectral tributary to reconstruct the input signal digitally at the target rate.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: July 5, 2011
    Assignee: NEC Laboratories America, Inc.
    Inventors: Yue-Kai Huang, Ting Wang, Philip Nan Ji
  • Patent number: 7956777
    Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: June 7, 2011
    Inventor: Benjamin H. Ashmore, Jr.
  • Patent number: 7952501
    Abstract: A demodulator capable of compensating for an offset voltage of a radio frequency (RF) signal, and a method of compensating for the offset voltage of the RF signal are provided. The demodulator includes an analog-to-digital conversion (ADC) unit for converting a first analog signal corresponding to a difference between the RF signal comprising the offset voltage and an analog reference signal into a first digital signal, and a compensation voltage generation unit for converting the first digital signal into an offset compensation voltage. The ADC unit converts a second analog signal corresponding to a difference between the RF signal comprising the offset voltage and the offset compensation voltage into a second digital signal. Accordingly, the offset voltage included in the RF signal is compensated for, and thus distortion and a signal-to-noise ratio (SNR) of the RF signal are reduced. This leads to an improvement of the reception sensitivity of an RF receiver.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: May 31, 2011
    Inventors: Sung Wan Kim, Pyeong Han Lee, Sung Hun Chun
  • Patent number: 7852243
    Abstract: A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: December 14, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Jin Hwang, Kun-Woo Park, Yong-Ju Kim, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang
  • Patent number: 7843369
    Abstract: In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 30, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Tomomi Takahashi, Takashi Oshima, Taizo Yamawaki
  • Patent number: 7825838
    Abstract: A method for removing component mismatch errors for a system parameter being set by a ratio of two or more physical, electrical components (“components”) of the same kind on an integrated circuit including providing an array of component units having the same component value, determining the actual component values of each component unit in the array, selecting component units based on the actual component values to form pairs of component units where the pairs have approximately the same total component values, ordering the component unit pairs, assigning alternate component unit pairs to be associated with each of the two or more components, rotating at a first frequency the assignment of the component unit pairs. At each rotation, the component unit pairs to be associated with each component are shifted so that each component unit pair is associated with a different one of the two or more components in turn.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: November 2, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Theertham Srinivas, Vallamkonda Madhuri, DVJ Ravi Kumar, Gururaj Ghorpade, Priyanka Khasnis, Mehmet Aslan, Richard Dean Henderson
  • Patent number: 7821436
    Abstract: A system and method for reducing the power dissipated in an Analog to Digital Converter (ADC). The method includes the steps of: receiving a residue output from a previous phase of a plurality of clock phases where the plurality of clock phases includes a sample-and-hold phase and an amplifying phase for sampling and amplifying an analog input signal respectively, eliminating an effect of load on a residue amplifier when amplifying the residue output to generate an amplified residue output in the amplifying phase, and eliminating an effect of small feedback factor when sampling the amplified residue output in the sample-and-hold phase. Power advantage is achieved by sharing the load on the residue amplifier across the sample-and-hold phase and the amplifying phase rather than being fully present in any one of the clock phases. The present invention also provides a method for reducing the number of comparators used in ADCs.
    Type: Grant
    Filed: June 9, 2007
    Date of Patent: October 26, 2010
    Assignee: Cosmic Circuits Private Limited
    Inventors: Venkatesh Teeka Srinvasa Setty, Chandrashekar Lakshminarayanan, Prasun Kali Bhattacharya, Prasenjit Bhowmik, Chakravarthy Srinivasan, Mukesh Khatri, Sanjeeb Kumar Ghosh, Sumanth Chakkirala, Sundararajan Krishnan, Prakash Easwaran