Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract: Techniques and circuitry are presented for more rapidly and accurately obtaining a temperature code (TCO) on an integrated circuit. A comparison voltage is ramped up and two counts are determined concurrently, a first count on how many clock cycles for the comparison voltage to ramp up from a low reference voltage to a proportional to absolute temperature (PTAT) and a second count for the number of clock cycles for the comparison voltage to go from the low reference voltage to a high reference voltage. The TCO value is then obtained by using the second count in a post-processing calibration to adjust the first count. An initial calibration can also be included when the circuit is powered up.

Abstract: A sensor that can provide multiple resolutions, based on the output of the same analog-to-digital converter is disclosed. Some applications require a fast measurement of a physical parameter (e.g., temperature, voltage, pressure), but can tolerate a lower resolution measurement. Other applications require a higher resolution measurement, but can tolerate a slower measurement. The sensor may comprise a sigma delta modulator (SDM) ADC that outputs a digital reading. The output may comprise a bus having a width that is equal to the desired highest resolution of the digital code for the physical parameter. The sensor may further comprise a storage unit for each desired level of resolution. The sensor may further comprise logic that causes the storage units to sample the output bus after a certain number of clock cycles in order to store a digital code having a number of bits equal to the resolution.

Abstract: During a period of calibration of the ADC, the effect of unexpected external noise can be excluded. Provided is an analog to digital convertor including: an ADC that converts an analog value into a digital value; and an averaging circuit that calculates a correction value by a calibration operation. The converted value is corrected and output using the correction value being held in a normal operation. The analog to digital convertor is configured as follows. In the calibration operation, an elemental correction value on the basis of a converted value by the ADC corresponding to a predetermined analog value is supplied to the averaging circuit. The averaging circuit calculates the average value of the remaining elemental correction values obtained by removing the maximum value and the minimum value from the elemental correction values supplied a plurality of times, and calculates the correction value on the basis of the average value.

Abstract: A radio communication receiver apparatus is configured to process multiple radio frequency bands in a telecommunication system. The apparatus includes a plurality of digital receiver chains wherein each digital receiver chain is coupled to receive a digital representation of the multiple radio frequency bands, including a particular radio frequency band for processing by the respective digital receiver chain. Each digital receiver chain includes a digital receiver that is programmable to select a particular radio frequency band from the digital representation of the multiple radio frequency bands, and configured to down convert the selected radio frequency band into a digital baseband signal associated with the particular radio frequency band. Built in calibration is provided by operation of direct radio frequency technology.

Abstract: A time-interleaved digital-to-analog converter (DAC) architecture is provided. The DAC architecture includes a multiplexer/encoder configured to receive a data signal and to generate a plurality of data streams based on the data signal. First and second DAC circuits receive respective first and second data streams of the plurality of data streams and selectively process the respective first and second data streams to generate a respective DAC output signal. The respective DAC output signals of the first and second DAC circuits are coupled together to provide an output signal of the DAC architecture.

Abstract: Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g.

Abstract: System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

Abstract: An analog to digital converter (ADC) includes a comparator and a plurality of capacitor pairs coupled between first and second inputs the comparator, where each one of the capacitor pairs corresponds to one of a plurality of cycles used by the ADC to generate a digital value representing a sampled analog voltage. The ADC also includes a voltage detection circuit and a state machine that is configured to, upon determining during a first cycle that the sampled voltage across the first and second inputs satisfies a threshold, maintaining a first pair of the plurality of capacitor pairs in a default state such that the sampled analog voltage is unchanged. Otherwise, the state machine is configured to switch the first pair of the plurality of capacitor pairs to change the sampled analog voltage.

Abstract: A four-level pulse amplitude modulation transmitter and corresponding method are provided. The transmitter includes a most significant bit processing section and a least significant bit processing section. The transmitter further includes at least one termination resistor connected to respective outputs of the processing sections to provide a transmitter output. Each of the processing sections include a set of retiming latches arranged in a parallel for aligning input parallel data and providing parallel aligned latched outputs responsive to one phase of a quarter-rate four-phase quadrature clock. Each of the processing sections further includes a serializer for serializing the parallel aligned latched outputs to provide a serialized output using quarter-rates of the quarter-rate four-phase quadrature clock. Each of the processing sections also include an output driver for driving the serialized output.

Abstract: Certain aspects of the present disclosure provide methods and apparatus for calibrating a tunable active filter. One example apparatus is a filter circuit that generally includes a tunable active filter comprising at least one amplifier and a first feedback path coupled between an input and an output of the at least one amplifier, the first feedback path comprising at least one switch; and an amplitude limiter coupled to the tunable active filter and comprising at least one transistor disposed in a second feedback path coupled between the input and the output of the at least one amplifier.

Abstract: A hybrid SAR-ADC that uses a combination of voltage-based signal processing and time-based signal processing to convert an analog input signal to a digital output signal is disclosed. In some embodiments, the hybrid SAR-ADC has a voltage-based signal processing element configured to convert an analog input signal to a first digital signal having a plurality of MSBs and to generate a residue voltage from an input voltage and the first digital signal. A voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. A time-based signal processing element is configured to convert the time domain representation to a second digital signal comprising a plurality of LSBs. By determining the plurality of MSBs using voltage-based signal processing and determining the plurality of LSBs using time-based signal processing, the hybrid SAR-ADC is able to achieve low power and compact area.

Abstract: A self-healing data converter system including a data converter; a parametric function module coupled to the data converter to receive a target performance requirement for a data converter and produce a set of function values to the data converter; an assistant module that captures data converter performance under one or more stress conditions; and a processing module coupled to the data converter to stress the data converter in accordance with one or more predetermined parameters and based on the target performance requirement and data converter performance, the processing module determines new parameters based on a self-healing method and applies the new parameters to produce a new set of function values for the data converter until a predetermined threshold is met to adaptively self-heal the data converter to changed conditions.

Abstract: A system and method for low-power digital signal processing, for example, comprising adjusting a digital representation of an input signal.

Abstract: The embodiments of the present invention provide a nonlinear term selection apparatus and method, an identification system and a compensation system. The selection apparatus comprises: a linear coefficient calculator configured to measure linear properties of a nonlinear system by using measurement data, so as to obtain a plurality of linear coefficients; and a nonlinear term selector configured to select nonlinear model expanded terms of the nonlinear system by using the plurality of linear coefficients, so as to obtain nonlinear terms of the nonlinear system. With the embodiments of the present invention, the nonlinear model may be simplified, and the complexity of the nonlinear model may be lowered.

Abstract: A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

Abstract: A method of preventing inter-system interference while acquiring waveforms in a test and measurement instrument with variation in a device under test system S-parameters. The method includes receiving a waveform from a device under test at the test and measurement instrument, digitizing the waveform, identifying portions of the digitized waveform with different S-parameter characteristics, separating the identified portions of the digitized waveform into different waveforms, and displaying the different waveforms to a user.

Abstract: A pipeline analog-to-digital converter (ADC) converts an analog input signal over several stages, where a stage generates a residue for the subsequent stage to digitize. The residue is generated by coarsely quantizing the analog input signal to generate a digital code, which is used to reconstruct the analog input signal, and the residue is the difference between the analog input signal and the reconstructed version of the analog input signal. The coarse quantization can have errors which are attributed to comparator offsets and bandwidth mismatch. To estimate the comparator offsets while being insensitive to bandwidth mismatch, peak and trough detectors are used to track maximum and minimum values of the residue or the output of the ADC over time, and an expected value estimating the comparator offset can be computed based on the maximum and minimum values. The expected value advantageously “averages” out the bandwidth mismatch contribution to the offset.

Abstract: Various aspects facilitate gain adjustment associated with an analog to digital converter. A capacitor array comprises a plurality binary-weighted capacitors and generates an output voltage received by a comparator based on an input voltage and a reference voltage. A gain calibration component receives the input voltage and applies a modified input voltage that corresponds to a portion of the input voltage to the output voltage generated by the capacitor array component.

Abstract: Provided are a ramp signal calibration apparatus and method and image sensor including the apparatus. The apparatus includes: an analog-to-digital converter (ADC) including a trimmable transistor having a gain value that varies according to stored data, and configured to receive a ramp signal in a state where the gain value is a first gain value, and to output first and second output signals; a subtractor configured to calculate a difference between the first and second output signals; a digital comparator configured to compare the difference with a reference value and to determine whether a slope of the ramp signal has changed; and a counter configured to change the stored data based on whether the slope of the ramp signal has changed, wherein when the counter changes the data, the first gain value of the trimmable transistor is changed to a second gain value according to the changed data.

Abstract: The integral type Analog/Digital (AD) converter includes: a comparator configured to compare a reference voltage of a ramp waveform with an input voltage and output a comparison signal; a DLL circuit configured to generate a plurality of clock signals; a delay adjustment circuit configured to delay the comparison signal; a counter configured to count a time from starting of changing of the ramp waveform to the inversion of the outputting from the delay adjustment circuit and output the counted result as a high-order bit; and a TDC configured to latch and decode the plurality of clock signals when the output of the delay adjustment circuit is inverted and output the latched and decoded result as a low-order bit, wherein the TDC starts an operation thereof by the inversion of the comparison signal, and stops the operation thereof by the inversion of the output signal of the delay adjustment circuit.

Abstract: Embodiments described herein provide for a method of modulating an input light beam of an interferometric fiber optic gyroscope (IFOG). The method includes intermittently jumping a phase step to suppress dead band. During a first cycle, a first cycle raw rate is stored and a feedback signal is generated based on a jumped phase step. During a second cycle, a second cycle raw rate is stored and a feedback signal is generated based on the jumped phase step. During a third cycle, a third cycle phase step is generated by accumulating the first cycle raw rate with a second cycle phase step, and a feedback signal is generated from the third cycle phase step. During a fourth cycle, a fourth cycle phase step is generated by accumulating the second cycle raw rate with the third cycle phase step, and a feedback signal is generated from the fourth cycle phase step.

Abstract: Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier.

Abstract: Embodiments described herein provide for a method of modulating an input light beam of an interferometric fiber optic gyroscope (IFOG). The method includes intermittently jumping a phase step to suppress dead band. If a bit flip was clocked into a digital to analog converter generating the feedback signal at the beginning of a cycle in which the jumped phase step is implemented, the method includes at least one of re-introducing a rate difference corresponding to the bit flip, altering the timing of the bit flip, or altering the timing of the generating a feedback signal based on the jumped phase step.

Abstract: The present invention is directed integrated circuits and methods thereof. More specifically, an embodiment of the present invention provides a comparator calibration loop where a digital integrator stores a running sum based on the output of a comparator. A DAC converts the running sum and generates an offset calibration voltage, which is filtered by a low-pass filter module, and the filtered offset calibration voltage is used to cancel out the intrinsic offset voltage and low frequency noise of the comparator. There are other embodiments as well.

Abstract: Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Abstract: A multi-lane analog to digital converter (ADC) samples an analog input according to multiple phases of a sampling clock. Ideally, the multiple phases of the sampling clock are non-overlapping. The multi-lane ADC includes one or more reset switches to remove any residual samples that can remain after their conversion from an analog signal domain to a digital signal domain. As a result of this removal, the multiple phases of the sampling clock need not to ideally coincide with one other. Rather, some overlap between the multiple phases of the sampling clock can exist while having digital output samples still accurately represent the analog input.

Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

Abstract: A data processing system having an analog-to-digital converter (ADC) and method for testing the ADC are provided. The data processing system also comprises a digital-to-analog converter (DAC) and test logic. The DAC has a first voltage range, an input for receiving a test code, and an output. The ADC has a second voltage range larger than the first voltage range, an input coupled to the output of the DAC, and an output for providing a series of output codes over the second voltage range. The test logic is coupled to the ADC and is for controlling testing of the ADC using the DAC. A plurality of series of test codes are provided to the DAC for testing portions of the second voltage range output from the ADC. A beginning series of test codes is for testing a beginning portion of the second voltage range and subsequent series of test codes are for testing subsequent portions of the second voltage range.

Abstract: An analog-to-digital converting device includes a converting module, for sampling an analog input voltage according to a plurality of sampling signals to generate a comparing voltage and generating a comparing signal according to the comparing voltage, wherein the converting module comprises a plurality of capacitors and each of the plurality of capacitors couples between one of the plurality sampling signals and the comparing voltage; a control module, for adjusting the plurality of sampling signals according to the comparing signal, to generate a digital signal corresponding to the analog input voltage, wherein a plurality of bits of the digital signal are respectively corresponding to the capacitances of the plurality of capacitors; and a calibration module, for adjusting the capacitances of the plurality of capacitors according to the digital signal.

Abstract: A linear reference analog to digital converter (ADC) network may include a first ADC operatively connected to a first sample and hold circuit. The linear reference ADC network may be configured to receive an input signal from the first sample and hold circuit and sample the input signal with a harmonic distortion. The linear reference ADC network may further include a reference ADC operatively connected to a second sample and hold circuit and configured to receive the input signal and sample the input signal with a second harmonic distortion. The linear reference ADC network may further include a combining module operatively connected to the first ADC and the reference ADC, the combining module configured to equalize a linearity of an output of the first ADC to a linearity of an output of the reference ADC, and output a combined output signal, and a circuit configured to output a calibrated output signal having calibrated harmonic distortion content.

Abstract: A feedback circuit provides a feedback signal to a transducer. The feedback circuit includes an ADC that generates digital representations of a feedback signal, digital controller that identifies adjustments for the feedback, and DAC that generates an analog output of the adjusted feedback signal. The digital controller performs speculative computation to identify adjustments for the feedback signal output for each output value from the ADC prior to receiving the output from the ADC. The ADC and DAC include sigma-delta modulators that operate with a zero clock cycle delay in a forward path. The ADC, digital controller, and DAC generate adjustments to the feedback output signal with reduced delay that reduce phase lag and improve phase margin to maintain stability in the transducer.

Abstract: A high-speed sampling front-end circuit is presented that includes a MDAC sampling network, a reference voltage generator circuit, a comparator array, an operational amplifier, an output short-circuit switch, an adjustable clock duty cycle stabilizer, a status control module and a feedback control module. The circuit features low power, high sampling rate and high input bandwidth of sampling network. The time constant of the MDAC sampling network and the comparator array is precisely matched one another to improve input bandwidth of the sampling network. Sampling capacitors are designed as feedback capacitors and DAC calculation capacitors, thereby the operational amplifier doubles feedback coefficient and features 50% bandwidth and 50% power. The cycle stabilizer is adopted to shorten sampling time and extend amplification phase to greatly improve sampling rate. One input reference voltage tends to simplify the design of the reference voltage generator circuit.

Abstract: Systems and methods described herein enable a residual error image to be added and rendered in an existing HTML canvas using native primitives. A current image and a residual error image containing pixel value differences between the current image and an updated image are received. A positive residual error image and a negative error image are generated from the residual error image. The positive residual error image is added to the current image to generate a partially updated image, and the partially updated image is xored to generate an inverse image. The negative residual error image is added to the inverse image to generate an updated inverse image, and xoring the inverse image to revert the inverse image to generate the updated image.

Abstract: An amplifier system includes a low offset amplifier having a first signal input, a second signal input, an output, a resistive digital to analog converter (RDAC) coupled between a first amplifying terminal and a second amplifying terminal of the amplifier that provides offset control, and a current supply coupled to the RDAC. The amplifier system further includes a low offset amplifier having a first signal input, a second signal input, an output, a resistive digital to analog converter coupled between a first amplifying terminal and a second amplifying terminal of the amplifier that provides offset control, and a current supply coupled to the RDAC. The amplifier system also further includes a load coupled to the output and to the second input of the amplifier and a controller coupled to the RDAC that provides an offset control of the first and second inputs by controlling the RDAC.

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract: A circuit calibrating method, applied to an ACS generating circuit, which comprises a plurality of ACS generating units and activates the ACS generating unit corresponding to different DCCs to generate difference ACSs. The circuit calibrating method comprises: (a) determining which one of the ACSs has a large difference from an ideal value thereof; (b) adjusting a number of the ACS generating units, which are activated by a DCC corresponding to the ACS acquired in the step (a), or a next stage of the DCC corresponding to the ACS acquired in the step (a); and (c) generating the ACS to a target circuit, according to the number of the ACS generating circuits adjusted in the step (b).

Abstract: An apparatus may include a scrambler element configured to receive an input signal and generate a scrambled thermometer code-like signal having a plurality of bits based on the input signal and having a plurality of possible quantization values. The scrambler element may generate at least one equivalent code of the scrambled thermometer code-like signal for each possible quantization value. For each of one or more of the possible quantization values, the scrambler element may be configured to generate a plurality of possible equivalent codes of the scrambled thermometer code-like signal. Responsive to the input signal indicating a change in quantization value of the scrambled thermometer code-like signal, the scrambler element may change the scrambled thermometer code-like signal by transitioning the smallest possible number of the plurality of bits of the scrambled thermometer code-like signal to change quantization value of the scrambled thermometer code-like signal in accordance with the input signal.

Abstract: Devices, circuitry, and methods for improving matching between semiconductor circuits are shown and described. Measuring a difference in matching between semiconductor circuits may be performed with a test current generator and test current measurement circuit, and adjusting a threshold voltage of a semiconductor component of at least one circuit until the difference between the circuits is at a desired difference may be performed with a program circuit.

Abstract: A robust and fast background calibration technique for correction of time-interleaved ADC offset, gain, bandwidth, and timing mismatches is proposed. The technique combines the use of a calibration signal and a reference ADC. The calibration signal enhances robustness and makes the technique independent of the input signal's statistics. The reference ADC speeds up convergence and enables the use of a small amplitude calibration signal that does not significantly reduce the input signal dynamic range. The calibration signal can be subtracted or filtered from the ADC output and is therefore invisible to the ADC user.

Abstract: The test signal generator generates an analog and digital test signals to test a sigma-delta ADC which has an analog portion succeeded by a digital decimation filter. The test signal generator supplies a first digital test signal having a first particular number of bits N and a first particular bit rate RN corresponding to digital signals occurring after the digital decimation filter. A digital sigma-delta modulator converts the first digital test signal into a second digital test signal having a second particular number of bits M<N thereby corresponding to a digital signal occurring at an input of the digital decimation filter. A DAC converts the second digital test signal into an analog signal, and a filter to filter the analog signal to obtain an analog test signal for testing the analog portion.

Abstract: A delta-sigma modulation analog-to-digital converter (ADC) may be constructed by combining a VCO used for a first order filter with a digital loop filter used for a second or higher order of the ADC. One such ADC would include an analog input node configured to receive an analog signal; a voltage-controlled oscillator (VCO) comprising a first input configured to receive the analog signal, wherein the voltage-controlled oscillator is configured to implement a first order noise-shaping function; a digital loop filter comprising a second input configured to receive an output of the voltage-controlled oscillator (VCO); and a digital output node configured to output a digital signal based on an output of the digital loop filter. The digital loop filter may be configured to implement at least a first order noise-shaping function, but may also implement higher order noise-shaping functions.

Abstract: A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Abstract: A method comprises sampling an input voltage signal, comparing the sampled input voltage signal with an output signal of a feedback DAC, and determining an (N+1) bit code representation for a comparison result, the (N+1) bit code yielding the N bit output signal. On detection of the (N+1) bit code being equal to a predefined calibration trigger code, performing a calibration for a most significant bit of the (N+1) bit code by replacing the (N+1) bit code by an alternative (N+1) bit code that yields the same N bit output signal, performing an additional comparison cycle using the alternative (N+1) bit code, determining, using comparison results of the additional comparison cycle and the preceding (N+1)th cycle, a sign of a DAC capacitor mismatch error, and tuning programmable binary scaled calibration capacitors in parallel to a capacitor corresponding to the one of the most significant bits of the (N+1) bit code.

Abstract: An analog/digital converter system includes a multiplexer, which includes multiple channels having at least one switch, and an analog/digital converter, the analog input of which is connected to the output portal of the multiplexer. Also described is a method for checking a multiplexer for an analog/digital converter. At least one other switch for testing the multiplexer is provided in at least one channel, this other switch connecting the input portal and/or the output portal of the corresponding channel and/or the corresponding channel to a predefined voltage potential.

Abstract: The present invention provides a method for auto-calibration of ADC, comprising acquiring a voltage signal value of a reference voltage source; converting the voltage signal value of the reference voltage source to a digital signal value according to a preset conversion coefficient value; and comparing the digital signal value to a target value and adjusting the conversion coefficient value according to the comparing result so that the difference between the digital signal value and the target value is within an allowed margin of error. The procedure of the method for auto-calibration of ADC of the present invention is executed automatically, no professional operator is needed to calibrate manually. As such, labor cost is reduced and work efficiency is improved.

Abstract: A system includes an interleaved analog-to-digital converter (ADC) comprising a plurality of sub-ADCs, where each of the plurality of sub-ADCs has an adjustable timing. The system includes a data analyzer that analyzes an output of the interleaved ADC, that estimates timing mismatches of the plurality of sub-ADCs, and that corrects the timing mismatches by adjusting the adjustable timing of one or more of the plurality of sub-ADCs based on the estimated timing mismatches.

Abstract: A digital-to-analog converter has an output. An analog-to-digital converter senses a voltage at the output of the digital-to-analog converter and generates a digital voltage signal. A source mismatch estimator processes the digital voltage signal to output an error signal indicative of current source mismatch within the digital-to-analog converter. An error code generator generates a digital calibration signal from the error signal. The digital calibration signal is converted by a redundancy digital-to-analog converter to an analog compensation signal for application to the output of analog-to-digital converter to nullify effects of the current source mismatch.

Abstract: Logic for direct current (DC) estimation of a wireless communication packet. Logic may determine a first DC estimation based upon a first set of sequences in a preamble of the wireless communication packet. Logic may determine a second DC estimation based upon a second set of sequences in the preamble. Logic may select one of the DC estimations based upon a frequency-offset estimation. Logic may remove one of the DC estimations from the packet. Logic to null DC bins that result from a Fourier transform of the packet to mitigate transmitter DC bias. And logic to determine a correction for the packet based upon a difference between a predetermined guard interval value and a received guard interval value and to apply the correction to the packet.