Converter Calibration Or Testing Patents (Class 341/120)
  • Patent number: 11444632
    Abstract: A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 13, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Sujata Sen, Mattia Oddicini, Luca Petruzzi, Benjamim Tang
  • Patent number: 11429226
    Abstract: A drive sense circuit comprises an analog front-end and a digital back end. The analog front-end generates an analog drive sense signal based on an analog reference signal that includes a varying component. The varying component has a magnitude that is substantially less than a supply rail power of the drive sense circuit. When the drive sense circuit is coupled to a load, the analog front end drives the load with the analog drive-sense signal and detects an analog signal variation in the analog drive-sense signal based on a characteristic of the load. The digital back-end converts the analog signal variation into a digital sensed value corresponding to the characteristic of the load.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: August 30, 2022
    Assignee: SIGMASENSE, LLC.
    Inventors: Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand, Richard Stuart Seger, Jr.
  • Patent number: 11424752
    Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 23, 2022
    Assignee: AyDeeKay LLC
    Inventors: Christopher A. Menkus, Robert W. Kim
  • Patent number: 11424757
    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) with calibration function and a calibration method thereof are provided. The SAR ADC has at least one capacitor digital-to-analog converter (CDAC), having Nd capacitors corresponding to Nd bits; and a controller. The calibration method includes: coupling the capacitors of an i-th to an (Nd?1)-th bit to a first reference voltage, and generating a first digital code based an operation of the capacitors of an (i?1)-th bit to a 0-th bit; coupling the capacitors of an (i+1)-th bit to the (Nd?1)-th bit to the first reference voltage, coupling the capacitor of the i-th bit to a second reference voltage, and generating a second digital code based on the operation of the capacitors of the (i?1)-th bit to the 0-th bit; generating a capacitor weight of the capacitor of the i-th bit; and calibrating the SAR ADC based on the capacitor weight.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: August 23, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Hui Chung, Qi-Feng Zeng
  • Patent number: 11418206
    Abstract: A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 16, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Shih-Hsiung Huang, Ying-Cheng Wu, Chien-Ming Wu, Kai-Yin Liu
  • Patent number: 11405571
    Abstract: Changing the analog gain for each of columns while suppressing an expansion of area and an increase in power consumption. A solid-state imaging apparatus (1, 1A) according to an embodiment includes: converters (10A to 10D) connected to a vertical signal line (VSL) extending from a pixel array unit (30); a voltage generator (20) that is connected to a plurality of voltage lines and outputs reference voltages having mutually different voltage values individually to the plurality of voltage lines; wiring lines (L10 to L31, L20 to L23) connecting the converter and the plurality of voltage lines; and switches (SW0 to SW3) provided on the wiring line and configured to perform changeover of the voltage lines connected to the converter to one of the plurality of voltage lines.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: August 2, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yusuke Ikeda
  • Patent number: 11394392
    Abstract: A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: July 19, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Shih-Hsiung Huang
  • Patent number: 11387836
    Abstract: A method has been disclosed that relates to electrical variability compensation technique for configurable-output circuits. The compensation technique can be applied to a generality of circuits whose output has to vary between two electrical limits spanning the range in between them according to a specific code given as input. A switching sequence that is process gradient-direction agnostic has been disclosed which limits variability. An electric device comprising a processing gradient-direction agnostic configurable-output circuit has been also disclosed.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Pierguido Garofalo
  • Patent number: 11368165
    Abstract: A converter circuit includes an analog-to-digital signal conversion path. An input port receives an analog input signal having an offset, and an output port delivers a digital output signal quantized over M levels. The digital output signal is sensed by a digital-to-analog feedback path, which includes a digital-to-analog converter applying to the input port an analog feedback signal produced as a function of an M-bit digital word under control of a two-state signal having alternating first and second states. M-bit digital word generation circuitry coupled to the digital-to-analog converter and sensitive to the two-state signal produces, alternately, during the first states, a first M-bit digital word, which is a function of the digital output signal quantized over M levels, and, during the second states, a second M-bit digital word, which is a function a correction value of the offset in the analog input signal.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: June 21, 2022
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Calogero Marco Ippolito, Michele Vaiana
  • Patent number: 11356111
    Abstract: A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes an input port, a non-binary DAC, an ADC to receive an output of the non-binary DAC, a lookup table to store a plurality of calibration code and a calibration logic coupled with the non-binary DAC. The self-calibrating DAC has two modes of operations, a calibration mode and a normal operational mode. In the calibration mode, the self-calibrating DAC is configured to calculate weightages of the non-binary DAC and to calculate an offset coefficient and a gain coefficients using high precision on chip analog-to-digital converter (ADC).
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 7, 2022
    Assignee: NXP B.V.
    Inventors: Hanging Xing, Ronak Prakashchandra Trivedi, Jean CauXuan Le
  • Patent number: 11353506
    Abstract: A safety circuit for the multi-channel processing of an input signal. The safety circuit includes an analog-to-digital conversion device having a first analog input and a second analog input and at least one digital output for processing the input signal. Furthermore, the safety circuit has a test device which is set up to apply a test signal at the first and/or second input of the A/D conversion device in such a way that the test signal superposes the input signal such that the test signal dominates the input signal.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 7, 2022
    Assignee: WAGO Verwaltungsgesellschaft mit beschraenkter Haftung
    Inventors: Alexander Buelow, Christian Voss, Torsten Meyer
  • Patent number: 11323127
    Abstract: A digital-to-analog conversion circuit, a digital-to-analog conversion method, and a display device are provided. The digital-to-analog conversion circuit includes a first digital-to-analog conversion sub-circuit and a second digital-to-analog conversion sub-circuit. The second digital-to-analog conversion sub-circuit includes least-significant-bit voltage selection modules whose quantity is a, a weighed summation operational amplifier, switching control modules whose quantity is a and energy storage modules whose quantity is a. The weighted summation operational amplifier includes a reverse-phase input end, an operational amplification output end, and same-phase input ends whose quantity is a. The reverse-phase input end is connected to the operational amplification output end, and a is an integer greater than 1.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 3, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tangxiang Wang, Chen Song
  • Patent number: 11316525
    Abstract: An analog-to-digital converter system includes a digital-to-analog converter for generating calibration voltages based on digital input codes, and an analog-to-digital converter, connected to the digital-to-analog converter, for receiving the calibration voltages from the digital-to-analog converter, for receiving sampled voltages, for generating digital output codes based on the calibration voltages, and for generating digital output codes based on the sampled voltages. The analog-to-digital converter system may have a lookup table, connected to the analog-to-digital converter, for storing the first digital output codes in association with the digital input codes. A method of calibrating an analog-to-digital converter system is also disclosed.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Visvesvaraya Appala Pentakota, Narasimhan Rajagopal, Chirag Chandrahas Shetty, Prasanth K, Neeraj Shrivastava, Eeshan Miglani, Jagannathan Venkataraman
  • Patent number: 11293781
    Abstract: An encoder according to an example of the present disclosure includes a first reception unit configured to receive a position information request signal for requesting position information on an object to be detected, a position information generation unit configured to generate the position information at a position information generation timing after a predetermined delay time elapses from when the position information request signal is received, and a first transmission unit configured to transmit the position information to the outside via serial communication. The first transmission unit is configured to transmit, at least once, position information generation timing information representing the predetermined delay time to the outside via serial communication.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 5, 2022
    Assignee: Fanuc Corporation
    Inventor: Shinichirou Hayashi
  • Patent number: 11287352
    Abstract: A method for determining the position of an irregularity in an optical transmission fiber using an optical time domain reflectometer, the method comprising the steps of emitting a succession of sampling light pulses into the optical transmission fiber, detecting reflected light pulses resulting from the reflection of the sampling light pulses at the irregularity in the optical transmission fiber and generating corresponding time-dependent detection signals, wherein different delays are associated with detection signals corresponding to different sampling light pulses, obtaining a combined signal from the detection signals, and analyzing the combined signal for determining the position of the irregularity in the optical transmission fiber with respect to the optical time domain reflectometer, wherein the combined signal corresponds to a superposition of the detection signals.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 29, 2022
    Assignee: XIEON NETWORKS S.a.r.l.
    Inventors: Lutz Rapp, Nuno Renato Duarte Pereira
  • Patent number: 11287471
    Abstract: An electronic circuit for online monitoring a clock signal is provided. The electronic circuit includes a period-to-pulse converter, a pulse-shrinking block and an encoder. The period-to-pulse converter receives the clock signal outputted by a phase-locked loop, and converts each of a plurality of clock period samples of the clock signal to generate a pulse-train signal having a plurality of pulses. The pulse-shrinking block receives the plurality of pulses of the pulse-train signal, and generates a plurality of catch bits by shrinking the plurality of pulses of the pulse-train signal. The encoder outputs a minimum code denoting a minimum clock period of the clock signal and a maximum code denoting a maximum clock period of the clock signal according to the plurality of catch bits. The electronic circuit subtracts the maximum code and the minimum code to generate a peak-to-peak jitter amount code.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 29, 2022
    Assignee: National Tsing Hua University
    Inventors: Shi-Yu Huang, Wei-Hao Chen, Chu-Chun Hsu
  • Patent number: 11287460
    Abstract: Various embodiments of the present technology may provide methods and apparatus for managing a battery system. The apparatus may provide a power line to connect a battery to a signal converter and a fuel gauge circuit to measure a voltage of the power line, detect noise on the power line, and control operation of a sensor and/or the fuel gauge circuit in response to the detected noise.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 29, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Hideo Kondo
  • Patent number: 11277146
    Abstract: An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventors: Christian Lindholm, Hundo Shin, Martin Clara
  • Patent number: 11271577
    Abstract: An ADC circuit is provided. The ADC circuit may include an array of bit capacitors; a comparator electrically connected to the bit capacitors; a NOR gate electrically connected to the comparator; an AND gate to create an asynchronous clock (ACLK) based on a digital output from the NOR and a synchronous clock (CLKin); a delay control circuit to receive the asynchronous clock and to create a delayed asynchronous clock (ACLKd); and a SAR control circuit to receive a digital output from an output end of the comparator, to receive the delayed asynchronous clock, to transmit a bit control signal (B<9:1>) to the bit capacitors, and to transmit a delay control word (DL<7:1>) to the delay control circuit. The ADC circuit can create an asynchronous comparator clock (CKcmp) with a maximum delay value (Td_max), thus leading to an improved conversion linearity and a reduced power consumption.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: March 8, 2022
    Assignee: Beken Corporation
    Inventors: Desheng Hu, Jiazhou Liu, Cunpeng Zhang
  • Patent number: 11271581
    Abstract: Method and apparatus for sharing an analog signal for use by a plurality of devices are disclosed. In some implementations, the analog signal may be generated by a controller. The controller also may generate a control signal to determine when other devices use the analog signal. In one implementation, the control signal may be a token that may be transmitted and received by the other devices. If a device possess the token, then the device may use the analog signal. If the device does not possess the token, then the device may not use the analog signal. In another implementation, the controller may transmit a peer-to-peer message to a selected device. When the selected device receives the peer-to-peer message, then the selected device may use the analog signal. In this manner, the controller ensures that only one device at a time may use the analog signal.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 8, 2022
    Assignee: Xilinx, Inc.
    Inventors: John K. Jennings, John O'Dwyer
  • Patent number: 11265002
    Abstract: A method includes converting, by n analog to digital converter circuits, n analog signals into n first digital signals having a first data rate frequency; converting, by n digital decimation filtering circuits, the n first digital signals into n second digital signals having a second data rate frequency; and converting, by n digital bandpass filter (BPF) circuits, the n second digital signals into a plurality of outbound digital signals having a third data rate frequency. The coefficients for the taps of a digital BPF circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone component of the analog signal. The first data rate frequency is a first integer multiple of the third data rate frequency. The second data rate frequency is a second integer multiple of the third data rate frequency.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: March 1, 2022
    Assignee: SIGMASENSE, LLC.
    Inventors: Grant Howard McGibney, Patrick Troy Gray, Gerald Dale Morrison, Daniel Keith Van Ostrand
  • Patent number: 11265007
    Abstract: Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 1, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Peter Kurahashi, Dacheng Zhou, Michael James Marshall
  • Patent number: 11258454
    Abstract: An embodiment target time comparison circuit corresponding to a target approximate voltage range among 2K time comparison circuits in a second comparison circuit compares a comparison operation time difference included in voltage comparison results regarding two adjacent approximate voltage ranges that are vertically adjacent to the target approximate voltage range with 2L reference times corresponding to 2L specific voltage ranges and generates a target binary code of L bits indicating a target specific voltage range including the held voltage from the obtained time comparison results.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Il-Min Yi, Naoki Miura, Hiroyuki Fukuyama, Hideyuki Nosaka
  • Patent number: 11251786
    Abstract: A supply-to-digital regulation loop (SDRL) circuit, including a reference supply circuit and a local supply circuit. The reference supply circuit includes a reference supply-to-digital converter (SDC) to convert an analog reference supply voltage to a digital reference signal. The local supply circuit is coupled to the reference supply circuit. The local supply circuit includes a local SDC to convert an analog local supply voltage to a digital local supply signal based on a digital feedback signal, and a local monitoring circuit to monitor the digital feedback signal based on a comparison of the digital local supply signal with the digital reference signal routed from the reference SDC of the reference supply circuit.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Stefano Bonomi, Frank Praemassing
  • Patent number: 11245411
    Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: February 8, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsuan-Ting Ho, Chi-Shun Weng, Liang-Wei Huang
  • Patent number: 11243120
    Abstract: A temperature sensor, a processor including the same, and a method of operating the same are provided. The temperature sensor includes: a reference circuit configured to receive a supply voltage provided from outside the processor and utilized by a logic block of the processor for operation of the logic block, and generate, using the supply voltage, at least one temperature information signal that varies according to a temperature of the logic block and at least one reference signal that is substantially constant relative to the temperature of the logic block; and a digital temperature generator configured to receive the at least one temperature information signal and the at least one reference signal generated by the reference circuit, and generate a digital temperature information signal indicative of the temperature of the logic block based on the at least one temperature information signal and the at least one reference signal.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 8, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hyun Cho, Hyung Jong Ko, Kyung Soo Park, Seoung Jae Yoo, Sang Ho Kim, Ho Jin Park
  • Patent number: 11239833
    Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sriram Murali, Jaiganesh Balakrishnan, Ram Narayan Krishna Nama Mony, Pooja Sundar
  • Patent number: 11228368
    Abstract: An optical communications network comprises optical data links comprising data channels. A time-domain sampled waveform of a selected data channel is obtained. The Fourier transform is applied to the time-domain sampled waveform of the selected data channel to generate a frequency-domain waveform of the selected data channel. Time-domain sampled waveforms of the selected data channel's neighboring data channels are obtained. The Fourier transform is applied to the time-domain sampled waveforms of the neighboring data channels to generate frequency-domain waveforms of the neighboring data channels. The noise-to-signal ratio is calculated based on the frequency-domain waveforms. Based on the calculated noise-to-signal ratio, an optical signal to noise ratio (OSNR) penalty is estimated. A notification is generated when the OSNR penalty exceeds a predetermined threshold.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 18, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yawei Yin, Binbin Guan
  • Patent number: 11218158
    Abstract: In one aspect, a transfer function (TF) estimation circuit configured to generate an estimate of a TF undergone by signals between an input of a digital-to-analog converter (DAC) of a feedforward path of a continuous-time (CT) stage of an analog-to-digital converter (ADC) and an output of a backend ADC of the ADC is disclosed. The TF estimation circuit includes one or more circuits configured to generate a first cross-correlation output by cross-correlating digital versions of signals based on a test signal provided to the CT stage and an output signal of the backend ADC, generate a second cross-correlation output by cross-correlating digital versions of signals based on the test signal and an output signal of a quantizer of the feedforward path of the CT stage, and generate the estimate of the TF based on the first and second cross-correlation outputs.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 4, 2022
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Sharvil Pradeep Patil, Donald W. Paterson, Prawal Man Shrestha, Asha Ganesan, Yue Yin, Zhao Li, Victor Kozlov, Hajime Shibata
  • Patent number: 11206035
    Abstract: An analog to digital (A/D) converter includes a capacitor array having respective first terminals selectively coupled to a reference voltage or ground via a plurality of switches and having respective second terminals coupled to a sample and hold (S/H) output. The A/D converter also includes a voltage comparator having a first input coupled to the S/H output and having a second input coupled to a bias voltage. The voltage comparator is configured to output a comparison voltage responsive to a sampled charge at the S/H output and the bias voltage. The A/D converter also includes a successive approximation register coupled to receive the comparison voltage and configured to output an approximate digital code responsive to the comparison voltage, wherein the approximate digital code is varied by controlling an equivalent capacitance of the capacitor array.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Vijay Kulkarni, Shridhar More, Amal Kumar Kundu, Minkle Eldho Paul
  • Patent number: 11196437
    Abstract: In accordance with an embodiment, a method for operating an analog-to-digital converter (ADC) includes: determining a trip point of a comparator of the ADC by applying a first signal having a first slope to an input of the ADC, and monitoring an output state of the comparator in response to the first signal; and after applying the first signal, applying a second signal having a second signal level based on the determined trip point of the comparator, monitoring values of an output code of the ADC in response to the second signal, and generating statistical information based on the monitored values of the output code, where the second signal is a static signal or has as second slope less than the first slope.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 7, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Dieter Draxelmayr
  • Patent number: 11184019
    Abstract: An analog-to-digital converter (ADC) with split-gate laddered-inverter quantizer is presented herein. The ADC converts, via the split-gate laddered-inverter quantizer, an analog input voltage into a digital output value. The split-gate laddered-inverter quantizer separately couples, during respective phases of a clock signal via respective capacitances, a reference voltage and an input voltage corresponding to the analog input voltage to P-type metal-oxide-semiconductor (PMOS) gates of a PMOS branch of the split-gate laddered-inverter quantizer and N-type metal-oxide-semiconductor (NMOS) gates of an NMOS branch of the split-gate laddered-inverter quantizer to optimize current flow at respective frequencies. Further, the split-gate laddered-inverter quantizer separately biases, during the respective phases of the clock signal, the NMOS gates and the PMOS gates at respective bias voltages to optimize the current flow at the respective frequencies.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 23, 2021
    Assignee: INVENSENSE, INC.
    Inventor: Dusan Vecera
  • Patent number: 11163347
    Abstract: A method of transferring power and data between a first circuit and a second circuit is described, whereby the second circuit comprises a processing unit having an I/O terminal and an electric energy storage element, the electric energy storage element being configured to be charged by the first circuit via the I/O terminal and configured to power the processing unit, the method comprising: establishing a wired communication link between an I/O terminal of the first circuit and the I/O terminal of the second circuit; operating the I/O terminal of the second circuit as an output terminal and the I/O terminal of the first circuit as an input terminal; transmitting data via the I/O terminal of the second circuit to the I/O terminal of the first circuit by modulating an output level of the I/O terminal of the second circuit between a high level and a low level; determining whether the output level of the I/O terminal of the second circuit corresponds to the high level or the low level and, when the output leve
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 2, 2021
    Assignee: eldoLAB Holding B.V.
    Inventor: Marc Saes
  • Patent number: 11146250
    Abstract: The present application discloses a pulse voltage generation device, method and controller, the device comprises: a transformer; a first AC/DC conversion circuit, with an alternating current side connected with a high-voltage side of the transformer; an energy storage capacitor, connected with a direct current side of the a first AC/DC conversion circuit, for storing electrical energy; and a discharge control circuit, in parallel connection with both ends of the energy storage capacitor, for controlling discharge of the energy storage capacitor to generate a high-voltage pulse.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 12, 2021
    Assignee: Suzhou Powersite Electric Co., Ltd.
    Inventors: Shengfang Fan, Qiang Huang, Fei Chen, Xiaosen Chen, Jie He
  • Patent number: 11139826
    Abstract: A DAC error measurement apparatus includes: an ADC and a feedback DAC, where a measurement input of the ADC includes a square wave signal with a constant frequency, a direct-current signal at a constant logical level, and an analog output of the feedback DAC; a measurement selection module, configured to provide a measured digit in a digital output to a separately selected source cell, and provide remaining digits in the digital output to remaining source cells, where the measured digit is a flippable digit, and the remaining digits are non-flipping digits; and a measurement module, configured to measure an amplitude of the digital output based on the digital output. One flipping digit in the digital output is the measured digit, and the remaining digits are the non-flipping digits, such that the measurement selection module may separately select one source cell to receive the measured digit.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: October 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Haixi Li
  • Patent number: 11133817
    Abstract: A processing system with a microarchitectural feature for mitigation of differential power analysis and electromagnetic analysis attacks can include a memory, a processor, and a mitigation response unit. The processor can include an instruction predictor that comprises a storage device for storing metadata associated with corresponding instruction blocks. The mitigation response unit is coupled to the instruction predictor to write and read the metadata associated with the corresponding instruction blocks. The mitigation response unit is configured to determine a mitigation technique for an instruction block based on an electromagnetic or power signature corresponding to execution of the instruction block and metadata associated with the instruction block.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 28, 2021
    Assignee: ARM LIMITED
    Inventors: Matthias Lothar Boettcher, Hugo John Martin Vincent, Brendan James Moran
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11128309
    Abstract: A digital calibration method, a device, and a true random number generator circuit are provided. In one aspect, the embodiment of the present disclosure uses the digital calibration method to calibrate compensation of a circuit to be calibrated, output of the circuit to be calibrated is sampled and tested multiple times, and whether a current test compensation calibration code value can make the circuit to be calibrated meet specified accuracy is judged based on a probability that the output result is a target result. Through sampling the output of the circuit to be calibrated multiple times, the selected compensation calibration code has higher accuracy.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 21, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Yuan Su, Xiang Fang, Zheng Li
  • Patent number: 11122259
    Abstract: A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 14, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Zhiyong Zhan, Tongtong Yu, Xin Wang, Liang Zuo, Kenny Geng
  • Patent number: 11112811
    Abstract: Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 7, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Eric Hunt-Schroeder, Alexander J. Filmer
  • Patent number: 11109017
    Abstract: An imaging system may include two or more pipeline processing circuits that receive image data streams from two or more corresponding image sensors and process the received image data in parallel in an image signal processing mode of operation. The imaging system may include fault detection circuitry coupled to the two or more pipeline processing circuits. The fault detection circuitry may configure the two or more pipeline processing circuits with fault detection configuration states and generate injection data for processing by the two or more pipeline processing circuits in a fault detection mode of operation. Fault detection may be enabled dynamically based on a horizontal and vertical sync circuit and during an image processing pause period between image frames. The imaging system having the fault detection circuitry may be configured to efficiently perform fault detection without interrupting image signal processing.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 31, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Dannie Gerrit Feekes
  • Patent number: 11070222
    Abstract: Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 20, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Mattias Palm, Lars Sundström, Ola Andersson
  • Patent number: 11070219
    Abstract: A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Munehiko Nagatani, Hideyuki Nosaka
  • Patent number: 11057047
    Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Vincent Quiquempoix, Zeynep Sueda Turk
  • Patent number: 11057048
    Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Vincent Quiquempoix
  • Patent number: 11038517
    Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 15, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajavelu Thinakaran
  • Patent number: 11012084
    Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 18, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Obaida Mohammed Khaled Abu Hilal
  • Patent number: 11005495
    Abstract: The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 11, 2021
    Assignee: SENSEEKER ENGINEERING, INC.
    Inventors: Kenton Veeder, Nishant Dhawan, Sean McCotter
  • Patent number: 10972129
    Abstract: A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jun Heo, Sung Sik Yoon, Byung Kyu Ahn
  • Patent number: 10951221
    Abstract: In some examples, a device includes an analog-to-digital converter (ADC) configured to receive an analog signal and output digital codes based on values of the analog signal. The device also includes a plurality of counters, where each counter of the plurality of counters is configured to increment in response to a respective digital code outputted by the ADC.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: March 16, 2021
    Assignee: Regents of the University of Minnesota
    Inventors: Gyusung Park, Hyung-il Kim