Converter Calibration Or Testing Patents (Class 341/120)
  • Patent number: 11125628
    Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Takeuchi, Shinya Konishi, Fumio Tsuchiya, Masaki Shimada
  • Patent number: 11128309
    Abstract: A digital calibration method, a device, and a true random number generator circuit are provided. In one aspect, the embodiment of the present disclosure uses the digital calibration method to calibrate compensation of a circuit to be calibrated, output of the circuit to be calibrated is sampled and tested multiple times, and whether a current test compensation calibration code value can make the circuit to be calibrated meet specified accuracy is judged based on a probability that the output result is a target result. Through sampling the output of the circuit to be calibrated multiple times, the selected compensation calibration code has higher accuracy.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 21, 2021
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventors: Yuan Su, Xiang Fang, Zheng Li
  • Patent number: 11122259
    Abstract: A test voltage sample and hold circuitry is disclosed in a readout circuitry of an image sensor. This circuitry samples a voltage at demand value based on a ramp voltage shared by the ADC comparators of the readout circuitry. The value of the sampled voltage is controlled by a control circuitry which is able to predict and calculate at what time a ramp generator may carry the demand voltage value. The sampled voltage is held by a hold capacitor during readout of one row and is accessed during the next row by the control circuitry as test data to drive a device under test (DUT) which may be any portion of the image sensor to be tested. Measured data out of the DUT is compared with expected data. Based on the result of the comparison, a signal indicates the pass or fail of the self-test concludes a self-test of the DUT.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: September 14, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Zhiyong Zhan, Tongtong Yu, Xin Wang, Liang Zuo, Kenny Geng
  • Patent number: 11112811
    Abstract: Disclosed are embodiments of an integrated circuit (IC) chip that includes an on-chip parameter generation system. The system includes multiple parameter generators (e.g., voltage generators, current generators, capacitance generators, etc.) and an integrated calibration circuit. The calibration circuit is configured to automatically, sequentially, and repeatedly calibrate the parameter generators in order to minimize chip-to-chip variations in parameters supplied to other on-chip components under real world operating conditions throughout the life of the IC chip. In other words, the integrated calibration circuit effectively minimizes temperature-induced chip-to-chip variations, age-induced chip-to-chip variations, etc. in parameters generated by the on-chip parameter generators. Also disclosed herein are embodiments of an associated method.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: September 7, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Eric Hunt-Schroeder, Alexander J. Filmer
  • Patent number: 11109017
    Abstract: An imaging system may include two or more pipeline processing circuits that receive image data streams from two or more corresponding image sensors and process the received image data in parallel in an image signal processing mode of operation. The imaging system may include fault detection circuitry coupled to the two or more pipeline processing circuits. The fault detection circuitry may configure the two or more pipeline processing circuits with fault detection configuration states and generate injection data for processing by the two or more pipeline processing circuits in a fault detection mode of operation. Fault detection may be enabled dynamically based on a horizontal and vertical sync circuit and during an image processing pause period between image frames. The imaging system having the fault detection circuitry may be configured to efficiently perform fault detection without interrupting image signal processing.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 31, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Dannie Gerrit Feekes
  • Patent number: 11070219
    Abstract: A digital-to-analog converter includes a core circuit including a plurality of input terminals for multi-bit digital signals, an output terminal for an analog signal, a plurality of constant current sources, a plurality of switch circuits connected in series to respective constant current sources of the plurality of constant current sources, and a load resistor connected to the output terminal. The core circuit being configured to select whether or not to allow a current to flow through each of the plurality of switch circuits based on the multi-bit digital signals and output a voltage generated by allowing the current flowing through each of the plurality of switch circuits to flow through the load resistor from the output terminal as an analog signal.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: July 20, 2021
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Munehiko Nagatani, Hideyuki Nosaka
  • Patent number: 11070222
    Abstract: Disclosed is a SAR ADC (Ai) having an input for receiving an input voltage, a comparator, a first switch network configured to be controlled by the SAR state machine and connected to the input of the SAR ADC and to reference voltage nodes, and a first capacitor network. The first capacitor network has a first node connected to an input of the comparator, a second node, and a bridge capacitor (Cb) connected between the first node and the second node. Furthermore, the first capacitor network comprises a first set of capacitors having a first and a second terminal, wherein the first terminal of each capacitor in the first set is connected to the first node and the second terminal of each capacitor in the first set is connected to the switch network.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 20, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Mattias Palm, Lars Sundström, Ola Andersson
  • Patent number: 11057047
    Abstract: An analog to digital converter (ADC) circuit includes voltage and reference input terminals, a sample circuit, and control logic. The sample circuit includes input and output terminals, and capacitors connected in parallel and arranged between the input and output terminals. The control logic is configured to, in a calibration phase of operation, cause the multiplexer to route the ADC reference input terminal to the sampling voltage input terminal, determine a given gain value, determine a set of the capacitors to be used to achieve the given gain value, successively enable capacitor subsets to sample voltage of the reference input while disabling a remainder of the capacitors until all capacitors have been enabled, determine a resulting output code, and from the output code, determine a gain error of the given gain value of the ADC circuit.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Vincent Quiquempoix, Zeynep Sueda Turk
  • Patent number: 11057048
    Abstract: An analog to digital converter (ADC) includes voltage and reference input terminals, a buffer circuit, and control logic. The buffer circuit includes input and output terminals and a variable resistor including resistive branches connected in parallel. The control logic is configured to, in a calibration phase, determine a given gain value for which gain error is to be calibrated, determine a set of the resistive branches in the buffer circuit to be used to achieve the given gain value, successively enable a different resistive branch of the variable resistor of the set until all resistive branches of the set have been enabled, determine an output code resulting after enabling all resistive branches of the set, and, from the output code, determine a gain error of the given gain value. The control logic is further configured to take corrective action based upon the gain error of the given gain value.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: July 6, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Vincent Quiquempoix
  • Patent number: 11038517
    Abstract: A system includes a multiplying digital-to-analog converter (MDAC). The system also includes an input-side component coupled to the MDAC and configured to provide a code to the MDAC. The system also includes a reference voltage source coupled to the MDAC and configured to provide a reference voltage to the MDAC. The MDAC comprises a nonlinear calibration circuit configured to adjust an output of the MDAC nonlinearly based on the code, the reference voltage, and an output of the nonlinear calibration circuit.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 15, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Rajavelu Thinakaran
  • Patent number: 11012084
    Abstract: A method for calibrating a successive-approximation analog-to-digital converter (ADC) includes configuring the successive-approximation ADC in a calibration mode of operation. The method includes, while in the calibration mode of operation: determining a digital code corresponding to a programmable capacitance of the successive-approximation analog-to-digital converter, and storing the digital code corresponding to the programmable capacitance in a storage element of an integrated circuit die including the successive-approximation ADC. The programmable capacitance may be a gain tuning capacitance, a bridge tuning capacitance, an offset capacitance, or a monotonicity tuning capacitance.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 18, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Obaida Mohammed Khaled Abu Hilal
  • Patent number: 11005495
    Abstract: The present disclosure provides a current generation circuit. In one aspect, the circuit includes a current source transistor and a current sink transistor connected to the current source transistor in series, with respective sources of the current source and sink transistors being connected with each other at a common node. A voltage difference between respective gates of the current source and sink transistors defines a current value flowing through the series, the voltage difference being variable such that the current value is either time-dependent or time-independent. Respective drains of the current source and sink transistors provide a high resistance output necessary to provide a current source or sink function thereby rejecting influence of drain variation or error on the current value.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 11, 2021
    Assignee: SENSEEKER ENGINEERING, INC.
    Inventors: Kenton Veeder, Nishant Dhawan, Sean McCotter
  • Patent number: 10972129
    Abstract: A check node update processor of the low density parity check (LDPC) code decoder includes: an approximate first minimum (AFM) condition check unit which checks whether a predetermined specific condition is satisfied, and a check node determining unit which sets an approximate minimum value as a size of an entire check node output when it is determined that the specific condition is satisfied as a checking result in the AFM condition check unit and calculates a first minimum value as a true minimum value and sets a second minimum value as an approximate minimum value when it is determined that the specific condition is not satisfied to determine a size of the check node output.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jun Heo, Sung Sik Yoon, Byung Kyu Ahn
  • Patent number: 10951221
    Abstract: In some examples, a device includes an analog-to-digital converter (ADC) configured to receive an analog signal and output digital codes based on values of the analog signal. The device also includes a plurality of counters, where each counter of the plurality of counters is configured to increment in response to a respective digital code outputted by the ADC.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: March 16, 2021
    Assignee: Regents of the University of Minnesota
    Inventors: Gyusung Park, Hyung-il Kim
  • Patent number: 10944368
    Abstract: Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milam Paraschou, Jeffrey Cooper
  • Patent number: 10938402
    Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 2, 2021
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Che-Wei Hsu, Soon-Jyh Chang
  • Patent number: 10931907
    Abstract: An image sensor includes: a photoelectric conversion unit that photoelectrically converts incident light and generates a charge; and an A/D conversion unit that converts the analog signal generated due to charge generated by the photoelectric conversion unit into a digital signal, wherein: the A/D conversion unit includes a comparison unit that compares the analog signal with a reference signal and a first circuit layer including a first capacitor for generating the reference signal and a second circuit layer laminated to the first circuit layer and including with a second capacitor for generating the reference signal.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: February 23, 2021
    Assignee: NIKON CORPORATION
    Inventor: Tomoki Hirata
  • Patent number: 10917103
    Abstract: An analog-to-digital converter (ADC) device includes ADC circuitries, a calibration circuitry, and a skew adjusting circuitry. The ADC circuitries convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuitry performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuitry analyzes time difference information within even-numbered sampling periods of the clock signals, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 9, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Juh Kang, Yu-Chu Chen, Man-Pio Lam
  • Patent number: 10879881
    Abstract: A device with a noise shaping function in sampling frequency control includes a first adder, an N-bit quantizer, a mapping circuit, a second adder, a first D flip-flop, a scaler, and a second D flip-flop. The first adder generates a first value according to an input signal, a second value, and a third value. The N-bit quantizer outputs a codeword to a controller according to the first value. Frequency adjusting orders corresponding to codewords outputted by the N-bit quantizer are between a smallest predetermined negative value and a largest positive predetermined value, the controller utilizes an adjusting order corresponding to the codeword to make a frequency generator generate adjusted sampling frequency, and N is an integer greater than 2. The first D flip-flop, the scaler, and the second D flip-flop are used for providing a high-pass filter effect to the device.
    Type: Grant
    Filed: May 17, 2020
    Date of Patent: December 29, 2020
    Assignee: BlueX Microelectronics ( Hefei ) Co., Ltd.
    Inventors: Hao-Ming Chen, Yi-Chun Lu, Hongyu Li
  • Patent number: 10873338
    Abstract: An electronic circuit comprises an input voltage circuit, an analog-to-digital converter (ADC) circuit, and logic circuitry. The input voltage circuit is configured to generate multiple input voltages. The ADC circuit is configured to convert the multiple input voltages to first digital values using the first longer ADC acquisition time and convert the multiple input voltages to second digital values using the second shorter ADC acquisition time. The logic circuitry is configured to determine calibration information for the ADC circuit using the first digital values and the second digital values, and scale analog-to-digital (A/D) conversion results of the ADC circuit using the calibration information.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 22, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Yao Zhao, Aine McCarthy, Shuchun Xie, Ke Wei
  • Patent number: 10868562
    Abstract: A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mao-Hsuan Chou, Ya-Tin Chang, Ruey-Bin Sheen, Chih-Hsien Chang
  • Patent number: 10859626
    Abstract: A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 8, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Gang Zhao, Yongyao Li, Xusheng Liu
  • Patent number: 10852292
    Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown in an electrode formation process when an electrode and an amplifier are provided on a same substrate. A diode is provided of which a cathode is connected to a previous stage of an amplifying transistor for amplifying a signal read by a read electrode for reading a potential having contact with liquid in which a specimen is input and an anode is grounded. With such a configuration, by bypassing a negative charge generated between the electrode and the amplifying transistor in the electrode formation process from the diode and discharging the negative charge toward ground so as to prevent electrostatic breakdown. This is applicable to a bioelectric potential measuring apparatus.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 1, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Sato, Machiko Kametani, Jun Ogi, Yuri Kato
  • Patent number: 10848166
    Abstract: Techniques for saving operating power of an analog-to-digital converter (ADC) are provided. In an example, a circuit can include an ADC configured to provide a multiple-bit digital representation of an analog input during a first mode of operation and an output configured to provide a single bit representation of a first comparison of the analog input signal to a second analog signal during a second mode of operation. In certain examples, the circuit can include an encoder configured to provide the multiple-bit digital representation during the first mode and to power down during the second mode of operation.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 24, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: George Pieter Reitsma, Andreas Koch
  • Patent number: 10841013
    Abstract: A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decorder, for example, a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: November 17, 2020
    Assignee: INPHI CORPORATION
    Inventors: Oscar Ernesto Agazzi, Diego Ernesto Crivelli, Hugo Santiago Carrer, Mario Rafael Hueda, German Cesar Augusto Luna, Carl Grace
  • Patent number: 10827045
    Abstract: Provided are a data structure including a header area, and a payload area comprising data, a method of generating the data structure, and extracting information from the data structure. At least one of the header area and the payload area includes at least one sub-area in which one or more signal fields are included. At least one signal field among the signal fields includes information for signalling presence or absence of one or more information fields located at least partly in the data structure, the one or more information fields corresponding to the one or more signal fields.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Alain Mourad, Sung-hee Hwang, Daniel Ansorregui, Belkacem Mouhouche, Hak-ju Lee
  • Patent number: 10819365
    Abstract: Improved switching techniques for controlling three-level current steering DAC cells are disclosed. The techniques include decoupling two current sources, implemented as field-effect transistors (FETs), of a DAC cell both from their respective bias sources and from a load for converting a zero digital input, where the decoupling is performed in a certain order. The techniques also include coupling the current sources to their respective bias sources and to the load for converting a non-zero digital input, where the coupling is also performed in a certain order. The certain order of decoupling and coupling the bias sources and the load to the current sources of a DAC cell are based on the phenomenon of current memory in FETs. Utilizing current memory when operating a DAC cell may allow reducing power consumption while preserving the high performance properties of a three-level current steering DAC.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: October 27, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Khiem Quang Nguyen, Long Pham
  • Patent number: 10804918
    Abstract: The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2N?1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 13, 2020
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Xiaofeng Guo, Jon Sweat Duster, Haigang Feng, Ning Zhang, Yulin Tan
  • Patent number: 10794943
    Abstract: A capacitance adjustment method for enabling or disabling a first set of capacitors to an nth set of capacitors of n sets of capacitors, includes generating a base count according to base capacitance, generating a first count to an nth count according to the first set of capacitors to the nth set of capacitors respectively, obtaining a first ratio to an nth ratio according to the base count and the first count to the nth count, indicating a target count, obtaining a target ratio according to the base count and the target count, and obtaining a first control signal to an nth control signal according to the target ratio and the first ratio to the nth ratio so as to enable or disable the first set of capacitors to the nth set of capacitors accordingly.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 6, 2020
    Assignee: RichWave Technology Corp.
    Inventor: Ren-Hong Yen
  • Patent number: 10788376
    Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: September 29, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Mohamed M. Elsayed, Kenneth W. Fernald
  • Patent number: 10782363
    Abstract: Systems, methods, and apparatuses for magnetic field sensors with self-test include a detection circuit to detect speed and direction of a target. One or more circuits to test accuracy of the detected speed and direction may be included. One or more circuits to test accuracy of an oscillator may also be included. One or more circuits to test the accuracy of an analog-to-digital converter may also be included. Additionally, one or more IDDQ and/or built-in-self test (BIST) circuits may be included.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 22, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: P. Karl Scheller, James E. Burgess, Steven E. Snyder, Kristann L. Moody, Devon Fernandez, Andrea Foletto
  • Patent number: 10778242
    Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 10771078
    Abstract: A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 8, 2020
    Assignee: MEDIATEK INC.
    Inventor: Chun-Cheng Liu
  • Patent number: 10756829
    Abstract: An example method determines an error vector magnitude using automatic test equipment (ATE). The method includes demodulating data received at a first receiver to produce first symbol error vectors, where each first symbol error vector represents a difference between a predefined point on a constellation diagram and a first measured point on the constellation diagram generated based on at least part of the data received by the first receiver; demodulating the data received at a second receiver to produce second symbol error vectors, where each second symbol error vector represents a difference between the predefined point on the constellation diagram and a second measured point on the constellation diagram generated based on at least part of the data received by the second receiver; and determining the error vector magnitude for the data based on the first symbol error vectors and the second symbol error vectors.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 25, 2020
    Assignee: Teradyne, Inc.
    Inventor: Scott K. Therrien
  • Patent number: 10742227
    Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Yitzhak Elhanan Schifmann, Yoel Krupnik, Ariel Cohen
  • Patent number: 10742225
    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Martin Clara, Matteo Camponeschi, Christian Lindholm, Kameran Azadet
  • Patent number: 10735017
    Abstract: A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 4, 2020
    Assignee: GOODIX TECHNOLOGY INC.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10720841
    Abstract: A single ended n-bit hybrid digital-to-analog converter is configured to receive as an input an analog signal and produce an n-bit digital output. The converter includes a split main sub-digital-to-analog converter capacitor array, a most significant bit capacitor array, and a main capacitor array. A coupling capacitor couples the main array to the split main sub-digital-to-analog convert.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 21, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: Simon Chaput, Gu-Yeon Wei
  • Patent number: 10707888
    Abstract: A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Pernull, Peter Bogner
  • Patent number: 10700694
    Abstract: A calibration method applicable for a SAR ADC comprising a capacitor array, comprises the following operations: Inputting an input signal to the SAR ADC, wherein the SAR ADC is configured to generate an output signal according to the input signal, and the output signal comprises multiple selected digital codes; calculating average code densities for multiple digital code groups, respectively, wherein the multiple digital code groups are determined by dividing the multiple selected digital codes, and each of the multiple digital code groups comprises one or more selected digital codes of the multiple selected digital codes; calibrating capacitance of a first under-correction capacitor element of the capacitor array according to the first comparison result.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 30, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Hao Wang, Yu-Chu Chen
  • Patent number: 10686463
    Abstract: In accordance with various embodiments of the disclosed subject matter, a system, device, apparatus and method for calibrating a split bit digital readout to avoid misalignment of the least significant counter bit (i.e., the LSB of the M most significant bits) and most significant residual bit (i.e. the MSB of the N least significant bits). For example, various embodiments provide a field programmable gate array (FPGA), digital signal processing (DSP) function and the like configured to calibrate one or many split bit digital readouts such as may exist on a digital pixel sensor (DPS) or other device.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 16, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Matthew D. Howard
  • Patent number: 10665145
    Abstract: The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 26, 2020
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Shengdong Zhang, Chuanli Leng, Xingwu Lin
  • Patent number: 10659072
    Abstract: An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventor: Cho-Ying Lu
  • Patent number: 10630308
    Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Cheng Wu, Shih-Hsiung Huang
  • Patent number: 10623130
    Abstract: In some examples, a system includes a propulsor engine and a controller configured to determine a frequency for a new communication session on a communication channel based on a frequency of a previous communication session, wherein the frequency for the new communication session is different than the frequency of the previous communication session. In some examples, the controller is further configured to establish the new communication session via the communication channel with the propulsor engine. In some examples, the controller is also configured to exchange information with the propulsor engine at the frequency for the new communication session via the communication channel.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 14, 2020
    Assignee: Rolls-Royce North American Technologes, Inc.
    Inventor: Richard Joseph Skertic
  • Patent number: 10623011
    Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.
    Type: Grant
    Filed: May 4, 2019
    Date of Patent: April 14, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Hua-Chun Tseng, Tu-Hsiu Wang
  • Patent number: 10623013
    Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vishnu Ravinuthula, Kyl Wayne Scott
  • Patent number: 10615811
    Abstract: A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Hui Wu, Yu-Chang Chen, Chih-Lung Chen, Shih-Hsiung Huang
  • Patent number: 10606723
    Abstract: A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pankaj Bongale, Partha Ghosh, Rubin Ajit Parekhji
  • Patent number: 10601434
    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet, Matteo Camponeschi, Jose Luis Ceballos, Christian Lindholm, Hundo Shin, Martin Clara