Converter Calibration Or Testing Patents (Class 341/120)
  • Patent number: 10782363
    Abstract: Systems, methods, and apparatuses for magnetic field sensors with self-test include a detection circuit to detect speed and direction of a target. One or more circuits to test accuracy of the detected speed and direction may be included. One or more circuits to test accuracy of an oscillator may also be included. One or more circuits to test the accuracy of an analog-to-digital converter may also be included. Additionally, one or more IDDQ and/or built-in-self test (BIST) circuits may be included.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 22, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: P. Karl Scheller, James E. Burgess, Steven E. Snyder, Kristann L. Moody, Devon Fernandez, Andrea Foletto
  • Patent number: 10778242
    Abstract: An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 15, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 10771078
    Abstract: A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 8, 2020
    Assignee: MEDIATEK INC.
    Inventor: Chun-Cheng Liu
  • Patent number: 10756829
    Abstract: An example method determines an error vector magnitude using automatic test equipment (ATE). The method includes demodulating data received at a first receiver to produce first symbol error vectors, where each first symbol error vector represents a difference between a predefined point on a constellation diagram and a first measured point on the constellation diagram generated based on at least part of the data received by the first receiver; demodulating the data received at a second receiver to produce second symbol error vectors, where each second symbol error vector represents a difference between the predefined point on the constellation diagram and a second measured point on the constellation diagram generated based on at least part of the data received by the second receiver; and determining the error vector magnitude for the data based on the first symbol error vectors and the second symbol error vectors.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: August 25, 2020
    Assignee: Teradyne, Inc.
    Inventor: Scott K. Therrien
  • Patent number: 10742225
    Abstract: A n-bit Successive Approximation Register Analog-to-Digital Converter, SAR ADC, is provided. The SAR ADC comprises a respective plurality of sampling cells for each bit of the n-bit of the SAR ADC. Each sampling cell comprises a capacitive element coupled to a cell output of the sampling cell in order to provide a cell output signal. Further, each sampling cell comprises a first cell input for receiving a first signal, and a first switch circuit capable of selectively coupling the first cell input to the capacitive element. Each cell additionally comprises a second cell input for receiving a second signal, and a third cell input for receiving a third signal. The third signal exhibits opposite polarity compared to the second signal. Each sampling cell comprises a second switch circuit capable of selectively coupling one of the second cell input and the third cell input to the capacitive element. The SAR ADC further comprises at least one comparator circuit coupled to the sampling cells.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Martin Clara, Matteo Camponeschi, Christian Lindholm, Kameran Azadet
  • Patent number: 10742227
    Abstract: Describe is a buffer which comprises: a differential source follower coupled to a first input and a second input; first and second current steering devices coupled to the differential source follower; and a current source coupled to the first and second current steering devices. The buffer provides high supply noise rejection ratio (PSRR) together with high bandwidth.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Yitzhak Elhanan Schifmann, Yoel Krupnik, Ariel Cohen
  • Patent number: 10735017
    Abstract: A successive approximation register (SAR) analog to digital converter (ADC) is disclosed. The SAR ADC includes: a DAC, configured to receive an analog input voltage and a digital input word, and to generate a first voltage. The SAR ADC also includes a comparator, configured to generate a second voltage based on the first voltage and a reference voltage. The second voltage has a value corresponding with a sign of the difference between the first voltage and the reference voltage. The SAR ADC also includes an SAR logic circuit configured to receive the second voltage from the comparator, and to generate the digital input word for the DAC. The SAR logic is further configured to generate a digital output word representing the value of the analog input voltage, where the digital output word of the SAR logic has a greater number of bits than the digital input word of the DAC.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 4, 2020
    Assignee: GOODIX TECHNOLOGY INC.
    Inventors: Mohamed Aboudina, Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10720841
    Abstract: A single ended n-bit hybrid digital-to-analog converter is configured to receive as an input an analog signal and produce an n-bit digital output. The converter includes a split main sub-digital-to-analog converter capacitor array, a most significant bit capacitor array, and a main capacitor array. A coupling capacitor couples the main array to the split main sub-digital-to-analog convert.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: July 21, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: Simon Chaput, Gu-Yeon Wei
  • Patent number: 10707888
    Abstract: A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 7, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Pernull, Peter Bogner
  • Patent number: 10700694
    Abstract: A calibration method applicable for a SAR ADC comprising a capacitor array, comprises the following operations: Inputting an input signal to the SAR ADC, wherein the SAR ADC is configured to generate an output signal according to the input signal, and the output signal comprises multiple selected digital codes; calculating average code densities for multiple digital code groups, respectively, wherein the multiple digital code groups are determined by dividing the multiple selected digital codes, and each of the multiple digital code groups comprises one or more selected digital codes of the multiple selected digital codes; calibrating capacitance of a first under-correction capacitor element of the capacitor array according to the first comparison result.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 30, 2020
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Hao Wang, Yu-Chu Chen
  • Patent number: 10686463
    Abstract: In accordance with various embodiments of the disclosed subject matter, a system, device, apparatus and method for calibrating a split bit digital readout to avoid misalignment of the least significant counter bit (i.e., the LSB of the M most significant bits) and most significant residual bit (i.e. the MSB of the N least significant bits). For example, various embodiments provide a field programmable gate array (FPGA), digital signal processing (DSP) function and the like configured to calibrate one or many split bit digital readouts such as may exist on a digital pixel sensor (DPS) or other device.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: June 16, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventor: Matthew D. Howard
  • Patent number: 10665145
    Abstract: The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: May 26, 2020
    Assignee: Peking University Shenzhen Graduate School
    Inventors: Shengdong Zhang, Chuanli Leng, Xingwu Lin
  • Patent number: 10659072
    Abstract: An apparatus is provided to calibrate an analog-to-digital converter (ADC). The apparatus includes a calibration circuitry coupled to an output of the ADC, wherein the calibration circuitry is to identify a maximum value and minimum value of the output of the ADC, and is to calibrate one or more performance parameters of the ADC according to the maximum and minimum values. The performance parameters include: gain of the ADC, offset of the ADC, and timing skew between the ADC and a neighboring ADC.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventor: Cho-Ying Lu
  • Patent number: 10630308
    Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: April 21, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Cheng Wu, Shih-Hsiung Huang
  • Patent number: 10623011
    Abstract: A successive-approximation-register (SAR) analog-to-digital converter (ADC) includes an analog circuit and a digital control circuit. The digital control circuit is coupled to the analog circuit. The digital control circuit includes a calibration circuit, a memory device, and an asynchronous control circuit. The calibration circuit is configured to perform a calibration operation. The memory device is coupled to the calibration circuit and stores calibration information generated by performing the calibration operation. The asynchronous control circuit is coupled to the memory device, and reads the calibration information from the memory device in an asynchronous control mode. In the asynchronous control mode, before the asynchronous control circuit performs the operations of the SAR ADC, the asynchronous control circuit removes the non-idea effects of the SAR ADC according to the calibration information.
    Type: Grant
    Filed: May 4, 2019
    Date of Patent: April 14, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Hua-Chun Tseng, Tu-Hsiu Wang
  • Patent number: 10623130
    Abstract: In some examples, a system includes a propulsor engine and a controller configured to determine a frequency for a new communication session on a communication channel based on a frequency of a previous communication session, wherein the frequency for the new communication session is different than the frequency of the previous communication session. In some examples, the controller is further configured to establish the new communication session via the communication channel with the propulsor engine. In some examples, the controller is also configured to exchange information with the propulsor engine at the frequency for the new communication session via the communication channel.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: April 14, 2020
    Assignee: Rolls-Royce North American Technologes, Inc.
    Inventor: Richard Joseph Skertic
  • Patent number: 10623013
    Abstract: A battery powered system includes a voltage level shifter, an anti-aliasing filter, a pair of switches, a unity gain differential buffer, a second pair of switches, and an analog-to-digital converter. The first pair of switches couple the differential output port of the voltage level shifter to the differential input port of the anti-aliasing filter. The second pair of switches couple the differential output port of the anti-aliasing filter to the differential input port of the unity gain differential buffer. The analog-to-digital converter is coupled to the differential output port of the unity gain differential buffer.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vishnu Ravinuthula, Kyl Wayne Scott
  • Patent number: 10615811
    Abstract: A Successive Approximation Register (SAR) Analog-to-digital converter (ADC) includes: a digital-to-analog converter (DAC), a comparison circuit and a logic circuit. The DAC is configured to generate a transformed voltage according to a digital signal and a reference voltage, and the digital signal is generated by a digital signal generating circuit. The comparison circuit is coupled to the DAC and configured to compare the transformed voltage and an input voltage to generate a comparison result, and further configured to receive a control signal. The logic circuit is coupled to the comparison circuit, and configured to perform a logic transform operation upon the comparison result to generate an output signal to the digital signal generating circuit and the comparison circuit. The control signal controls the comparison circuit to enable or disable the SAR ADC.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: April 7, 2020
    Assignee: Realtek Semiconductor Corp.
    Inventors: Cheng-Hui Wu, Yu-Chang Chen, Chih-Lung Chen, Shih-Hsiung Huang
  • Patent number: 10606723
    Abstract: A test circuit that includes a circuit to be calibrated, an error generation circuit, and a simplex circuit coupled to one another. The circuit to be calibrated is configured to implement a first plurality of trim codes as calibration parameters for a corresponding plurality of components of the circuit to be calibrated and generate a first actual output. The error generation circuit is configured to generate a first error signal based on a difference between the first actual output and an expected output of the circuit to be calibrated. The simplex circuit is configured to receive the first error signal from the error generation circuit, generate a second plurality of trim codes utilizing a simplex algorithm based on the first error signal, and transmit the second plurality of trim codes to the circuit to be calibrated.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pankaj Bongale, Partha Ghosh, Rubin Ajit Parekhji
  • Patent number: 10601434
    Abstract: An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Albert Molina, Kameran Azadet, Matteo Camponeschi, Jose Luis Ceballos, Christian Lindholm, Hundo Shin, Martin Clara
  • Patent number: 10592209
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10594411
    Abstract: A method and system for measuring a device under test are disclosed. In some embodiments, a method of implementing a measurement system is provided. The method includes providing a plurality of nodes, each node including a combination of a communication tester configured to generate a communication signal and a channel emulator configured to emulate a channel, and providing a user interface configured to enable a user to control at least one of the plurality of nodes.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 17, 2020
    Assignee: ETS-Lindgren, Inc.
    Inventor: Michael David Foegelle
  • Patent number: 10593403
    Abstract: A memristive array includes a number of bit cells, each bit cell including a memristive element and a selecting transistor serially coupled to the memristive element. The array also includes a waveform generation device coupled to the number of bit cells. The waveform generation device generates a shaped waveform to be applied to the number of bit cells to switch a state of the memristive element. The waveform generation device passes the shaped waveform to gates of the selecting transistors of the number of bit cells.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng
  • Patent number: 10594332
    Abstract: A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 17, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Liang-Huan Lei, Jian-Ru Lin, Shih-Hsiung Huang
  • Patent number: 10594334
    Abstract: Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: March 17, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10587279
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry generates a first signal according to least significant bits of an input signal, and generates a second signal according to most significant bits of the input signal. The calibration circuitry compares the first signal with the second signal to generate a calibration signal, and calibrates the DAC circuitry according to the calibration signal. The calibration signal has bits. The calibration circuitry further repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the bits, and performs a statistic operation according to the comparison results, in order to adjust the at least one bit, and a number of the at least one bit is less than a number of the bits.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 10, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chih-Chieh Yang, Shih-Hsiung Huang, Liang-Huan Lei
  • Patent number: 10581446
    Abstract: Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 3, 2020
    Assignee: NXP USA, Inc.
    Inventors: Brandt Braswell, George Kunnen, Mark Lancaster
  • Patent number: 10582207
    Abstract: A video processing system includes a host processor, a video encoder and a memory. The host processor sends a configuration message to the video encoder that indicates to the video encoder how to encode a video frame and that includes information indicating the location of encoding configuration data that is stored in the memory. The video encoder receives the configuration message, uses the location indicating information to read the encoding configuration data from the memory, and encodes the video frame in accordance with the encoding configuration data read from the memory.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 3, 2020
    Assignee: Arm Limited
    Inventors: Dominic Hugo Symes, Sven Ola Johannes Hugosson
  • Patent number: 10581447
    Abstract: A method and apparatus for measuring phase response in a radio receiver is disclosed. A radio receiver includes a digital-to-analog (D/A) conversion unit coupled to receive a test signal. The D/A conversion unit includes a number of single-bit digital-to-analog conversion (DAC) circuits coupled to receive the test signal and configured to convert it into the analog domain. Clock signals received by each of the single-bit DAC circuits are out of phase with respect to one another. The output of the D/A conversion unit is an analog signal that is a composite of the signals output by the DAC circuits therein. The analog signal is then conveyed to an analog-to-digital converter (ADC) and converted into an N-bit digital signal. The N-bit digital signal is then conveyed to a correlator to determine a phase response of the radio receiver.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 3, 2020
    Assignee: Apple Inc.
    Inventors: Simone Gambini, Robert G. Lorenz
  • Patent number: 10581443
    Abstract: Offset correction in a differential successive approximation register (SAR) analog-to-digital converter (ADC) is accomplished with a capacitor-reduced digital-to-analog converter (DAC) topology to enable offset correction without the need for a dedicated compensation DAC. This eliminates addition analog circuitry and die area. To perform the offset correction, the differential SAR ADC couples together inputs thereof to create an offset voltage, converts the offset voltage into a digital representation thereof, stores the digital representation of the offset voltage in an offset register, and corrects for the offset voltage by generating an offset compensation voltage with the capacitor-reduced array DAC controlled by the digital representation stored in the offset register. The digital representation controls scaling of reference voltages to the reduced capacitor array DAC associated with a least-significant-bit (LSB) of the differential SAR ADC.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 3, 2020
    Assignee: Microchip Technology Incorporated
    Inventors: Anders Vinje, Ivar L√łkken
  • Patent number: 10554217
    Abstract: Provided is a sensor terminal including a sensor element, the sensor terminal further including: an ADC that converts an analog signal output from a sensor element into a digital signal; a storage device in which a plurality of first storage setting numbers being information for controlling the ADC and a plurality of pieces of first characteristic information including description of operation of the ADC are stored in association with each other; and a communication device that receives a first reception setting number from the outside of the sensor terminal, and transmits the first characteristic information corresponding to the first storage setting number that coincides with the first reception setting number, to the outside of the sensor terminal.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: February 4, 2020
    Assignee: HITACHI, LTD.
    Inventors: Yohei Nakamura, Taizo Yamawaki
  • Patent number: 10547322
    Abstract: An analog-digital converter has multiple feedback, and includes: a capacitor digital-analog converter including a plurality of switches driven by a digital code, and a plurality of capacitors respectively connected to the plurality of switches, wherein the capacitor digital-analog converter is configured to generate a residue voltage based on an analog input voltage and a voltage corresponding to the digital code; first and second feedback capacitors each storing the residue voltage; an integrator configured to generate an integral signal by integrating the residue voltage; first and second comparators respectively configured to generate first and second comparison signals from the integral signal; and a digital logic circuitry configured to receive the first and second comparison signals, and generate a digital output signal from the first and second comparison signals, the digital output signal corresponding to the digital code during a successive approximation register (SAR) analog-digital conversion inter
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Heon Lee, Michael Choi
  • Patent number: 10530338
    Abstract: There are provided: a table memory to store a relation between a control code and gains of variable gain amplifiers; a gain controller to apply the gains to the variable gain amplifiers; an amplitude phase detector to detect amplitude and a phase from an output signal of the vector sum phase shifter; an amplitude phase recorder to record, when the gains are applied by the gain controller, a combination of a control code corresponding to said gains and the amplitude and the phase detected by the detector; and a table calibrator to find a phase shift characteristic of a vector summed part from records of the amplitude phase recorder and calibrate the relation between a control code and gains recorded in the table memory by using the phase shift characteristic.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takaya Maruyama, Eiji Taniguchi, Takanobu Fujiwara, Koji Tsutsumi
  • Patent number: 10516410
    Abstract: An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: December 24, 2019
    Assignee: OLYMPUS CORPORATION
    Inventors: Shuzo Hiraide, Yasunari Harada, Masato Osawa, Hideki Kato
  • Patent number: 10484213
    Abstract: A circuit and method in an amplifier circuit for filtering a DC offset in differential input signals and inserting a programmable adjustable crosspoint offset in differential output signals. An amplifier circuit includes a differential amplifier circuit configured to amplify differential input signals into differential output signal. The amplifier circuit further includes a feedback circuit coupled between the differential output signals and the differential input signals. The feedback circuit is configured to generate a programmably adjustable crosspoint offset in the differential output signal and a programmably adjustable cutoff frequency of the feedback circuit. An amplifier method includes amplifying differential input signals into differential output signals, generating a programmably adjustable crosspoint offset in the differential output signal, and generating a programmably adjustable cutoff frequency of a feedback circuit between the differential output signals and the differential input signals.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 19, 2019
    Assignee: Finisar Corporation
    Inventor: Sagar Ray
  • Patent number: 10474553
    Abstract: Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiankun Jin, Mark Stachew
  • Patent number: 10469096
    Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: November 5, 2019
    Assignee: eSilicon Corporation
    Inventors: Nicola Ghittori, Claudio Nani, Enrico Monaco
  • Patent number: 10454491
    Abstract: A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 22, 2019
    Assignee: eSilicon Corporation
    Inventors: Nicola Ghittori, Claudio Nani, Enrico Monaco
  • Patent number: 10444309
    Abstract: The invention relates to a digital amplifier for providing a desired electrical output power, the amplifier comprising a power source (100) for generating the electrical output power, the amplifier further comprising: a digital input adapted for receiving a digital input signal (112), the digital input signal (112) representing the desired electrical output power level, a reference power generator (124) for generating an analogue reference power controlled by the digital input signal (112), a power measurement component (142; 128) adapted for measuring the power differential between the electrical output power provided by the power source (100) and the analogue reference power, an analogue-to-digital converter (130) adapted for converting the power differential into a digital power differential value (132), a combiner adapted for providing a combined digital signal (136) by adding the digital power differential value (132) to the digital value input to the reference power generator (124) for generating the
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: October 15, 2019
    Assignee: Koninklijke Philips N.V.
    Inventor: Martin Hollander
  • Patent number: 10389374
    Abstract: Approaches provide for calibrating high speed analog-to-digital converters (ADCs). For example, a calibration signal can be applied to parallel ADCs. The output of the parallel ADCs can be analyzed using a gradient-based optimization approach or other such optimization approach to determine optimized gain error calibration data to compensate for gain mismatch in and between individual parallel time-interleaved ADCs and to determine time-offset calibration data to compensate for timing errors in and between individual parallel time-interleaved ADCs. For example, once a calibration signal is applied to an ADC, the output of the ADC can be analyzed to determine a spectrum of the calibration signal. One or more images (e.g., phasors) of the spectrum can be determined and used to determine initial values of the optimization.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: August 20, 2019
    Assignee: SiTune Corporation
    Inventors: Mahdi Khoshgard, Marzieh Veyseh, Vahid M Toosi
  • Patent number: 10382048
    Abstract: Disclosed herein are systems for calibrating an analog-to-digital converter (ADC) device, as well as related devices and methods. In some embodiments, a system for calibrating an ADC device may include an ADC device, wherein the ADC device includes an ADC and a dither source, and wherein the ADC device is to apply a set of calibration parameters to generate digital outputs. The system may also include calibration circuitry, coupled to the ADC device, to determine which of multiple sets of values of calibration parameters results in the digital outputs having the lowest amount of noise, and to cause the ADC device to apply the calibration parameters associated with the lowest noise.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: August 13, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Paul R. Fernando, Sudarshan Ananda Natarajan
  • Patent number: 10378969
    Abstract: Methods and devices are provided where a first current and a second current are provided selectively to a semiconductor component, and times for charging a capacitor to a voltage at the semiconductor component are provided.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Di Zhu, Chin Yeong Koh
  • Patent number: 10367517
    Abstract: An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 30, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Cheng Wu, Shih-Hsiung Huang
  • Patent number: 10352775
    Abstract: A temperature sensor is disclosed. The temperature sensor includes an analog core having at least first and second circuit nodes and configured to provide a temperature dependent output, a multiplexer coupled to the first and second circuit nodes and configured for at least first and second states in each of which the first circuit node couples to a different circuit element and in each of which the second circuit node couples to a different circuit element, and a controller coupled to the analog core and configured to provide a temperature measurement that is an average of at least first and second readings of the temperature dependent output of the analog core, the first reading taken while the multiplexer is in the first state, and the second reading taken while the multiplexer is in the second state.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Dong Pan
  • Patent number: 10355684
    Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 16, 2019
    Assignees: SK HYNIX INC, KUMOH NATIONAL INSTITUTE OF TECHNOLOGY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Young Chan Jang, Pil Ho Lee, Kwang Hun Lee, Hyun Bae Lee
  • Patent number: 10348993
    Abstract: Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 9, 2019
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Michael Kelly, Daniel Mooney, Curtis Colonero, Robert Berger, Lawrence Candell
  • Patent number: 10345837
    Abstract: A voltage regulator has a comparator and a reference voltage coupled to a first input of the comparator. An output voltage of the voltage regulator is coupled to a second input of the comparator through a resistor. A current source is coupled to the second input of the comparator. The first current source can be a first digital-to-analog converter (DAC). A second current source can be coupled in parallel with the first DAC. The second current source can be a second DAC. The voltage regulator can include a boost topology.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: July 9, 2019
    Assignee: Semtech Corporation
    Inventor: Miguel Valencia
  • Patent number: 10340934
    Abstract: To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 2, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Nevena Rakuljic, Carroll C. Speir, Eric Otte, Corey Petersen, Jeffrey P. Bray
  • Patent number: 10333539
    Abstract: A calibration method includes the following: providing a first charge quantity to a first input terminal of a comparator; providing a second charge quantity to a second input terminal of the comparator by one of multiple switch capacitor groups, and providing a compensation charge quantity to the second input terminal of the comparator by at least another one of the switch capacitor groups; comparing a voltage value received by the first input terminal and a voltage value received by the second input terminal, and outputting a voltage comparison result to a controller; and if the controller determines the charge quantity provided to the second input terminal approximates to the charge quantity provided to the first input terminal based on the voltage comparison result, recording a calibration charge quantity in a lookup table stored by the controller. An analog-to-digital converter and a calibration apparatus are also provided.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 25, 2019
    Assignee: ITE Tech. Inc.
    Inventor: Jun-Hong Hsu
  • Patent number: RE47805
    Abstract: A method and apparatus for characterizing an A/D converter are provided. The A/D converter is configured to convert an input signal into a digital output signal. The method and apparatus may provide: applying an input signal to the A/D converter that in a first phase at least includes a gradient of a rising exponential function with Euler's number as the base, and in a further phase has a profile of a falling exponential function with Euler's number as the base, integrating a digital output signal associated with the A/D converter during the first phase to provide a first sum, integrating the digital output signal associated with the A/D converter during the further phase to provide a second sum, and calculating from the first sum and the second sum at least a gain error of the A/D converter and/or a zero point error of the A/D converter.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies AG
    Inventor: Heinz Mattes