Abstract: A calibration method of a pipeline analog-to-digital converter (ADC) that includes a residue amplifier includes the following steps: (A) generating an offset voltage; (B) adjusting a first input voltage of the residue amplifier according to the offset voltage and a reference digital code; (C) converting an output voltage of the residue amplifier into a second digital code; (D) performing a correlation operation on the reference digital code and the second digital code to generate an intermediate gain; (E) recording the intermediate gain; (F) repeating step (A) to step (E) to record a plurality of intermediate gains; (G) selecting one of the intermediate gains as a digital gain according to the second digital code; and (H) generating an output digital code according to a first digital code, the reference digital code, the digital gain, and the second digital code.

Abstract: A circuit includes a digital-to-analog converter and a gain stage. The gain stage includes: an operational amplifier; a variable gain network; and a leakage current control circuit. A first input of the operational amplifier is coupled to an input of the gain stage. An output of the operational amplifier is coupled to an output of the gain stage. A first terminal of the variable gain network is coupled to the second input of the operational amplifier. A second terminal of the variable gain network is coupled to the output of the operational amplifier. A first terminal of the leakage current control circuit is coupled to the output of the operational amplifier. A second terminal of the leakage current control circuit coupled to a third terminal of the variable gain network.

Abstract: A method (100) for characterising processing differences between analog channels, the method comprising injecting (102) three analog signals into a first analog channel and a second analog channel, digitising (104) these signals so as to obtain digital signals xk, xl and yl having N samples, estimating (106) parameters ?k,l and ?k,l from the digital signals, where ?k,l is a ratio between an amplitude of the first analog signal at the output of the first analog channel and an amplitude of the second analog signal at the output of the second analog channel, and where ?k,l is a difference between a phase shift induced by the first analog channel in the first analog signal and a phase shift induced by the second analog channel in the second analog signal, the estimation comprising the application of a least squares method in order to determine values of the parameters ?k,l and ?k,l minimising the following quantity: ? n = 1 N ( x k ( n ) - ? k , l ( cos ? ( ? k , l ) ? x l ( n

Abstract: A system and method for compensating segmented DAC intrinsic INL by adjusting the relative strength of DAC thermometer segments. In the method, the strength of each thermometer segment is adjusted sequentially to reduce INL to 0 at one point on each thermometer code range. The strength of the binary section is also adjusted to further reduce INL while conserving output amplitude. The system includes a calibration circuit that senses the DAC differential output and compares it to an ideal output generated from the same DAC via dithering between 0 and a maximum code. The compensation scheme only performs a specific type of DAC compensation, specifically compensating for systematic non-linearity rather than for mismatch-induced non-linearity. The method can also be applied to calibrate a full thermometer DAC.

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

Abstract: An apparatus can include a digital-to-analog converter (DAC) and calibration circuitry including an oscillator. The calibration circuitry can be coupled to an output of the DAC, the calibration circuitry to sample and count DAC output pulses for at least two consecutive pulses using at least two separate counter circuits. The calibration circuitry can determine error between at least two consecutive pulses and provide a correction value based on the error. The apparatus can further include correction circuitry to provide a calibration signal to the DAC based on the correction value.

Abstract: Systems and methods for increasing a false positive identification rate of a face recognition algorithm are provided. A method includes using a first image sensor, acquiring image data for a first facial image of a person and selecting an application profile for the first facial image. The application profile is selected to modify the image data to alter a value of an image classification feature used by a face recognition algorithm to increase a false positive identification rate of the face recognition algorithm that is configured to match an input facial image with at least one of N stored facial images. The method further includes, modifying an aspect associated with the face of the person, such that a second facial image of the face, when acquired by a second image sensor subsequent to the modification of the aspect, is different from the first facial image.

Abstract: A capacitive biometric skin contact sensor configured to resolve the contours of skin in contact with the sensor, wherein the sensor comprises: an array of sensor pixels, wherein each sensor pixel comprises a thin film transistor and a capacitive sensing electrode connected to the thin film transistor; a plurality of gate drive channels, wherein each gate drive channel is arranged to provide a gate drive signal to one or more of the sensor pixels; a plurality of read-out channels, wherein each read-out channel is arranged to receive a read-out current from one or more of the sensor pixels, each read-out current being indicative of a proximity to a respective capacitive sensing electrode of a conductive object to be sensed; and an analog to digital converter comprising a dual slope integrator arranged to receive, as its input, either an output current or a reference voltage, wherein said output current is based on one or more read-out currents; wherein the biometric sensor is configured to: apply the output cu

Abstract: A phase interpolator circuit has a first stage that selects a pair of phase vectors from among M available sets of pairs and a second stage that interpolates between the selected pair to phase align a sample clock. The interpolation functions applied to selected pairs of phase vectors can differ to account for integral non-linearity, duty-cycle distortion, phase errors, and crosstalk that vary between phase vectors.

Abstract: A circuit and method for calibrating ADCs and DACs generates a calibration signal by a DAC; filters spurs from the calibration signal from the DAC to generate a filtered calibration signal; calculates ADC interleave calibration factors to improve performance metrics of the ADC, responsive to the filtered calibration signal; receives the calibration signal from the DAC and calculates DAC interleave calibration factors; generates a calibration signal with improved performance metrics, responsive to the DAC interleave calibration factors received from the ADC; and repeats the process until the performance of the ADC and DAC are within a predetermined range.

Abstract: A method for use in an automated wireless industrial system comprising a device configured to act as a control node and at least one field level device, wherein the method comprises: issuing a control communication; inserting at least one time delay (tk) to the control communication; noting the communication time (TCL) for the communication; comparing the time for communication (TCL) to an expected time for communication (TR); and determining if any of the at least one time delay (tk) should be adapted, and if so, adapting at least that time delay.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a first converter, a second converter, and an adjustment circuit. The first converter is configured to sample an analog signal and convert the sampled analog signal to a first digital value based on a first clock signal. The second converter is configured to sample the analog signal and convert the sampled analog signal to a second digital value based on a second clock signal shifted a first phase from the first clock signal. The adjustment circuit is configured to adjust at least one of a gain of each of the first digital value and the second digital value and a phase of each of the first clock signal and the second clock signal based on the first digital value and the second digital value.

Abstract: A signal processing apparatus includes a plurality of time-interleaving digital-to-analog converters each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal. The signal processing apparatus includes analog multiplexer that samples the plurality of sub-DAC output signals at a preset multiplexer clock frequency and generates a multiplexer output signal. The signal processing apparatus further includes a local ADC that receives the multiplexer output signal and generate a digital feedback signal. The signal processing apparatus further includes a digital compensation engine that receives the digital feedback signal from the local ADC and determine one or more distortion compensation parameters.

Abstract: A measurement unit is disclosed and includes a converter unit and a processing unit is configured to provide a measurement result value, based on a first input signal and a second input signal. The converter unit is configured to provide a first digital, quantized values based on the first input signal or derived from the first input signal and the second input signal. The converter unit is further configured to provide second digital, quantized values based on the second input signal. The measurement unit is configured to change the one or more control signals of the converter unit between determination of different first values or a determination of the different second values, wherein different first values and/or different second values are provided using different converter quantization step sizes.

Abstract: A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.

Abstract: Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process variations. Furthermore, disclosed herein is ZQ calibration method that provides for calibrating of the impedance of each of an on-die termination, a pull-up driver, and a pull-down driver using a single calibration circuit.

Abstract: The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism is provided. A digital-to-analog conversion circuit includes conversion circuits to generate an output analog signal and echo-canceling analog signals. An echo transmission circuit processes an echo-transmitting path to generate an echo signal. An echo calibration circuit generates an output calibration signal and echo-canceling calibration signals according to an input digital circuit through calibration circuits corresponding to the conversion circuits. A calibration parameter calculating circuit generates a plurality of offsets according to an error signal of the echo signal relative to the calibration signals and path information related to the echo calibration circuit.

Abstract: A wireless transceiver having an in-phase quadrature-phase (IQ) calibration function includes a transmitter, a receiver, a signal generator, and a switch circuit. The switch circuit includes a first and a second switch circuits. The first switch circuit is turned on in a receiver-end calibration process, and outputs a predetermined signal from the signal generator to the transmitter. The second switch circuit is turned on in the receiver calibration process and outputs a derivative signal of the predetermined signal from the transmitter to the receiver to let the receiver performs a receiver-end IQ calibration accordingly. The first switch circuit is turned off and the second switch circuit is turned on in a transmitter-end calibration process; the second switch circuit outputs a radio-frequency signal from the transmitter to the receiver to let the receiver generates a calibration reference accordingly; and the transmitter performs a transmitter-end IQ calibration according to the calibration reference.

Abstract: In a first correction process, a correction value T(0) is set as a median value between minimum and maximum correction values Tmin(0) and Tmax(0). A provisional adjustment value B=T(0)+Bini is input to the circuit section. A signal value output from the circuit section in accordance with the provisional adjustment value B is obtained by an A/D converter, and the magnitude relationship between the signal value and a target value is determined. When the signal value is smaller than the target value, a value that is smaller than the correction value T(0) by an error tolerance is set as a new minimum correction value Tmin(1). The median value between the minimum correction value Tmin(1) and the maximum correction value Tmax(1)=Tmax(0) is set as a next correction value T(1). In the next correction process, the provisional adjustment value B=T(1)+Bini is input to the circuit section.

Abstract: Aspects of the present disclosure provide measurement devices and methods for detecting electrical characteristics of devices under test (DUTs), such as semiconductor nanowires. Techniques described herein provide programmable measurement devices that may be implemented in a compact form factor while being able to perform reliable measurements. In some embodiments, measurement devices described herein may be programmed to modulate signals for transmitting to a DUT, and may demodulate signals from the DUTs adaptively using self-programming techniques described herein. Such self-programming may include applying a programmable phase delay to oscillator signals used during demodulation. In some embodiments, such measurement devices may be implemented on a single circuit board, in a single integrated circuit package, or even on a single solid-state semiconductor die. Techniques described herein may enable reliable, inexpensive, and small-scale fluid sample measurement devices.

Abstract: A method for precise acquisition of a signal of a sensor, by an evaluation and control unit which has a multiplexer at whose inputs there is at least one reference voltage whose voltage value is known, a ground potential of the reference voltage, a measurement signal of the exhaust gas sensor, and a ground potential of the measurement signal. A computer is connected downstream from the multiplexer via a transmission path and via an ADC that converts a voltage between its two inputs into a digital value. The method provides that a plurality of individual measurements are carried out in which switching states of the multiplexer are modified, and digital values are subsequently acquired at the output of the ADC. The computer calculates a measurement value, corrected with regard to offset and gain, from these digital values.

Abstract: Analogue-to-digital converter, ADC, circuitry including: successive-approximation circuitry configured in a subconversion operation to draw a charge from a first voltage reference, REF1; compensation circuitry including a compensation capacitor and configured, in a precharge operation, to connect the compensation capacitor so that the compensation capacitor stores a compensation charge, and, in the subconversion operation, to connect the compensation capacitor to the first voltage reference so that a charge is injected into the first voltage reference, REF1; and control circuitry, wherein: the successive-approximation circuitry and the compensation circuitry are configured such that one or more parameters defining at least one of said charges are controllable; and the control circuitry is configured to adjust at least one said parameter to adjust an extent to which the charge injected into the first voltage reference, REF1, by the compensation circuitry compensates for the charge drawn from the first voltage

Abstract: Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.

Abstract: According to an embodiment, a digital microphone includes an analog-to-digital converter (ADC) for receiving an analog input signal; a DC blocker component coupled to the ADC; a digital low pass filter coupled to the DC block component; and a nonlinear compensation component coupled to the digital low pass filter for providing a digital output signal.

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.

Abstract: Methods and apparatus for controlling a power supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch; and calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells and having an output coupled to at least one of the plurality of DAC cells, the calibration circuitry being configured to sense a voltage of the first node in the first DAC cell and to control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on the sensed voltage of the first node.

Abstract: An electronic circuit includes a ramp signal generator, an oscillator, a monitoring circuit and a logic controller. The ramp signal generator generates a ramp signal. The oscillator generates a clock signal. The monitoring circuit operates in an operation mode selected from a first mode of monitoring an external output voltage and a second mode of performing an analog built-in self-test (ABIST), and generates a comparator output. The logic controller controls the monitoring circuit to operate in the operation mode. When the monitoring circuit operates in the second mode, the logic controller counts the clock signal, controls the monitoring circuit to perform the ABIST based on the ramp signal, and generates an ABIST output indicating whether the monitoring circuit operates normally based on a value of the counting and the comparator output.

Abstract: A data sensing circuit includes one or more drive sense circuits operably coupled to a plurality of data sources. The one or more drive sense circuits produces a plurality of digital sense signals regarding the plurality of data sources at an oversampling rate. The data sensing circuit further includes a digital filtering circuit operably coupled to receive, in parallel, at least some of the plurality of digital sense signals and generate, in a serial manner, a plurality of affect values from the least some of the plurality of digital sense signals.

Abstract: The present disclosure provides an analog-to-digital converter system comprising a sampler configured to sample an input signal and provide at least two output signals with a predetermined output sample rate, and an analog-to-digital converter for each one of the output signals and configured to convert the respective output signal into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate. Further, the present disclosure provides a respective method.

Abstract: An electronic device is provided. The electronic device includes an image sensor including a plurality of unit pixels, each unit pixel including two or more individual pixels, and at least one processor. The at least one processor is configured to acquire a first image frame from the image sensor, determine a photographing environment of the electronic device, based on the first image frame, and, in response to the photographing environment corresponding to a first photographing environment, control the image sensor to acquire analog data through the individual pixels, and provide first digital data digitally converted from the analog data with first sensitivity, and second digital data digitally converted from the analog data with second sensitivity which is higher than the first sensitivity, and acquire a second image frame which follows the first image frame, based on the first digital data and the second digital data.

Abstract: A receiver includes an interface configured to receive a data signal based on an n-level pulse amplitude modulation (PAM-n) in which n is an integer equal to or greater than 4. The interface may include an analog-digital converting circuit configured to adjust a reference voltage, for distinguishing second bit data from the data signal in a second section, based on first bit data converted from the data signal in a first section and the first bit data converted from the data signal in the second section, the second section being after the first section.

Abstract: A delta-sigma modulation apparatus performs delta-sigma modulation on a first signal as an input signal and outputs a second signal, outputs, using the second signal and a third signal generated through a transmission process of the second signal, a fourth signal that is an approximated value of a signal which is generated through at least part of the transmission process, and performs the delta-sigma modulation on the first signal using the fourth signal and outputs the second signal.

Abstract: The present disclosure relates to the field of biometric parameter measurement, and in particular, to a temperature measurement circuit, a temperature measurement method, a temperature and light intensity measurement circuit, a temperature and light intensity measurement method, a chip, a module, and an electronic device. A temperature signal is obtained based on an output voltage of a differential amplifier circuit when a non-inverting input terminal of the differential amplifier circuit is unload, an output voltage of the differential amplifier circuit when the non-inverting input terminal of the differential amplifier circuit is connected to a calibration resistor, and the output voltage of the differential amplifier circuit when the non-inverting input terminal of the differential amplifier circuit is connected to a thermistor, which improves the accuracy of the temperature measurement.

Abstract: A capacitive biometric skin contact sensor configured to resolve the contours of skin in contact with the sensor, wherein the sensor comprises: a contact sensing area comprising an array of sensor pixels, wherein each sensor pixel comprises a thin film transistor and a capacitive sensing electrode connected to the thin film transistor; a plurality of gate drive channels, wherein each gate drive channel is arranged to provide a gate drive signal to one or more of the sensor pixels; a plurality of read-out channels, wherein each read-out channel is arranged to receive a read-out current from one or more of the sensor pixels, each read-out current being indicative of a proximity to a respective capacitive sensing electrode of a conductive object to be sensed; a current multiplexer connected to a plurality of the read-out channels to receive read-out currents therefrom; and an analog to digital converter configured to provide a digital signal based on said read-out currents; wherein the sensor is configured to co

Abstract: Described is an apparatus to concurrently measure multiple input voltages at a high sampling data rate, such as at least two mega-samples per second. The apparatus may include a plurality of voltage data acquisition components that concurrently sample different input voltages and produce respective voltage data samples. Each of the plurality of voltage data acquisition components may be directly coupled to a field programmable gate array that receives the voltage data samples, packetizes those voltage data samples, and provide the packetized voltage data samples to a system on chip.

Abstract: A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.

Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

Abstract: Embodiments of sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a bias compensation circuit configured to measure a biasing condition of a first OTA of the pair of OTAs and to apply the biasing condition of the first OTA to a second OTA of the pair of OTAs to reduce Total Harmonic Distortion Plus Noise (THD+N) in the sigma-delta ADC circuit. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Abstract: A successive-approximation analog-to-digital converter includes a sampling circuit for sampling an analog input signal to acquire a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a succession of reference voltages to generate, for each reference voltage, a decision bit indicating the comparison result. The converter also includes a digital-to-analog converter which is adapted to generate the succession of reference voltages, in dependence on successive comparison results in the comparator, to progressively approximate the sampled voltage. The regenerative comparator comprises an integration circuit for generating output signals defining the decision bits, and a plurality of regeneration circuits for receiving these output signals. The regeneration circuits are operable, in response to respective control signals, to store respective decision bits defined by successive output signals from the integration circuit.

Abstract: This disclosure falls into the field of audio coding, in particular it is related to the field of providing a framework for providing loudness consistency among differing audio output signals. In particular, the disclosure relates to methods, computer program products and apparatus for encoding and decoding of audio data bitstreams in order to attain a desired loudness level of an output audio signal.

Abstract: A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.

Abstract: The present invention discloses a signal gain tuning circuit having adaptive mechanism. An amplifier receives an analog signal to generate a tuned analog signal to an ADC circuit to further generate a digital signal. A gain control capacitor array and the amplifier together determine a gain of the tuned analog signal. The control circuit receives an actual level of the digital signal to determine an offset of the digital signal and an estimated level to generate a tuning control signal. Each of coarse-tuning capacitors of a coarse-tuning capacitor array corresponds to a first tuning amount relative to a maximal gain. Each of fine-tuning capacitors of a fine-tuning capacitor array corresponds to a second tuning amount relative to the maximal gain. A tuning capacitor enabling combination of the coarse-tuning and fine-tuning capacitor arrays are determined according to the tuning control signal to tune the gain and decrease the offset.

Abstract: An analog-to-digital converter comprising a plurality of sampling cells. At least one of the plurality of sampling cells comprises a capacitive element coupled to a cell output of the at least one of the plurality of sampling cells, wherein a cell output signal is provided at the cell output. The at least one of the plurality of sampling cells further comprises a first cell input for receiving an input signal to be digitized, and a second cell input for receiving a calibration signal. Additionally, the at least one of the plurality of sampling cells comprises a first switch circuit capable of selectively coupling the first cell input to the capacitive element based on a clock signal, and a second switch circuit capable of selectively coupling the second cell input to the capacitive element, wherein a size of the second switch circuit is smaller than a size of the first switch circuit.

Abstract: An example apparatus includes: nonlinearity function selection circuitry with an output, the nonlinearity function selection circuitry to select a type of a nonlinearity function, the nonlinearity function to model nonlinearity portions of data output from an analog-to-digital converter, nonlinearity function term generation circuitry with a first input coupled to the output, the nonlinearity function term generation circuitry to generate one or more nonlinearity function terms of the nonlinearity function based on the type of the nonlinearity function and the data, and coefficient determination circuitry with a second input coupled to the output, the coefficient determination circuitry to determine one or more nonlinearity function coefficients based on the one or more nonlinearity function terms, the nonlinearity portions of the data to be compensated based on the one or more nonlinearity function coefficients.

Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.

Abstract: A transmitter includes a shift register, a lookup table, and a digital to analog converter. The shift register is configured to receive an input signal and to output delayed copies of the input signal. The lookup table is configured to store compensation values estimated based on the input signal and the delayed copies of the input signal. The digital to analog converter is configured to output a transmit signal based on the input signal and the compensation values. The compensation values are designed to mitigate distortion of the transmit signal from conversion of the input signal to a digital signal.

Abstract: An electricity usage monitor may include a coupling component to attach the electricity usage monitor to an electrical circuit to monitor electricity usage of the electrical circuit, an analog-digital converter (ADC) configured to convert analog current readings captured by the electricity usage monitor into digital values, a processor operably coupled to the ADC, and a non-transitory, computer-readable medium operably coupled to the processor and comprising instructions which, when executed by the processor, cause the processor to perform operations. The operations may include determining a standard deviation of the digital values, based on the standard deviation, adjusting a gain of the ADC, and transmitting a signal to a server comprising the digital values.

Abstract: An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.