Abstract: An apparatus configured for built in self test (BiST) of analog-to-digital convertors (ADCs) is described. The apparatus includes an ADC to be tested. The apparatus includes a ramp generator. The ramp generator provides a voltage ramp to the ADC. The apparatus further includes feedback circuitry for the ramp generator. The feedback circuitry maintains a constant ramp slope for the ramp generator. The apparatus includes an interval counter. The interval counter provides a timing reference.

Abstract: A self-calibration circuit and method for capacitors are provided. A capacitor array is calibrated to approximate a reference capacitor according to an average parameter generated by calibrating the capacitor array multiple times. Since the capacitance of the compensation capacitor required to be connected to the target capacitor in parallel is determined according to the average parameter generated by performing the calibration multiple times, the error caused by a single calibration can be reduced, and meanwhile the calibration error caused by a reference voltage error or noise is reduced.

Abstract: A PRA-DAC is disclosed. The PRA-DAC is operable to increase its conversion speed.

Abstract: A reference voltage generating unit generates a plurality of analog reference voltages, and an A/D converting unit converts the analog reference voltages thus generated and an analog input voltage input from an external device to digital reference values. A CPU generates, based on the analog reference voltages and the digital reference values converted from the analog reference voltages, an equation for correcting the analog input voltage to be converted to a digital value falling in a range of the digital reference values. With the equation generated, the CPU calculates the analog input voltage for the digital value obtained by conversion.

Abstract: The present invention provides a signal converting apparatus with built-in self test, including a first signal converting circuit, a second signal converting circuit, a comparing apparatus, a control logic apparatus and a voltage divider. The first and the second signal converting circuit take a first and a second reference voltage and are respectively controlled by a first and second set of control signals from the control logic apparatus for the comparing apparatus to generate a comparing result.

Abstract: A ramp voltage generation circuit suitable for an A/D converter preventing a variation in a digital value obtained by an A/D conversion operation. The circuit comprises a stabilization voltage source Vref, an operation amplifier AMP1 having a non-inversion input terminal receiving a voltage VREF from the Vref and an inversion input terminal connected to a switched capacitor equivalent resistance Req, and a transistor MNSF for conducting a current Ick to the Req based on an output voltage of the AMP1. Both ends of a conductive load Cint charged and discharged based on a current Iint2 generated by a current mirror of the Ick are connected to an output terminal and an inversion input terminal of an operation amplifier AMPint, a voltage of a stabilization voltage source Vc is applied to a non-inversion input terminal, and an output voltage of the AMPint is outputted to the outside as a ramp voltage.

Abstract: A precision digital to analog conversion circuit and method are provided. A regulated direct current (DC) voltage having a DC voltage magnitude is supplied to a device, such as a processor. The processor generates a pulse width modulation (PWM) output signal based, at least in part, on the regulated DC voltage. An analog output signal is generated from the PWM output signal. The regulated DC voltage is compared to a precision reference DC voltage, the DC voltage magnitude is selectively adjusted based on the comparison.

Abstract: A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired.

Abstract: A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.

Abstract: A sigma-delta converter suitable for measuring a photocurrent comprises an input node adapted to receive a current to be measured (Imeas), a capacitor connected to the input node, a clocked comparator coupled to the input node and to a reference voltage Vref at respective inputs, and a switchable current source connected to the input node which conducts a reference current Iref when switched on. The converter is arranged in a sigma-delta configuration, with the current source switched on to pull down the voltage (VCMP) at the input node when the comparator output toggles due to VCMP increasing above Vref, and to be switched off when the comparator output toggles due to VCMP falling below Vref, such that the comparator output comprises a digital bitstream which varies with Imeas.

Abstract: A calibration circuit and method suitable for black level calibration in image processing, the circuit comprising an analogue gain amplifier, an analogue to digital converter; a correction circuit for receiving a digital signal and providing a digital offset signal; and a digital to analogue converter for receiving said digital offset signal and feeding a corresponding analogue offset signal back to the input of said gain amplifier. The calibration circuit is arranged such that the correction circuit and said digital to analogue converter form a feedback loop applying an offset to said input signal and said correction circuit includes an inverse gain circuit for applying an inverse gain to a signal within said correction circuit prior to said digital to analogue converter. Preferably the inverse gain applied is such that the total loop gain does not deviate too far from unity.

Abstract: A single-pass method of trimming a network, and a network manufactured according to the method, uses the assumption that the peak INL value is minimized by trimming all the structures in the network to a same target value based upon the boundary conditions of the discretely adjustable elements that make up the structures. Using this assumption, the number of targets that need to be simulated, can be greatly reduced making estimation of peak INL possible in a reasonable amount of testing or manufacturing time. The trim algorithm produces results that are optimum or substantially close to optimum and is guaranteed not to deteriorate the Peak INL compared to the untrimmed Peak INL. An auto-calibration system using the trim method is also provided so that the method can be used in a product in real time if desired.

Abstract: A switch signal generator circuit that may form part of a digital to analog converter is provided. The switch signal generator circuit may include a first switch that controls a high reference gate voltage. The high reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a high reference voltage to the digital to analog converter. The switch signal generator circuit may include a second switch that controls a low reference gate voltage. The low reference gate voltage may provide the ON state voltage for a plurality of switches that control the coupling of a low reference voltage to the digital to analog converter. The switch signal generator circuit may also include a resistor. In one embodiment of the invention, a current conducted by the first switch and/or a current conducted by the second switch may each be proportional to a current conducted by the resistor. One of the switches in the switch generator circuit may be a P channel switch.

Abstract: An optical receiving device of the present invention receives optical signals from an optical transmitting device which uses a modulation format wherein an optical intensity waveform of each symbol is return-to-zero (RZ) pulse, and converts the received optical signals into digital signals by a conversion process of an analog to digital (AD) converter. A control-value calculating unit subsequent to the AD converter digitally processes the digital signals, retrieves an absolute value of the digital signals or a value corresponding one-to-one with the absolute value of the digital signals, estimates errors from an appropriate timing of a sampling timing in the AD converter based on the absolute value of the digital signals or the value corresponding one-to-one with the absolute value of the digital signals, and calculates a control value controlling the sampling timing based on the estimated errors.

Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.

Abstract: A comparator compares an input voltage and a reference voltage and generates an output based on the comparison. The comparator may receive the input voltage in a normal mode of operation. Voltage band circuitry provides first and second test voltages to the comparator. The test voltages define a band around the reference voltage. An integrator adjusts an offset correction signal provided to the comparator based on outputs of the comparator that are generated using the test voltages. The output of the comparator that is generated using the first test voltage could be generated during a first auto-zeroing cycle. The output of the comparator that is generated using the second test voltage could be generated during a second auto-zeroing cycle. This technique helps to maintain the offset of the comparator with the band around the reference voltage.

Abstract: A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits. Each of the pair of variable resistance circuits may adjust a resistor segment of the DAC.

Abstract: A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Abstract: An analog-to-digital converter compensation method includes providing at least one analog tone, converting the analog tone into digital signals, and using the digital signals to generate an error compensation model comprising a plurality of compensation values corresponding to respective digital signals. The compensation values are obtained by applying a time domain window, performing a discrete Fourier transform on digital signals within the time domain window, zeroing out transform bins except for bins within lobes on selected spurious frequencies, performing an inverse Fourier transform, and obtaining resulting signals from applying an inverse of the time domain window.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: A trimdac circuit for adjusting the output of a digital-to-analog converter (DAC) is provided. The trimdac may be used, to adjust a plurality of resistor segments in the DAC. The trimdac may include a programmable Read Only Memory (ROM) or other suitable memory device. The ROM may include a plurality of multi-bit digital words. Each of the multi-bit digital words may control a plurality, and most preferably a pair of variable resistance circuits.

Abstract: A circuit for calibrating a resistance value on an integrated circuit includes a resistor network, a reference voltage generator, a comparator, a servo loop, and a shift register. The resistor network includes a plurality of resistor and switch pairs in parallel. The resistor network further includes a servo resistor in series with a servo resistor switch such that the servo resistor and servo resistor switch are in parallel with the plurality of resistor and switch pairs. The servo loop generates a shift register gating signal and includes a current sample register for storing a current comparator output data value and a previous sample register for storing a previous comparator output data value. The shift register, upon receipt of a shift register gating signal at a first state, inputs the current comparator output data value to shift data bits through the shift register.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor that is based at least in part on N1/(N+N1) is obtained.

Abstract: A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

Abstract: The device for detecting and tracking a status of a device under laser trim includes: a series connected string of trim tracking links; and a plurality of detecting devices wherein each detecting device is coupled in parallel with a corresponding trim tracking link. This device allows detection of laser beam to work surface misalignment and the termination of lasing before critical active circuit components can be damaged.

Abstract: An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combination. A first output connection is controlled by first and third data paths. A second output connection is controlled by second and fourth data paths. Each data path is defined such that a currently exercised data path generates an output signal having an asserted state on the output connection that is controlled by the currently exercised data path. The currently exercised data path is also defined to cause a next data path in the sequence to generate an output signal having a non-asserted state on the output connection that is controlled by the next data path.

Abstract: Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.

Abstract: A low-noise current reference circuitry includes a voltage source, a current source, and a controller. The voltage source generates a reference voltage. The current source provides a low-noise output current in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the reference voltage and a voltage derived from the output current. A low-noise voltage reference circuitry includes a reference voltage source, a voltage source, and a controller. The reference voltage source generates a reference voltage. The voltage source provides a low-noise output voltage in response to a control signal. The controller provides the control signal based at least in part on the relative magnitudes of the output voltage and the reference voltage.

Abstract: An offset compensating apparatus and method of a digital/analog converter that are capable of preventing an offset of a driving unit by switching an offset generated from an LCD panel driving unit of an LCD projection TV, by adding a current cell of the least significant bit, by adjusting and outputting a Vcom voltage of a buffer stage, or by including an offset compensating unit for changing a digital coding circuit.

Abstract: In a semiconductor integrated circuit, serially inputted trimming data are sequentially written to plural memory cells in accordance with selection signals for trimming a bleeder resistor, making it possible to dispense with a data register for storing the trimming data, thereby saving layout area.

Abstract: A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

Abstract: Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

Abstract: Trimming by disconnecting a fuse connected in parallel to a feedback resistor of an amplifier circuit would cause a variation in voltage value due to a remaining resistance component. A voltage generator circuit is provided therein with a D/A converter circuit of an R-2R ladder resistor network type circuit. The D/A converter circuit is provided with a first switch circuit to an eighth switch circuit, corresponding to each bit, which are switched to set a digital value. Each switch circuit, which is provided with a fuse for providing a fixed voltage value, allows the fuse to be disconnected to fix the voltage value to a value obtained by inverting the initial value. The setting circuit controls the switching operation of each switch circuit, thereby simulating an electrical state of a fuse being disconnected before the fuse is actually disconnected.

Abstract: A parameter of an integrated circuit including a first trim array and a second trim array is trimmed by measuring an initial value of the parameter, determining whether the parameter exceeds a reference value, and as long as the parameter exceeds the reference value, repetitively blowing fuses associated with binarily weighted trim elements of the first trim array to eliminate trim contributions thereof to thereby decrease the parameter by weighted amounts corresponding to a present trim array bit number value until either all fuses of the first trim array have been blown or enough have been blown to cause the parameter to be less than a ?LSB/2 weight. If the parameter then is less than the ?LSB/2 weight, a fuse of the second trim array corresponding to a present bit number is blown to increase the parameter to greater than a +LSB/2 weight. The procedure is repeated until all fuses in one trim array have been blown, to thereby minimize the number of residual trim elements.

Abstract: A calibration circuitry includes an adjustable capacitor, a voltage generator, a reference voltage generator, and a controller. The reference voltage generator provides a reference voltage. The voltage generator provides a measurement voltage that depends on the capacitance of the adjustable capacitor. The capacitance of the adjustable capacitor varies in response to a control signal. The controller provides the control signal based on the relative values of the reference voltage and the measurement voltage.

Abstract: A pipelined analog to digital converter. Each stage in the pipeline has a flash converter and a multiplying digital to analog converter. Each stage provides a digital bits and an analog residue that is passed to the next stage in the pipeline. The digital bits from all stages are combined in digital logic to produce the digital output of the converter. The flash converter in each stage has a set of comparators, each coupled to a reference ladder. A random number generator in connection with a switch matrix “shuffles” the reference inputs to the comparators. The comparators are latched as soon as practical after they are stable and the reference inputs are shuffled as soon as practical after the comparators are latched. Also, a bandwidth trim circuit is provided to compensate for different cutoff frequencies of the input impedances of the flash and multiplying digital to analog converters.

Abstract: A method and apparatus for testing ADC circuitry. The method and apparatus detects infrequently occurring errors by providing a series of waveforms to the ADC that have different amplitude, frequency, or voltage offset from one another. The outputs of the ADC for the waveforms are then analyzed for timing related errors.

Abstract: An A/D converter calibration apparatus includes a set of operating condition parameter sensors (100) for detecting the current operating conditions, which are represented by parameters x1, . . . , xN. The measured parameters are forwarded to an operating conditions change detector (102), which calculates a change measure and determines whether this measure exceeds a predetermined change threshold. When a change exceeding the threshold has been detected, a calibration trigger signal CAL_TRIG is passed to a calibration control unit (104), which initiates a background calibration sequence.

Abstract: A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron injection are the mechanisms used to vary the amount of charge on the floating gate. Since floating gate devices store charge essentially indefinitely, no continuous trimming mechanism is required, although one could be implemented if desired. By trimming the current sources with high accuracy, a DAC can be built with a much higher resolution and with smaller size than that provided by intrinsic device matching.

Abstract: A variable impedance network for the use in building potentiometers and digital-to-analog converters (DAC) is disclosed. The impedance network is constructed such that it reduces the overhead circuits associated with it compared to conventional approach. The percent reduction of overhead circuitry including the wiper transistors increases exponentially as the number of the taps required for the potentiometer increases.

Abstract: A digital-to-analog (D/A) converter with a required accuracy can be implemented in a smaller chip area and at a lower cost. The D/A converter comprises a decoder which receives a digital input signal comprised of a first number of bits, and divides the first number of bits into a second number of bit groups. Bit group converters equal in number to the second number, are provided for the second number of bit groups, and each selects and uses a form of weight for each of the bit groups associated therewith to convert the bit group into an analog form in response to the second number of bit groups, thereby generating the second number of bit group analog outputs. An adder adds the second number of the bit group analog outputs to form an analog signal output representative of the digital signal input.

Abstract: A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

Abstract: An improved self-calibrating and self-repairing Data Acquisition System (DAS) for use in inaccessible areas, such as onboard spacecraft, and capable of autonomously performing required system health checks, failure detection. When required, self-repair is implemented utilizing a “spare parts/tool box” system. The available number of spare components primarily depends upon each component's predicted reliability which may be determined using Mean Time Between Failures (MTBF) analysis. Failing or degrading components are electronically removed and disabled to reduce power consumption, before being electronically replaced with spare components.

Abstract: The present invention provides methods and apparatus for trimming semiconductor devices and circuits, such as pin electronics circuits used in automated test equipment (ATE) systems and the like, without requiring a laser trimming operation. In a preferred embodiment, the present invention addresses the need to precisely adjust a reference current and/or voltage by replacing a conventional current/voltage reference source with a digital-to-analog (D/A) converter. A select switch or mechanism is preferably coupled to the input of the D/A converter and operatively presents a digital input word to the D/A converter by selectively reading the digital word from at least one of a data register and a fuse register. The data register is preferably used during testing of the overall current or voltage reference by iteratively trying various digital input codes while concurrently measuring the analog output signal from the D/A converter until the output signal sufficiently matches a predetermined output value.

Abstract: An interface module includes a high density analog interface (HAI) for electrical interconnection between a programmable logic controller (PLC) and an analog to digital converter (ADC) or a digital to analog converter (DAC). The HAI includes a single application specific integrated circuit having a data scaling function block, a diagnostics function block configured to verify functionality of said scaling function block, a self-calibration function block configured to compensate for drift in said ADC, and a shared interface function block configured to electronically connect said module with a programmable logic controller (PLC).

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: A relatively compact trimming circuit for hypothetically breaking a fuse includes a resistance bypass circuit connected to a node between a resistor and a fuse. The bypass circuit selectively performs ordinary breakage and hypothetical breakage of the fuse in accordance with a control signal and a data signal. An output changeover circuit connected to the node generates a first output signal in accordance with a state of the fuse during the ordinary breakage. The output changeover circuit generates a second output signal in accordance with the data signal during the hypothetical breakage.

Abstract: A self-trimming current source for used in a switched current source DAC is made from a fixed current source and a variable current source, which are connected in parallel to provide a total output current. The total output current is automatically calibrated by temporarily switching one side of the self-trimming current source to a measurement circuit. Based on the measured value, the variable current source is adjusted to make the total output current equal to a predetermined value. The fixed current source is implemented with a complementary pair of field-effect transistors (FETs) connected in a cascode connection, with the two drain terminals presenting high impedances to the circuitry to which they are connected. A DAC typically includes a plurality of self-trimming current sources, each of which is calibrated during each DAC conversion cycle.

Abstract: A digital to analog converter has a decoder configured to select weighted decoding elements in a decoding network. The decoded outputs increase in steps by a mathematical progression as a function of the value of the input to the decoder. A calibration circuit adjusts the value of the digital input code received by the decoder to achieve a calibration function. In a programmable resistor embodiment, the value of the resistance selected by subsequent digital codes increases by a constant ratio. An adder is used to add an offset value to the digital input, thereby shifting the value of the resistance selected by the decoder to compensate for fabrication variances.