Abstract: A push pull digital-to-analog converter circuit configuration improves the signal-to-noise ratio when used in the common bipolar (both positive and negative) mode of operation, thereby improving its absolute accuracy. Digital data is supplied to a data buffer which includes an inverter. The inverter supplies the data to one of a pair of push pull connected DACS, referred to as dual DACS. The buffer supplies the data to the other DAC without inversion. The outputs of the pair of DACS are combined by an op-amp circuit which takes the two analog outputs from those circuits and combines them while the push pull circuits are opposed so noise is reduced and accuracy of the conversion is enhanced.

Abstract: A digital-to-analog (D/A) converter for converting a n-bit digital 2's complement signal to an analog signal. The D/A converter consists of a controller, a capacitor array, and a switch array. The controller operates to convert a 2's complement digital input signal into a 1's complement digital signal. The capacitor array consists of (n-1) capacitors each being connected at one electrode to a common output terminal. The switch array consists of (n-1) switches each connected individually to the remaining electrodes of the (n-1) capacitors. The switch array applies either one of a first or a second reference voltage to the (n-1) capacitors in response a second controller signal. An additional capacitor and switch are connected to the capacitor and switch arrays which serve to convert a digital signal from 2's complement to 1's complement.

Abstract: A digital voltmeter which converts an input signal having an amplitude to be measured into a digital signal from which a series of pulses is developed having a duty cycle which is proportional to the amplitude of the input signal. These pulses are supplied are supplied to a digital-to-analog converter which develops an analog signal having an amplitude proportional to the duty cycle of the pulses and is compared with the input signal to stabilize the digital signal at a value corresponding to the amplitude of the input signal.

Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense.

Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

Abstract: In a half-flash analogue to digital converter (ADC) for balanced signals, d.c. offset compensation is provided by means of two negative feedback arrangements 510 and 520. A first compensating signal LOFF is the time-average of the output of the middle comparator MC17 of the coarse converter stage and provides compensation of offsets in the most significant bits (MSB) of the output. A second compensating signal COFF is generated by an additional comparator MC34 to effect compensation of offsets re-introduced when a difference amplifier 404 forms the residual signal V.sub.LSB for the input to the fine converter stage.

Abstract: An ultra-fast high resolution digital-to-analog converter (DAC) converts a digital input code into a corresponding analog output voltage. The DAC has an inherent low impedance bipolar output.In one embodiment, the DAC includes a resistor network coupled to a voltage source for providing a plurality of reference voltages. The DAC comprises a chain of capacitor/switch links each coupled via a pair of terminals, wherein the DAC output voltage appears across the chain. Each capacitor/switch link includes a capacitor, is responsive to a respective bit of the DAC input code and operates to couple the capacitor across the terminals when the bit is high, and connect the terminals when the bit is low. The respective reference voltages are also applied to the capacitors which are discharged only due to parasitic effects. The on-resistances of all individual switches and values of the capacitors employed in the DAC are insignificant.