Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: An image processor includes a readout arranged to read out an M-bit image data word from an image sensor pixel array and an adder arranged to add a noise contribution to the image data word to obtain a dithered M-bit word. A dither processor is arranged to derive correction data having a word size of M+1 bits from a combination of a plurality of M-bit reference words. The noise contribution are derived from said correction data, wherein different correction data are derived for different groups of pixels, each different group of pixels is associated with a specific pixel value DC shift.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: A dynamic dithering method is provided for improving linearity in analog-to-digital converters.

Abstract: The present invention provides a data processing system which can increase resolution and which has excellent tracking with respect to the switching of a conversion range and is small in conversion error.

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.

Abstract: An analog-to-digital converter (ADC) system and method. The ADC system in accord with one embodiment includes a sampling digital-to-analog converter configured to sample a combination of an analog signal value and an analog dither value, and a control circuit comprising a mismatch-shaping encoder. The control circuit is configured to sequentially apply a plurality of digital codes to the sampling digital-to-analog converter during an analog-to-digital conversion operation to derive a digital code representing the combination of the analog signal value and the analog dither value. Several embodiments are presented.

Abstract: A digital delta sigma modulator includes an input integration stage, a resonating stage, a quantizer, and a plurality of feedback paths operably coupled to the quantizer, the input integration stage, and the resonating stage. The input integration stage is operably coupled to integrate a digital input signal to produce an integrated digital signal, wherein the input integration stage has a pole at substantially zero Hertz. The resonating stage is operably coupled to resonate the integrated digital signal to produce a resonating digital signal, wherein the resonating stage has poles at a frequency above zero Hertz. The quantizer stage is operably coupled to produce a quantized signal from the resonating digital signal.

Abstract: An analog-to-digital converting circuit includes a first comparison circuit configured to compare a first analog signal associated with a first digital signal with an analog input signal and output a first selection signal based on a result of the comparison, a second comparison circuit configured to compare a second analog signal associated with a second digital signal with the analog input signal and output a second selection signal based on a result of the comparison, and a selection circuit configured to generate intermediate digital signals associated with the first digital signal and output one of the intermediate digital signals as the first digital signal and another of the intermediate digital signals as the second digital signal, based on the first selection signal and the second selection signal.

Abstract: A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.

Abstract: A method includes operating on a sigma-delta modulated signal to reduce a dither signal component in one of a first signal and a second signal, the first signal being an integer portion corresponding to a digital frequency ratio and the second signal corresponding to a fractional portion of the digital frequency ratio. In at least one embodiment of the method, the operation is performed digitally in a frequency synthesizer.

Abstract: A sigma delta modulator may include a loop filter and an adder configured to accept an output of the loop filter and a dither input signal. The adder may be further configured to combine the output of the loop filter and the dither input signal into a combined output signal. The sigma delta modulator may further include a quantizer configured to accept the combined output signal from the adder, and quantize the combined signal into a quantizer output signal. The sigma delta modulator may further include a first subtractor configured to accept the quantizer output signal and subtract the dither input signal from the quantizer output signal.

Abstract: A sigma-delta analog-to-digital converter (“?? ADC”) may include a loop filter, ADC, a feedback digital-to-analog converter (“DAC”), and a control circuit. The feedback DAC may include several unit elements (resistors, capacitors, or current sources) that, ideally, are identical to each other but vary due to mismatch errors introduced during manufacture. Mismatch errors may introduce signal errors that generate undesirable noise frequencies and non-linearities in a ?? ADC output signal. Embodiments of the present invention provide a stability corrected second order shuffler that allows for the shaping of the frequency response by the ?? ADC to reduce the effect of the mismatch error between DAC unit elements. The second order shuffler may include accumulation correctors, to suppress saturation for accumulators within the shuffler. The suppression may compress the range of accumulation values for each accumulator while maintaining context for the values to stabilize operation of the second order shuffler.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: A resolution detector may be used in conjunction with an ADC to identify unresolved bits in a raw digital output of the ADC. Bits that have been properly resolved by the ADC may be distinguished from those that have not been successfully resolved, because of time limitations or other reasons. Each bit that has not been successfully resolved may be classified and referred to as an unresolved bit. If there are any unresolved bits detected in a sampling cycle, dither may then be incorporated in the raw digital output to compensate for the unresolved bits in that cycle. The dither may be added to the raw digital output of the ADC to eliminate any missing codes in the processed digital output codes or the dither may be substituted for the unresolved bits in raw digital output to generate the processed digital output.

Abstract: An image processing device includes a storing unit for storing a dither matrix. The dither matrix has a plurality of dot regions divided into a plurality of sub-matrices. A creating unit is configured to create binary image data by comparing an input value to threshold values of each sub-matrix. The plurality of sub-matrices includes a first sub-matrix having a first threshold value smallest among threshold values in the first sub-matrix; a second sub-matrix having a plurality of threshold values that are smaller than the first threshold value and are arranged adjacent to each other; a third sub-matrix; having a second threshold value largest among threshold values in the third sub-matrix; and a fourth sub-matrix having a plurality of threshold values that are larger than the second threshold value and are arranged adjacent to each other.

Abstract: A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value.

Abstract: A process variable transmitter is used to measure a process variable, and, in doing so, dynamically changes the resolution of the A/D converter based upon the measured value of the analog input signal. This can be done by automatically adjusting the configurable resolution gain adjustment based on the value of the analog signal being measured, by normalizing the input signal being measured so that it is centered in an optimal resolution window of the A/D converter, or by adjusting a voltage reference provided to the A/D converter.

Abstract: An A/D conversion device has means for generating a control clock signal having a cycle that is an integral multiple of a cycle of a reference clock signal; means for generating a shift voltage which varies every cycle of the reference clock signal while the cycle of the control clock signal is taken as one cycle, means for offsetting an analog signal by the shift voltage, means for A/D converting the offset analog signal every cycle of the reference clock signal signal, and means for averaging outputs from the A/D converter every cycle of the control clock signal.

Abstract: A method and a corresponding device for reducing inter-channel coupling in a circuit having a plurality of channels includes injecting a randomly determined amount of dither into a first channel of a circuit having a plurality of channels, and after injecting the dither, obtaining an output signal of a second channel in the plurality of channels. A correlation value indicating a degree of correlation between the injected dither and the output signal is determined, and an amount of charge applied to the second channel due to cross-coupling with the first channel is reduced. The amount of the reduction is calculated as a function of the correlation value.

Abstract: A method and device involve a circuit having a switched capacitor network that is switchably connected to an input signal. A randomly determined amount of dither is injected into a circuit having a switched capacitor network that is switchably connected to an input signal. After injecting the dither, at least one correlation value is determined. The correlation value(s) indicates a degree of correlation between the injected dither and an output of the circuit. Distortion caused by an amount of charge kicked back into the circuit when the switched capacitor network is reconnected to the input signal may then be reduced. The reduction is calculated as a function of the correlation value(s).

Abstract: Circuits and methods for converting a signal from analog to digital. A random number generator provides a random number to a memory. The memory is preconfigured to include codes of predetermined digital to analog (DAC) configurations that provide the maximum amount of DAC gradient suppression. At least one Flash reference generation DAC (FRGD) has an input coupled to the memory unit and an output providing a reference voltage level for its respective Flash comparator. The Flash comparators compare the analog input signal to their respective reference voltage and provide a digital output signal based on the comparison.

Abstract: Mental influence detectors and corresponding methods are useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector includes a source of non-deterministic random numbers, a converter to convert a property of numbers, a processor to accept converter output and to produce an output signal representative of an influence of mind. The processor output signal contains fewer numbers than the input. A quantum computer includes a physical source of entropy to generate output numbers; a source of test numbers; a measurement processor to accept output numbers and to measure a relationship between process numbers and at least one test number to produce an output representative of an influence of mind.

Abstract: An AD conversion apparatus includes a shift signal generating portion configured to generate n shift signals (n is a natural number greater than one) of which amplitudes are different from each other; a shift signal controlling portion configured to control the shift signal generating portion; a compounding portion configured to compound input analog signal and the n shift signals sequentially into n first signals; an AD converting portion configured to execute AD conversion to convert the n first signals into n second signals; and a signal processing portion configured to calculate an average of the n second signals to generate output digital signal.

Abstract: A digital-to-analog converter is disclosed. The converter includes a gradient correction module that generates a correction term based on a model of gradient error. The correction term is then applied to the signal path in the digital domain or applied to the output of the digital-to-analog converter in the analog domain. The model used to generate the correction term is based on a vertical gradient error in the array of current source elements, which may be modelled and calibrated using a second-order polynomial. Further, a digital-to-analog converter having a Nyquist DAC and an oversampled DAC is disclosed. When the oversampled DAC is enabled, the resolution of the Nyquist DAC may be increased while slowing the conversion rate.

Abstract: A system and method for controlling a power converter includes a digital-to-analog converter (DAC) and ramp generator for generating a reference current command. The DAC is configured to decrement (or increment) to a next state after a fixed number of clock pulses have occurred. The reference current command controls an output of the power converter. Means are provided for delaying an output of the DAC for a number of clock pulses less than the fixed number to increase a resolution of the DAC.

Abstract: A delta-sigma A/D converter having plural input channels comprises a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

Abstract: A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.

Abstract: A process variable transmitter is used to measure a process variable, and, in doing so, dynamically changes the resolution of the A/D converter based upon the measured value of the analog input signal. This can be done by automatically adjusting the configurable resolution gain adjustment based on the value of the analog signal being measured, by normalizing the input signal being measured so that it is centered in an optimal resolution window of the A/D converter, or by adjusting a voltage reference provided to the A/D converter.

Abstract: In one embodiment, an apparatus includes a first capacitor system and a second capacitor system. Each capacitor system comprises one or more engaged capacitors from respective pluralities of selectively engagable capacitors. The first capacitor system and second capacitor system are respectively selectively coupled to a first reference voltage and a second reference voltage. The apparatus further includes a switch configured to transfer charge between the first capacitor system and the second capacitor system when the switch is closed such that the first capacitor system and the second capacitor system each store the same first voltage. The apparatus further includes a node coupled to the first capacitor system, the second capacitor system, and a first input of a differential amplifier of an analog to digital converter. The node is configured to bias the differential amplifier to the first voltage.

Abstract: Various embodiments of the present invention provide systems, apparatuses and methods for performing analog to digital conversion. For example, an analog to digital converter circuit is discussed that includes an analog input, a number of analog to digital converters and a generalized beamformer. The analog to digital converters are operable to receive the analog input and to yield a number of digital streams. Each of the analog to digital converters samples the analog input with different phase offsets. The generalized beamformer is operable to weight and combine the digital streams to yield a digital output.

Abstract: Techniques and devices provide analog-to-digital conversion at two or more signal frequencies or frequency bands and can be used to construct multi-mode analog-to-digital converters in various circuits, including receivers and transceivers for wireless communications and radio broadcast environments. Adjustable analog-to-digital converters based on the described techniques can be configured to adjust circuit parameters to adapt the technical specifications of different input signals at different signal frequencies or frequency bands, such as FM, HD-radio, and DAB radio signals in radio receiver applications.

Abstract: A delta-sigma modulator (100) including a dithering capability for eliminating idle tones is provided according to the invention. The delta-sigma modulator (100) includes a bitstream converter (107) configured to generate a digital signal output substantially corresponding to an analog signal input, a periodicity detector (111) coupled to the bitstream converter (107) and configured to detect periodicity in the digital signal output, and a dithering sequence generator (116) connected to and activated by the periodicity detector (111). The dithering sequence generator (116) generates a dithering sequence. The delta-sigma modulator (100) further includes a pulse-width modulation (PWM) generator (119) coupled to the dithering sequence generator (116) and receiving the dithering sequence. The PWM generator (119) modulates the dithering sequence onto the analog signal input of the delta-sigma modulator (100) as a dithering signal.

Abstract: A resolution detector may be used in conjunction with an ADC to identify unresolved bits in a raw digital output of the ADC. Bits that have been properly resolved by the ADC may be distinguished from those that have not been successfully resolved, because of time limitations or other reasons. Each bit that has not been successfully resolved may be classified and referred to as an unresolved bit. If there are any unresolved bits detected in a sampling cycle, dither may then be incorporated in the raw digital output to compensate for the unresolved bits in that cycle. The dither may be added to the raw digital output of the ADC to eliminate any missing codes in the processed digital output codes or the dither may be substituted for the unresolved bits in raw digital output to generate the processed digital output.

Abstract: An embodiment of an analog-to-digital converter system is described wherein an analog voltage signal Vin(t) is provided by an input amplifier. The analog signal Vin(t) has a predetermined full-scale range that is less wide than a reference voltage (Vref) range used by a downstream ADC to derive a first digital (numerical) representation D1(k) of a sampled value Vin(k) of the analog signal Vin(t). The first digital representation has N bits. A digital circuit then converts the N-bit D1(k) code to a second numerical representation D2(k) of the sampled analog voltage Vin(k) with respect to the full-scale range of the ADC system. The D2(k) code has P bits of resolution, which may be less than N bits. The P-bit D2(k) code representing Vin(k) is the output of the ADC system. Therefore, the width of the reference voltage range applied to the ADC is greater than the width of the system's full-scale range at the output of the system.

Abstract: A Digital-to-Analog Converter (DAC) produces an analog reference value from a first reference input. The analog reference value and an output value are used to produce an analog error signal. An Analog-to-Digital Converter (ADC) converts the analog error signal to a digital value. The ADC has higher level of resolution than the DAC. An error encoder adjusts the digital value to produce a digital error value using a second reference input.

Abstract: In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.

Abstract: Piecewise conversion of an analog input signal is performed utilizing a plurality of relatively lower bit resolution A/D conversions. The results of this piecewise conversion are interpreted to achieve a relatively higher bit resolution A/D conversion without sampling frequency penalty.

Abstract: Systems and methods for improving resolution of low-noise signals in an analog-to-digital conversion circuit. A simple, low cost pseudo-noise generating circuit is disclosed that, when connected to the signal conditioning circuitry of A/D conversion circuit, adds pseudo-noise to an analog input voltage signal. Additional pseudo-noise is beneficial for improving the resolution of analog-to-digital conversion when oversampling and summing or averaging are used in post-conversion processing operations. The circuit is composed of a plurality of resistors configured in at least two parallel branches. An individually switchable voltage source output is connected to each branch. A resulting analog voltage can be measured at a common termination point for the branches, depending on the combination of switchable voltage source output turned on, and the branch to which the voltage output is applied.

Abstract: A reference voltage generation circuit generates a reference voltage and outputs it to an amplifier reference voltage line. A power-supply-noise adding circuit adds power supply noise superimposed on a power supply to the reference voltage generated by the reference voltage generation circuit. A differential amplifier amplifies a difference between a voltage of a vertical signal line and a voltage of an amplifier reference voltage line and outputs the amplified voltage.

Abstract: A voltage control signal at a voltage control signal input terminal is used to adjust an output frequency of an oscillator circuit. The voltage level of the voltage control signal is converted in a one-bit analog-to-digital converter (ADC) to a digital output indicative of the voltage level. Successive digital representations of the voltage level of the voltage control signal are upsampled to generate upsampled blocks of data. A dither circuit inserts a digital dither in the upsampled blocks of data to generate dithered upsampled data, which is used to generate a control signal for a feedback divider of a phase-locked loop circuit and thereby adjust the output frequency.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. As an example, a circuit for converting analog signals to digital signals is disclosed. The circuit includes a variable gain amplifier circuit, an analog to digital converter circuit, and a summation circuit. The variable gain amplifier circuit is operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output. The analog to digital converter circuit is operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample. The summation circuit is operable to combine the first digital sample and the second digital sample.

Abstract: According to an embodiment, an analog-to-digital converter (ADC) including an ADC unit, a clock-phase control unit, a multiplexer, and a digital-output processing unit is provided. The digital-output processing unit inputs digital outputs of the ADC unit to either an averaging circuit or the multiplexer depending on the specified conversion speed and the specified conversion accuracy, or inputs the digital outputs of the ADC unit to the averaging circuit and the multiplexer in this order, and outputs ADC digital signals with the specified conversion speed and the specified conversion accuracy.

Abstract: A signal-linearization system and method reduces nonlinear distortions in a digitized signal generated by an analog-to-digital converter (ADC) when converting an analog input signal from analog to digital form. A signal adder adds a dither waveform to the analog input signal. An ADC includes sample-and-hold (S/H) circuitry and quantizer circuitry. The ADC converts the analog input signal with the added dither waveform into a digitized signal. The dither waveform operates to suppress nonlinear distortions attributed to the quantizer circuitry. A linearizer processor performs nonlinear equalization (NLEQ) on the digitized signal to suppress nonlinear distortions attributed to the S/H circuitry. A dither waveform removal module removes a digital counterpart of the dither waveform from the digitized signal.

Abstract: A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

Abstract: A multi-bit (M-bit, M>1) Sigma-Delta digital-to-analog converter (DAC) with a variable resolution multi-bit quantizer that has its digital value inputs that are truncated or rounded to a resolution that follows a random or pseudo-random sequence to provide automatic dynamic dithering for removing undesired idle tones in the analog output of the Sigma-Delta DAC. Random numbers N(n) between 1 and M are provided, and M?N(n) least significant bits in each M-bit digital value at the output of the quantizer are forced to zero with a digital truncator or rounder. The random numbers N(n) may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.

Abstract: In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency fe and coded on NB bits, a second main output digital signal s?(t) is represented on NMSB bits also being available at the output. At least three processings are applied successively to the outputs, a first processing carrying out a demodulation by a frequency f0 and a decimation of factor N in an independent manner, z second processing carrying out an improvement of the resolution and a third processing carrying out a correction of the distortions. These three processings are carried out after decimation. A sigma-delta modulator implements the method.

Abstract: In the field of direct mind-machine interactions, prior art devices and methods do not provide sufficiently fast and reliable results. Mental influence detectors (100, 140, 400, 430) and corresponding methods provide fast and reliable results useful for detecting an influence of mind and hidden or classically non-inferable information. An anomalous effect detector (100) includes a source (104) of non-deterministic random numbers (110), a converter (114) to convert a property of numbers, a processor to accept converter output (118) and to produce an output signal (124) representative of an influence of mind. The processor output signal (124) contains fewer numbers than the input (110).